Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Budapest University of Technology and Economics

Abstraction Levels in the Digital System Modeling

Dr. Péter Horváth

Department of Electron Devices

February 8, 2017

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Contents

Contents

handling complexity – abstraction levels in digital system modeling

the Gajski-Kuhn Y-diagram – function representations, modeling
means, structural elements
a detailed discussion of the different abstraction levels and their
optimization goals
design flow of digital systems
top-down and bottom-up design approaches
top-down and bottom-up methods in digital design
a detailed discussion of the digital system design flow – from the
viewpoint of the system designer
additional readings

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Handling complexity –
Abstraction levels

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

The Gajski-Kuhn Y-diagram

The Gajski-Kuhn Y-diagram

The GK diagram is an expressive representation of the abstraction

levels.
The circles represent the abstraction levels and the arrows represent
the aspects they are examined from.

register transfers

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

Design objectives on the different abstraction levels

System – defining design partitions and their interfaces

Algorithm – behavioral modeling with high-level programming
languages
RTL (register-transfer level) – defining "microarchitecture",
separating control and datapath
Gate – defining the behavior of RTL components with Boole-
equations
Circuit – implementing the behavior of the logic gates with
transistor-based structures
Device – constructing small, fast, and low-power transistors
Technology – optimizing the technology parameters that influence
the device construction

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

System-level

The main objective is to define the partitions of the system and the
communication methods and interfaces between the partitions and
the outside world.
The object-oriented paradigm is widely used in system-level design.
design entity examples: GPCPU1 , GPGPU2 , DSP3 , memory (cache,
operative memory, mass storage), I/O subsystem, peripheral
controller
considerations on system-level
number of the microprocessors
topology of the memory subsystem in multiprocessor systems
memory hierarchy (cache levels and sizes)
communication models (hand-shake, mailbox, FIFO etc.)

1 general-purpose central processing unit

2 general-purpose graphics processing unit
3 digital signal processor

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

Algorithm-level

High-level programming language representation of the

subsystems’ behavior.
Once the algorithm-level implementations of the subsystems are
created, the system can be simulated.
The simulation requires high computation capacity, therefore the
efficiencies of the algorithmic models are critical. The most widely
used tools for algorithmic modeling are native C and C++,
supplemented by a set of hardware-oriented class libraries.

algorithm-level (C++) model of a simple RC filter

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

RTL – register-transfer level

The objective of RTL is to describe the data transfers and their
timing between simple functional units with (registers, register files,
arithmetic-logic units etc.)
Separating datapath and control; the datapath includes the
functional units and their interconnections. The control unit
generates control signals with appropriate timing.
data
control inputs
unit
considerations on RTL control
control: single-cycle, multicycle, signals
control
pipeline I/O
internal data-storage structures
(registers, register files)
clocking scheme: frequency, phase
status
signals signal

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

Gate-level

All digital functions – even those containing data storage – can be

represented by a set of interconnected logic gates. Although the
elementary data-storage elements (flip-flops) can be described with
gates, they are considered basic building blocks of gate-level models,
because they have a unique physical realization primitive (they are
not implemented as interconnected logic gates).
considerations on gate-level
handling logical hazards
two-level or multilevel logic realization
gate-level architecture optimization of functional units (e.g. adder:
ripple-carry vs. carry lookahead)

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

Circuit-level

The functionality of a logic gate can be realized by interconnected

transistors. This circuit-level model is a "standard cell".
representations of a standard cell
schematic: a logical network of transistors
layout: a physical realization of the schematic

To simulate a circuit-level
model, the mathematical
models of the transistors (e.g.
Ebers-Moll, Gummel-Poon,
EKV, BSIM3) are required.
considerations on circuit-level
circuit family (ECL, SCL,
static/dynamic CMOS)
topology (e.g. domino
CMOS: alternate/pipeline)

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

Device-level

To improve the computation capacity, power consumption, and

device density of the digital circuits, we need small, fast, and
efficient transistors. The aim of device-level is to optimize the
transistor parameters.

considerations on device-level
threshold voltage, switching
frequency, power
consumption, size etc.
scaling: short-channel and
strait-channel effects,
hot-electron effect,
gate-depletion, latch-up,
preventing or exploiting
quantum-effects (HKMG,
EEPROM)

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Abstraction levels

Technology-level

The aim of technology-level optimization is to analyze the effect of

technological parameters on the physical indices influencing the
device characteristics.
Technological parameters: temperature and duration of diffusion,
energy of implantation, etc.
Physical indices: oxide thickness, conductivity, carrier lifetime and
mobility, dopant density and distribution, etc.

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Design flow of digital systems

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Top-down and bottom-up design approaches

Top-down design method

In the top-down approach the design process starts with a high-level

representation of the system. The high-level model includes
partitions (subsystems) with a specific task. During the design
process the implementations of the subsystems are elaborated; they
are split into components with more specific sub-tasks and more
detailed implementations. The process stops when the components
of the refined design are simple enough to substitute them with an
existing model (practically with an RTL functional unit).

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Top-down and bottom-up design approaches

Bottom-up design method

In the bottom-up approach the designer creates basic functional

units with very simple tasks. Once a sufficient set of elementary
functionalities is constructed, a more complex model can be
prepared with the combination of the simple ones. The design
process stops when the increasingly complex model is able to
implement the desired functionality defined in the specification.

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Top-down and bottom-up design approaches

Top-down and bottom-up methods in digital design

In the digital design the top-down and the bottom-up methods

are both applied. The system designer creates RTL models from
the high-level specification with top-down method but the standard
cells are constructed from circuit-level by the component library
designer with bottom-up approach.

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Digital system design flow – from the viewpoint of the system designer

Step #1. Design partitioning (manual)

concept: The subsystems, their relations and interfaces have to be

outlined. The subsystems are represented as "black boxes".
tools: UML, SystemC TLM4 , MATLAB

specification

4 transaction-level modeling; a C++ class library for system-level modeling

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Digital system design flow – from the viewpoint of the system designer

Step #2. Functional modeling (manual)

concept: The behavior of the subsystems have to be formulated.

tools: high-level programming languages (C, C++, SystemC)

functional model (C++)

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Digital system design flow – from the viewpoint of the system designer

Step #3. RTL design (manual/automated)

concept: A microarchitecture consisting of simple functional units

(registers, register files, arithmetic units, etc.) has to be constructed.
tools: hardware description languages (VHDL, Verilog, SystemC)

functional model

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Digital system design flow – from the viewpoint of the system designer

Step #4. RTL optimization (manual/automated)

concept: There are many microarchitectures implementing the same

functionality. We have to choose one with parameters optimal for
the application.
tools: hardware description languages (VHDL, Verilog, SystemC)

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Digital system design flow – from the viewpoint of the system designer

Step #5. Logic synthesis (automated)

concept: The RTL description is automatically transformed into a

technology and vendor-independent gate-level model.
tools: ISE, Quartus II, LeonardoSpectrum, Precision, Encounter
RTL Compiler

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Digital system design flow – from the viewpoint of the system designer

Step #6. Mapping (automated)

concept: The mapping assigns a specific component library
primitive to the generic resources of the gate-level model. These
library primitives are the basic elements of an ASIC technology (e.g.
AMS 0.35) or an FPGA device family (e.g. Xilinx Spartan3E).
tools: ISE, Quartus II, LeonardoSpectrum, Precision, Virtuoso,
Calibre InRoute

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Digital system design flow – from the viewpoint of the system designer

Step #7. Place & route (automated)

concept: Place: The mapped primitives are assigned to a specific

resource in a device (FPGA) or they are placed into a specific
position of the chip layout (ASIC). Route: The interconnections of
the placed primitives are constructed. The output of the design flow
is a GDSII file (ASIC) including the information required for
manufacturing or a bitstream file (FPGA) including the
configuration memory content of the FPGA device.
tools: ISE, Quartus II, Virtuoso, Calibre InRoute

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Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Additional readings

Additional readings

David Money Harris, Sarah L. Harris – Digital Design and Computer

Architecture
Peter J. Ashenden – Digital Design – An Embedded System
Approach Using VHDL
M. Moris Mano, Charles R. Kime – Logic and Computer Design
Fundamentals
Pong P. Chu – RTL Hardware Design Using VHDL
Thorsten Grötker, Stan Liao, Grant Martin, Stuart Swan – System
Design with SystemC

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