ISSN 2321-8665

Vol.04,Issue.10,
WWW.IJITECH.ORG August-2016,
Pages:1777-1780

A High-Efficiency Mosfet Transformerless Inverter for Non-isolated

Micro-inverter Applications
Y. SUDHAKAR REDDY1, J. NAGARAJUNA BABU2
1
PG Scholar, Dept of EEE, Kottam Karunakar Institute of Technology, Kurnool, AP, India, E-mail: ysrworld@gmail.com.
2
HOD, Dept of EEE, Kottam Karunakar Institute of Technology, Kurnool, AP, India, E-mail: nagmtech307@gmail.com.

Abstract: This paper presents single-phase transformer less

grid-connected inverter that utilizes super junction MOSFETs
to achieve high efficiency for photovoltaic applications. In
proposed inverter due to the splitting structure of inductor
avoids reverse-recovery issues for the main power switches.
High-frequency pulse width modulation switching
commutation and the grid zero crossing instants, improving
the quality of the output ac-current and increasing the
converter efficiency. Also due to two additional AC-sides
switches conducting the currents during the freewheeling
phases so that the photovoltaic array is decoupled from the
grid. This reduces the high-frequency common-mode voltage
leading to minimized ground loop leakage current. This Paper Fig.1. H5 Topology.
describes H5 & H6 transformer less inverter topology. Detail
analysis of proposed transformer less inverter with operation This topology has high conduction losses due to the fact
modes, common mode leakage current analysis and design that the current must conduct through three switches in series
consideration of the proposed transformer less inverter in during the active phase. Another disadvantage of the H5 is
MATLAB simulation model are presented. that the line-frequency switches S1 and S2 cannot utilize
MOSFET devices because of the MOSFET body diode’s slow
Keywords: Microinverter, MOSFET Inverters, Photovoltaic reverse recovery. The slow reverse recovery of the MOSFET
(PV) Inverter, Transformer Less Inverter. body diode can induce large turn-on losses, has a higher
possibility of damage to the devices and leads to EMI
I. INTRODUCTION problems. Shoot-through issues associated with traditional full
Transformerless inverters are widely used in grid-tied bridge PWM inverters remain in the H5 topology due to the
photovoltaic (PV) generation systems, due to the benefits of fact that the three active switches are series-connected to the
achieving high efficiency and low cost. Various transformer dc bus.
less inverter topologies have been proposed to meet the safety
requirement of leakage currents, when no transformer is used
in a grid connected photovoltaic system, a galvanic
connection between the grid and PV array exists. In these
conditions, dangerous leakage currents (common-mode
currents) can appear through the stray capacitance between
the PV array and the ground. In order to avoid these leakage
currents, different inverter topologies that generate no varying
common-mode voltages have been proposed.

II. VARIOUS TRANSFORMERLESS TOPOLOGIES

In recent years, there have been quite a few new
transformers less PV inverters topologies, which eliminate
traditional line frequency transformers to achieve lower cost Fig.2. H6 Topology.
and higher efficiency, and maintain lower leakage current as
H6 Topology uses MOSFETs to decrease the conduction
well. One unipolar inverter topology, H5, as shown in Fig.1,
loss of IGBTs in H5 topology, by splitting S5 of H5 topology
solves the ground leakage current issue and uses hybrid
into two MOSFETs i.e. S5 and S6 in series and operates them
MOSFET and IGBT devices to achieve high efficiency.

Copyright @ 2016 IJIT. All rights reserved.

 Y. SUDHAKAR REDDY, J. NAGARAJUNA BABU
in high-frequency switching, S1−S4 in line grid line frequency transformer less inverter. The prototype of the two-stage non-
switching. Uency switching, S1−S4 in line grid line frequency isolated micro-inverter is shown in Fig. 6, which can be
switching as shown in Fig.2. Drawbacks of this inverter are divided into the high boost ratio non-isolated dc–dc converter
higher conduction loss from four devices in conduction loop. and the proposed transformer less inverter.

III.EXISTING AND PROPOSED SYSTEMS

A. Existing System
There have been quite a few new transformers less PV
inverters topologies, which eliminate traditional line
frequency transformers to achieve lower cost and higher
efficiency, and maintain lower leakage current as well. For
high power- level transformer less inverters, most of them
adopt neutral point clamp (NPC) or T-type three-level inverter
topologies, which require high dc-bus voltage and are not
suitable for low power PV inverter application. For the lower
power level transformer less inverters, most of the innovative
topologies use super junction metal–oxide–semiconductor
field-effect transistor (MOSFET) to boost efficiency. With
super junction MOSFETs, the conduction and switching
losses are lowered. However, with the poor reverse recovery
from MOSFET’s slow body diode, MOSFET-based phase
legs will have a risk of device failure, which is related to high
dv/dt, di/dt and phase-leg shoot through from gating voltage
false trigging on.

B. Proposed System
The proposed transformer less inverter has no dead-time
requirement, simple PWM modulation for implementation,
and minimized high-frequency A 250Whardware prototype
has been designed, fabricated, and tested in two-stage non-
isolated micro inverter application. Experimental results
demonstrate that the proposed MOSFET transformer less
inverter achieves 99.01% peak efficiency at full load
condition and 98.8% CEC efficiency and also achieves around
98% magnetic utilization. Due to the advantages of high
efficiency, low CM voltage, and improved magnetic
utilization, the proposed topology is attractive for two-stage
non-isolated PV micro inverter applications and transformer
less string inverter applications.

Fig.3. Circuit Diagram.
IV. EXPERIMENTAL RESULTS
A 250 W micro-inverter hardware prototype with 380 Vdc
input and 240 V ac output has been designed, fabricated and
tested in the two stage non-isolated micro-inverter to verify
the validity of the proposed high efficiency MOSFET
Fig.4. Operating modes of the proposed transformer less
inverter: (a) positive half-line cycle, S1 and S4 are on, (b)
positive half-line cycle, S1 and S4 are off, free-wheeling
current goes through S5 and D5, (c) negative half-line
cycle, S3 and S2 are on, and (d) negative half-line cycle, S3
and S2 are off, free-wheeling current goes through S6 and
D6.

International Journal of Innovative Technologies

Volume.04, Issue No.10, August-2016, Pages: 1777-1780
 A High-Efficiency Mosfet Transformerless Inverter for Non-isolated Micro-inverter Applications
As shown in Fig.4, Phase-leg splitting inductors only As shown in Fig. 9, the splitting inductors L01 and L04 only
conduct in positive half-line cycle and have 50% utilization, conduct current in the positive half cycle. The voltage
but filter inductors have full utilization. Compared with filter between dc bus negative G and ac grid ground E (VEG) is
inductors, the phase-leg splitting inductors are much smaller. shown in Fig. 10, which has a 60 Hz grid voltage component
The output filter inductor is 4.7 mH with the weight 90 g, the and a dc bias component. The waveform of VEG matches well
phase leg splitting inductor is 0.086 mH in total with the with the calculation results. This indicates nearly zero high-
weight 4 g. Compared with transformer less MOSFET frequency voltage on the PV parasitic capacitor, which means
inverter topologies in which only have 50% utilization of minimized leakage current.
magnetic, the proposed transformer less MOSFET inverter
has 98% utilization of inductance value and 96% utilization of
weight. The output voltage and current waveforms of the
proposed inverter are shown in Fig. 7. As there is no dead-
time requirement for each PWM switching cycle, the
proposed inverter has no duty cycle loss, which means 340 V
dc bus can almost generate 240 V ac sinusoid voltage. Fig. 8
shows the gating signals for all switches. In the positive half
cycle, S1 and S4 are switched simultaneously in high
frequency PWM and S5 is always on; other switches are
always off. In the negative half cycle S2 and S3 are switched
simultaneously in high-frequency PWM and S6 is always on;
other switches are always off.
Fig.7. Output voltage and current waveforms.

Fig.8. PWM gate signals waveforms.

Fig.5. Calculated total loss and efficiency under different
power levels.

Fig.9. Inverter splitting inductor current waveform.

In the experiment, YOKOGAWA WT1600 digital power

Fig.6. Two-hundred-fifty-watt two-stage non-isolated meter is used to measure voltages, currents, and efficiency.
micro-inverter hardware prototype. The test efficiency and the calculated efficiency of proposed

International Journal of Innovative Technologies

Volume.04, Issue No.10, August-2016, Pages: 1777-1780
 Y. SUDHAKAR REDDY, J. NAGARAJUNA BABU
inverter are shown in Fig. 11, which shows 99.01% peak
efficiency at full load 250 W. The CEC efficiency is a
weighted efficiency calculated at 10%, 20%, 30%, 50%, 75%,
and 100% of the full power level. The overall CEC efficiency
of proposed inverter is 98.8%, which is calculated through
𝜂𝐶𝐸𝐶 = 0.04𝜂10% + 0.05𝜂20% + 0.12𝜂30% + 0.21𝜂50%
+ 0.53𝜂75% + 0.05𝜂100 %
Fig.10. Waveforms of voltage between grid ground and
DC ground (VEG).
Fig.11. Efficiency test results of 250 W proposed inverter.
V. CONCLUSION
In this paper study of conventional H5, H6 and Proposed
transformer less inverter has been done. A high efficiency
Proposed Transformerless Inverter for PV grid-connected
power generation systems is simulated and corresponding
simulation results are presented. The main characteristics of
the proposed transformer less inverter are summarized as
follows:
 High efficiency can be achieved by employing super
junction MOSFETs for all switches since their body
diodes are never activated.
 CM leakage current is reduced due to two additional
unidirectional current switches (S5 and S6) which
International Journal of Innovative Technologies
Volume.04, Issue No.10, August-2016, Pages: 1777-1780
decouple the PV array from the grid during the zero
stages.
 For high inverter efficiency, higher switching frequency
(20 KHz) operation is allowed to reduce the output
current ripple and the size of passive components.
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