VLSI Testing

Memory Test

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0286: Testing and Verification of SoC Designs

Lecture 27
Apr 02, 2008 E0286@SERC 1
 RAM Organization
A a x

ROW (X) DECODER

0 0 0

ROW ADDRESS
BUFFERS
. CELL ARRAY
. 64 X 64 Cells
. 4 K Bits

A b0 b0 b
5 a x 63 b63 BIT−LINE PAIRS
5 63
SENSE
DATA IN DATABUS AMPLIFIER
DATA OUT
TRI−STATE
DATABUS TRI−STATE
INPUT y y OUTPUT BUFFER
BUFFERS 0 63
COLUMN (Y) DECODER
R/W
1 s s s11 s11
0 0
R/W COLUMN ADDRESS
R/W2 BUFFERS

CS CONTROL A6 . . . A11

Apr 02, 2008 E0286@SERC 2

 Test Time

Size Number of Test Algorithm Operations

n bits n n × log2n n3/2 n2

1 Mb 0.06 1.26 64.5 18.3 hr

4 Mb 0.25 5.54 515.4 293.2 hr
16 Mb 1.01 24.16 1.2 hr 4691.3 hr
64 Mb 4.03 104.7 9.2 hr 75060.0 hr
256 Mb 16.11 451.0 73.3 hr 1200959.9 hr
1 Gb 64.43 1932.8 586.4 hr 19215358.4 hr
2 Gb 128.9 3994.4 1658.6 hr 76861433.7 hr

Apr 02, 2008 E0286@SERC 3

 SRAM Fault Models

Faults found only in SRAM Model

Open-circuited pull-up device DRF
Excessive bit line coupling capacitance CF

Apr 02, 2008 E0286@SERC 4

 DRAM Only Fault Models

Faults only in DRAM Model

Data retention fault (sleeping sickness) DRF
Refresh line stuck-at fault SAF
Bit-line voltage imbalance fault PSF
Coupling between word and bit line CF
Single-ended bit-line voltage shift PSF
Precharge and decoder clock overlap AF

Apr 02, 2008 E0286@SERC 5

 Fault Modeling
¾ Behavioral (black-box) Model -- State machine
modeling all memory content combinations --
Intractable
¾ Functional (gray-box) Model -- Used
¾ Logic Gate Model -- Not used Inadequately
models transistors & capacitors
¾ Electrical Model -- Very expensive
¾ Geometrical Model -- Layout Model
¾ Used with Inductive Fault Analysis

Apr 02, 2008 E0286@SERC 6

 Functional Model

Apr 02, 2008 E0286@SERC 7

 Simplified Functional Model

Apr 02, 2008 E0286@SERC 8

 Reduced Functional Faults

Fault
SAF Stuck-at fault
TF Transition fault
CF Coupling fault
NPSF Neighborhood Pattern Sensitive fault*

Apr 02, 2008 E0286@SERC 9

 Stuck-at Faults
¾ Test Condition: For each cell, read a 0 and a 1.
A A
¾< /0> (< /1>)
w1 w1
w0
S0 S1
w0

State diagram of a good cell

w1
w0

S0 S1
w1 w0

SA0 fault SA1 fault

Apr 02, 2008 E0286@SERC 10
 Transition Faults
¾ Cell fails to make a 0 → 1 or 1 → 0 transition.

¾ Test Condition: Each cell must have an ↑ transition

and a ↓ transition, and be read each time before
making any further transitions.

¾ <↑/0>, <↓/1>
w1
w0 S0 S1
w0 w1
<↑/0> transition fault
Apr 02, 2008 E0286@SERC 11
 Coupling Faults

¾ Coupling Fault (CF): Transition in bit j (aggressor)

causes unwanted change in bit i (victim)
¾ 2-Coupling Fault: Involves 2 cells, special case of
k-Coupling Fault
¾ Must restrict k cells for practicality
¾ Inversion (CFin) and Idempotent (CFid) Coupling
Faults -- special cases of 2-Coupling Faults
¾ Bridging and State Coupling Faults involve any # of
cells
¾ Dynamic Coupling Fault (CFdyn) -- Read or write on
j forces i to 0 or 1

Apr 02, 2008 E0286@SERC 12

 State Transition Diagram of Two
Good Cells, i and j

w1/ j w0/i, w1/ j

w0/ i, w0/ j
S00 S01
w0/ j
w0/i w1/ i w0/ i w1/ i
w1/ j
S10 S11
w1/ i, w0/ j w1/i, w1/ j
w0/ j

Apr 02, 2008 E0286@SERC 13

 State Transition Diagram for
CFin < ↑ ; ↕ >

w0/ i, w1/ j
w0/ i, w0/ j w0/ j
S00 S01
w1/ j
w0/ i w1/ i w0/ i w1/ i
w1/ j
S10 S11
w1/ i, w0/ j w1/ i, w1/ j
w0/ j

Apr 02, 2008 E0286@SERC 14

 State Coupling Faults (SCF)
¾ Aggressor cell or line j is in a given state y and that
forces victim cell or line i into state x
¾ < 0;0 >, < 0;1 >, < 1;0 >, < 1;1 >

w0/ i, w0/ j w0/ j w0/ i, w1/ j

S00 S01
w1/ j
w0/ i w0/ i w1/ i
w1/ i
w1/ j
S S
10 11
w1/ i, w0/ j w0/ j w1/ i, w1/ j

State coupling fault (SCF) <1 ; 1>

Apr 02, 2008 E0286@SERC 15
 March Test Elements

M0: { March element (w0) }

for cell := 0 to n - 1 (or any other order) do
write 0 to A [cell];
M1: { March element (r0, w1) }
for cell := 0 to n - 1 do
read A [cell]; { Expected value = 0}
write 1 to A [cell];
M2: { March element (r1, w0) }
for cell := n – 1 down to 0 do
read A [cell]; { Expected value = 1 }
write 0 to A [cell];

Apr 02, 2008 E0286@SERC 16

 March Tests
Algorithm Description
MATS { (w0); (r0, w1); (r1) }
MATS+ { (w0); (r0, w1); (r1, w0) }
MATS++ { (w0); (r0, w1); (r1, w0, r0) }
MARCH X { (w0); (r0, w1); (r1, w0); (r0) }
{ (w0); (r0, w1); (r1, w0);
MARCH C- (r0, w1); (r1, w0); (r0) }
{ (w0); (r0, w1, w0, w1); (r1, w0, w1);
MARCH A (r1, w0, w1, w0); (r0, w1, w0) }
MARCH Y { (w0); (r0, w1, r1); (r1, w0, r0); (r0) }
{ (w0); (r0, w1, r1, w0, r0, w1);
MARCH B (r1, w0, w1); (r1, w0, w1, w0);
(r0, w1, w0) }
Apr 02, 2008 E0286@SERC 17
 Address Decoder Faults
• Address decoding error assumptions:
– Decoder does not become sequential
– Same behavior during both read and write
• Multiple ADFs must be tested for
• Decoders can have CMOS stuck-open faults

Cx Ax Cx
Ax Cx
Ay Cy Ay

Fault 1 Fault 2 Fault 3 Fault 4

No Cell No Address to Multiple Cells Multiple Addresses
Accessed for Ax Access Cell Cx Accessed with Ay for Cell Cx

Apr 02, 2008 E0286@SERC 18

 Theorem
• A March test satisfying conditions 1 & 2 detects all
address decoder faults.
• ... Means any # of read or write operations
• Before condition 1, must have wx element
– x can be 0 or 1, but must be consistent in test

Condition March element

1 (rx, …, w x )

2 (r x , …, wx)
Apr 02, 2008 E0286@SERC 19
 March Test Fault Coverage

Algorithm SAF ADF TF CF CF CF SCF

in id dyn
MATS All Some
MATS+ All All
MATS++ All All All
MARCH X All All All All
MARCH C- All All All All All All All
MARCH A All All All All
MARCH Y All All All All
MARCH B All All All All

Apr 02, 2008 E0286@SERC 20

 March Test Complexity

Algorithm Complexity
MATS 4n
MATS+ 5n
MATS++ 6n
MARCH X 6n
MARCH C- 10n
MARCH A 15n
MARCH Y 8n
MARCH B 17n

Apr 02, 2008 E0286@SERC 21

 MATS+ Example
Cell (2,1) SA0 Fault
0 00 1 11 0 00
0 00 1 11 0 00
0 0 0 1 1 1 0 0 0
(a) Good machine (b) Good machine (c) Good machine
after M0. after M1. after M2.
0 00 1 11 0 00
0 00 0 11 0 00
0 0 0 1 1 1 0 0 0
(d) Bad machine (e) Bad machine (f) Bad machine
after M0. after M1. after M2.

MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }

Apr 02, 2008 E0286@SERC 22

 MATS+ Example
Cell (2, 1) SA1 Fault

0 00 1 11 0 00
0 00 1 11 0 00
0 0 0 1 1 1 0 0 0
(a) Good machine (b) Good machine (c) Good machine
after M0. after M1. after M2.
0 00 1 11 0 00
1 00 1 11 1 00
0 0 0 1 1 1 0 0 0
(d) Bad machine (e) Bad machine (f) Bad machine
after M0. after M1. after M2.

MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }

Apr 02, 2008 E0286@SERC 23

 MATS+ Example
Multiple AF: Addressed Cell Not Accessed;
Data Written to Wrong Cell
¾ Cell (2,1) is not addressable
¾ Address (2,1) maps onto (3,1), and vice versa
¾ Cannot write (2,1), read (2,1) gives random data
0 00 1 11 0 00
0 00 1 11 0 00
0 0 0 1 1 1 0 0 0
(a) Good machine (b) Good machine (c) Good machine
after M0. after M1. after M2.

0 00 1 11 1 11 0 00
X00 X00 X11 X00
0 0 0 1 0 0 1 1 1 0 0 0
(d) Bad machine (e) Bad machine (f) Bad machine (g) Bad machine
after M0. after M1 for cell (2, 1). after M1. after M2.
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1), w0 }
Apr 02, 2008 E0286@SERC 24
 Memory BIST

Apr 02, 2008 E0286@SERC 25

 LFSR and Inverse Pattern LFSR

™NOR gate forces LFSR into all-0 state

¾ Get all 2n patterns

¾ Normal LFSR: ¾ Inverse LFSR:

G ( x) = x3 + x + 1 G ( x) = x3 + x2 + 1
Apr 02, 2008 E0286@SERC 26
 Up / Down LFSR
• Preferred memory BIST pattern generator
ƒ Satisfies March test conditions

0 M
0 M U
1 X
U
1 X D Q 0 M D Q 0 M D Q
U U
X0 1 X X1 1 X X2

Up/Down
Apr 02, 2008 E0286@SERC 27
Up / Down LFSR Pattern Sequences

Up Counting Down Counting

000 000
100 001
110 010
111 101
011 011
101 111
010 110
001 100

Apr 02, 2008 E0286@SERC 28

 Mutual Comparator
™ Test 4 or more memory arrays at same time:
¾ Apply same test commands & addresses to all 4
arrays at same time
¾ Assess errors when one of the di (responses)
disagrees with the others

Apr 02, 2008 E0286@SERC 29

 Mutual Comparator System

¾ Memory BIST with mutual comparator

¾ Benefit: Need not have good machine response

stored or generated
Apr 02, 2008 E0286@SERC 30
 SRAM BIST with MISR
• Use MISR to compress memory outputs
• Control aliasing by repeating test:
ƒ With different MISR feedback polynomial
ƒ With RAM test patterns in reverse order
• March test:
{ (w Address); (r Address); (w Address);
(r Address); (r Address); (w Address);
(r Address); (r Address) }
• Not proven to detect coupling or address decoder
faults
Apr 02, 2008 E0286@SERC 31
 BIST System with MISR

Apr 02, 2008 E0286@SERC 32

 LFSR and Inverse Pattern LFSR

™NOR gate forces LFSR into all-0 state

¾ Get all 2n patterns

¾ Normal LFSR: ¾ Inverse LFSR:

G ( x) = x3 + x + 1 G ( x) = x3 + x2 + 1
Apr 02, 2008 E0286@SERC 33
 Up / Down LFSR
• Preferred memory BIST pattern generator
ƒ Satisfies March test conditions

0 M
0 M U
1 X
U
1 X D Q 0 M D Q 0 M D Q
U U
X0 1 X X1 1 X X2

Up/Down
Apr 02, 2008 E0286@SERC 34
Up / Down LFSR Pattern Sequences

Up Counting Down Counting

000 000
100 001
110 010
111 101
011 011
101 111
010 110
001 100

Apr 02, 2008 E0286@SERC 35

 Mutual Comparator
™ Test 4 or more memory arrays at same time:
¾ Apply same test commands & addresses to all 4
arrays at same time
¾ Assess errors when one of the di (responses)
disagrees with the others

Apr 02, 2008 E0286@SERC 36

 Mutual Comparator System

¾ Memory BIST with mutual comparator

¾ Benefit: Need not have good machine response

stored or generated
Apr 02, 2008 E0286@SERC 37
 SRAM BIST with MISR
• Use MISR to compress memory outputs
• Control aliasing by repeating test:
ƒ With different MISR feedback polynomial
ƒ With RAM test patterns in reverse order
• March test:
{ (w Address); (r Address); (w Address);
(r Address); (r Address); (w Address);
(r Address); (r Address) }
• Not proven to detect coupling or address decoder
faults
Apr 02, 2008 E0286@SERC 38
 BIST System with MISR

Apr 02, 2008 E0286@SERC 39

 Thank You

Apr 02, 2008 E0286@SERC 40