LAMPIRAN

Gambar 1 Simulasi Decorder 2 to 4

Input Output

S1(SW1) S0(SW0) D1 D2 D3 D4

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1
Tabel 1 Hasil Simulasi Decorder 2 to 4
 Gambar 2 Simulasi Demultiplexer 1 to 4

Input Output
S1(SW1) S0(SW2) I(SW3) D1 D2 D3 D4
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
Tabel 2 Hasil Simulasi Demultiplexer 1 to 4
 Gambar 3 Simulasi Multiplexer 4 to 1

Input Output
S1(SW1) S0(SW2) I0(SW3) I1(SW4) I2(SW5) I3(SW6) Y(D1)
0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 0 0
0 1 0 1 0 0 1
1 0 0 0 0 0 0
1 0 0 0 1 0 1
1 1 0 0 0 0 0
1 1 0 0 0 1 0
Tabel 3 Hasil Simulasi Multiplexer 4 to 1