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Home Ass III

This document contains 10 questions for a homework assignment on design for testability, yield and reliability. The questions cover topics like computing test vectors to detect stuck-at faults using Boolean difference and the D-algorithm, levelizing and drawing s-graphs, March element types and fault coverage, designing a March test for a register file, calculating chip leakage currents, and generating tests for leakage faults. Students are asked to answer each question, which involves tasks like fault simulation, test pattern generation, and calculations related to testing chips for defects.

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Vaidhyanadhan Deepak
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156 views2 pages

Home Ass III

This document contains 10 questions for a homework assignment on design for testability, yield and reliability. The questions cover topics like computing test vectors to detect stuck-at faults using Boolean difference and the D-algorithm, levelizing and drawing s-graphs, March element types and fault coverage, designing a March test for a register file, calculating chip leakage currents, and generating tests for leakage faults. Students are asked to answer each question, which involves tasks like fault simulation, test pattern generation, and calculations related to testing chips for defects.

Uploaded by

Vaidhyanadhan Deepak
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Visvesvaraya National Institute of Technology

Center for VLSI and Nanotechnology


ENL 507 Design for Testability, Yield and Reliability

Home Assignment No. 3


Due: 9.00 am 23rd Oct 2018

Each question carries 5 Marks

Q.1 Using the circuit shown in Figure, compute the set of all vectors that can detect each of the
following faults using Boolean difference:
a. a/1
b. b1/1
c. e/0
d. e2/1

Q.2 Using the circuit shown in Figure Q.1, use the D algorithm to compute a vector for the fault b/1.
Repeat for the fault e/0.
Q.3 Repeat Q.2 using PODEM instead of the D algorithm.
Q.4 Compute drivabilities for all lines in the circuit of Figure for the fault B s-a-0.

Q.5 Redefine the s-graph by including PIs and POs as additional vertices. Levelize the graph starting
from PI vertices using the minimum distance rule. Draw the new types of levelized s-graphs for
circuits of Figures 8.9 and 8.13. What do the depths of these graphs represent in terms of the
length of test sequences?
Q.6. Do the following four March tests have identical fault coverage?

Q.7. Determine the March element type in the following procedure. What faults can it detect?

Q.8 A register file has 16 registers with 4 address lines (A0,A1, A2, and A3). Design a simple March
test to detect the SA0 fault on address line A1.

Q.9 We use BIC sensors for on-chip IDDQ testing. Each transistor on the chip draws a leakage current
of 0.01 nA around its drain, each transistor also has a sub-threshold conduction current of 0.005
nA, and each n well has a 0.5 nA leakage current. The chip has 50 million transistors. Assume
that each clump of 50 pFETs exists together in one n well, and that there are equal numbers of
nFETs and pFETs on the chip. Compute the number of n wells in this chip, and then compute the
total chip leakage current. If your BIC sensor pops its circuit breaker when the IDDQ current
exceeds 5µA calculate the maximum number of nFET and pFET pairs that can be serviced by
one BIC sensor in your design. Find the total number of BIC sensors needed to provide IDDQ
testing for this entire chip.

Q.10 For the circuit shown, consider the complete set of stuck-at fault tests. Use the leakage fault table
to generate a complete set of leakage fault tests for the circuit, and identify the minimum number
of stuck-fault test vectors needed to test all leakage faults.

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