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  • VLSI Labs Compilation

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    Jhoanie Marie Cauan
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    This document contains a compilation of 8 laboratory activities completed for the ECEN101 (Introduction to Digital VLSI) course. Each activity involves implementing different digital logic gates using CMOS technology in Electric software and verifying the design through simulation. The gates implemented include inverters, NAND, NOR, OR, AND, and 3-input logic functions. For each activity, the student provides the circuit schematic from Electric, the netlist, and simulation results.

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    VLSI Compilation of Laboratories using Electric and Winspice

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    This document contains a compilation of 8 laboratory activities completed for the ECEN101 (Introduction to Digital VLSI) course. Each activity involves implementing different digital logic gates using CMOS technology in Electric software and verifying the design through simulation. The gates implemented include inverters, NAND, NOR, OR, AND, and 3-input logic functions. For each activity, the student provides the circuit schematic from Electric, the netlist, and simulation results.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    4 views21 pages

    VLSI Labs Compilation

    Uploaded by

    Jhoanie Marie Cauan
    This document contains a compilation of 8 laboratory activities completed for the ECEN101 (Introduction to Digital VLSI) course. Each activity involves implementing different digital logic gates using CMOS technology in Electric software and verifying the design through simulation. The gates implemented include inverters, NAND, NOR, OR, AND, and 3-input logic functions. For each activity, the student provides the circuit schematic from Electric, the netlist, and simulation results.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 21

    Republic of the Philippines

    CAVITE STATE UNIVERSITY


    Don Severino de las Alas Campus
    Indang, Cavite
     (046) 415-0010 / (046) 415-0021
    www.cvsu.edu.ph

    COMPILATION OF LABORATORY ACTIVITIES


    IN ECEN101

    A Project
    Submitted to the Faculty of the
    College of Engineering and Information Technology
    Cavite State University
    Indang, Cavite

    In partial Fulfillment of
    the requirements for the subject
    ECEN 101 (Introduction to Digital VLSI)

    JHOANIE MARIE P. CAUAN

    November 29, 2018


    TABLE OF CONTENTS

    Laboratory Activity No. 2 1

    Laboratory Activity No. 3 3

    Laboratory Activity No. 4 5

    Laboratory Activity No. 5 7

    Laboratory Activity No. 6 9

    Laboratory Activity No. 7 11

    Laboratory Activity No. 8 15


    Laboratory Experiment No. 2
    CMOS (Inverter) Implementation

    Given: F = A’

    Truth Table:

    A A’ F
    0 1 1
    1 0 0

    Screenshots:
    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 2 Engr. Rose Ann E. 1


    Sumadsad

    201517338 / BSECE 5-1 CMOS (Inverter) August 29, 2018 19


    Implementation
    2. Netlist

    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 2 Engr. Rose Ann E. 2


    Sumadsad
    0
    201517338 / BSECE 5-1 CMOS (Inverter) August 29, 2018 19
    Implementation
    Laboratory Experiment No. 3
    NAND Implementation

    Given: F = (A.B)’

    Truth Table:

    A B F = (A.B)’
    0 0 1
    0 1 1
    1 0 1
    1 1 0

    Screenshots:

    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 3 Engr. Rose Ann E. 3


    Sumadsad

    201517338 / BSECE 5-1 NAND Implementation September 5, 2018 19


    2. Netlist

    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 3 Engr. Rose Ann E. 4


    Sumadsad

    201517338 / BSECE 5-1 NAND Implementation September 5, 2018 19


    Laboratory Experiment No. 4
    NOR Implementation

    Given: F = (A+B)’

    Truth Table:

    A B F = (A+B)’
    0 0 1
    0 1 0
    1 0 0
    1 1 0

    Screenshots:

    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 4 Engr. Rose Ann E. 5


    Sumadsad

    201517338 / BSECE 5-1 NOR Implementation September 12, 2018 19


    2. Netlist

    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 4 Engr. Rose Ann E. 6


    Sumadsad

    201517338 / BSECE 5-1 NOR Implementation September 12, 2018 19


    Laboratory Experiment No. 5
    OR Implementation

    Given: F = A+B

    Truth Table:

    A B F = A+B
    0 0 0
    0 1 1
    1 0 1
    1 1 1

    Screenshots:

    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 5 Engr. Rose Ann E. 7


    Sumadsad

    201517338 / BSECE 5-1 OR Implementation September 12, 2018 19


    2. Netlist

    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 5 Engr. Rose Ann E. 8


    Sumadsad

    201517338 / BSECE 5-1 OR Implementation September 12, 2018 19


    Laboratory Experiment No. 6
    AND Implementation

    Given: F = A.B

    Truth Table:

    A B F = A.B
    0 0 0
    0 1 0
    1 0 0
    1 1 1

    Screenshots:

    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 6 Engr. Rose Ann E. 9


    Sumadsad

    201517338 / BSECE 5-1 AND Implementation September 19, 2018 19


    2. Netlist

    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 6 Engr. Rose Ann E. 10


    Sumadsad

    201517338 / BSECE 5-1 AND Implementation September 19, 2018 19


    Laboratory Experiment No. 7
    3-Input CMOS Implementation

    A)
    Given: F = A + BC

    Truth Table:

    A B C F = A + BC
    0 0 0 0
    0 0 1 0
    0 1 0 0
    0 1 1 1
    1 0 0 1
    1 0 1 1
    1 1 0 1
    1 1 1 1

    Screenshots:
    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 7 Engr. Rose Ann E. 11


    Sumadsad

    201517338 / BSECE 5-1 3-Input CMOS September 19, 2018 19


    Implementation
    2. Netlist

    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 7 Engr. Rose Ann E. 12


    Sumadsad
    0
    201517338 / BSECE 5-1 3-Input CMOS September 19, 2018 19
    Implementation
    B)
    Given: F = AB + C

    Truth Table:

    A B C F = AB + C
    0 0 0 0
    0 0 1 1
    0 1 0 0
    0 1 1 1
    1 0 0 0
    1 0 1 1
    1 1 0 1
    1 1 1 1

    Screenshots:

    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 7 Engr. Rose Ann E. 13


    Sumadsad
    0
    201517338 / BSECE 5-1 3-Input CMOS September 19, 2018 19
    Implementation
    2. Netlist

    3. Simulation Results

    Engr. Rose Ann E. 14


    Cauan, Jhoanie Marie P. Laboratory Activity No. 7
    Sumadsad
    0
    201517338 / BSECE 5-1 3-Input CMOS September 19, 2018 19
    Implementation
    Laboratory Experiment No. 8
    4-Input CMOS Implementation

    A)
    Given: F = AB’ + CD

    Truth Table:

    A B C D F = AB’ + CD
    0 0 0 0 0
    0 0 0 1 0
    0 0 1 0 0
    0 0 1 1 1
    0 1 0 0 0
    0 1 0 1 0
    0 1 1 0 0
    0 1 1 1 1
    1 0 0 0 1
    1 0 0 1 1
    1 0 1 0 1
    1 0 1 1 1
    1 1 0 0 0
    1 1 0 1 0
    1 1 1 0 0
    1 1 1 1 1

    Cauan, Jhoanie Marie P. Laboratory Activity No. 8 Engr. Rose Ann E. 15


    Sumadsad
    0
    201517338 / BSECE 5-1 4-Input CMOS September 26, 2018 19
    Implementation
    Screenshots:
    1. Circuit from Electric (Schematic Diagram)

    2. Netlist

    Cauan, Jhoanie Marie P. Laboratory Activity No. 8 Engr. Rose Ann E. 16


    Sumadsad
    0
    201517338 / BSECE 5-1 4-Input CMOS September 26, 2018 19
    Implementation
    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 8 Engr. Rose Ann E. 17


    Sumadsad
    0
    201517338 / BSECE 5-1 4-Input CMOS September 26, 2018 19
    Implementation
    B)
    Given: F = A’BC + D’

    Truth Table:

    A B C D F = A’BC + D’
    0 0 0 0 1
    0 0 0 1 0
    0 0 1 0 1
    0 0 1 1 0
    0 1 0 0 1
    0 1 0 1 0
    0 1 1 0 1
    0 1 1 1 1
    1 0 0 0 1
    1 0 0 1 0
    1 0 1 0 1
    1 0 1 1 0
    1 1 0 0 1
    1 1 0 1 0
    1 1 1 0 1
    1 1 1 1 0

    Screenshots:

    1. Circuit from Electric (Schematic Diagram)

    Cauan, Jhoanie Marie P. Laboratory Activity No. 8 Engr. Rose Ann E. 18


    Sumadsad
    0
    201517338 / BSECE 5-1 4-Input CMOS September 26, 2018 19
    Implementation
    2. Netlist

    3. Simulation Results

    Cauan, Jhoanie Marie P. Laboratory Activity No. 8 Engr. Rose Ann E. 19


    Sumadsad
    0
    201517338 / BSECE 5-1 4-Input CMOS September 26, 2018 19
    Implementation

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