Code: R7210504 R07

B.Tech II Year I Semester (R07) Supplementary Examinations June 2015

DIGITAL LOGIC DESIGN
(Common to CSE, IT & CSS)
Time: 3 hours Max. Marks: 80
Answer any FIVE questions
All questions carry equal marks

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1 Convert the following numbers:
(a) (i) 10101100111.0101 to Base 10
(ii) (153.513)10 =( )8
(iii) Divide 01100100 by 00011001
(iv) Given that (292)10 = (1204)b determine ‘b’.
(b) Perform the following binary multiplication operations:
(i) 100010 X 001010=
(ii) 000100 X 010101=

2 Simplify using Boolean theorems:

(a) (i) (X’+XYZ’)+(X+X’Y’Z)(X(X’+Y’+Z))’
(ii) (X+Y)[X’(Y’+Z’)]’+X’Y’+X’Z’
(b) Explain about positive, negative and mixed logic in binary signals.

3 (a) Implement half adder using 4 NAND gates.

(b) Implement full subtract using NAND gates only.

4 Design an Excess-3 to BCD code converter using minimum number of NAND gates.

5 (a) Differentiate between sequential and combinational circuits.

(b) Differentiate between synchronous and asynchronous sequential circuits.

6 Explain about ripple counters in detail.

7 Explain about error detection and correction in detail.

8 Explain about the reduction of state and flow tables in an asynchronous sequential circuit in
detail.

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