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Contents
Lesson 1
Welcome #32;
Objectives #32;
Lesson 2
Objectives #32;
Lesson 3
Objectives #32;
Lesson 4
Revising the Board Layout #32;
Lesson 5
Routing the Clock Driver Net #32;
Finishing Up #32;
Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA
95134, USA
Lesson 1
Welcome
This tutorial is designed to familiarize you with Allegro PCB SI
230/610/630. It assumes that you already know how to use SI 230/610/630
and that you are familiar with Windows®. You begin this tutorial from the
PCB Editor.
Objectives
In this lesson, you learn:
<install_dir>\doc\assetut\goldenboards
We suggest that you complete each lesson in sequence. In this way, the
state of the board file at the end of one lesson can be used as the starting
point for the next lesson. You can, though, take a lesson out of sequence
by loading the appropriate board file for that lesson. See Board databases
used in this tutorial.
Also, to end this tutorial, you can optionally save the clock net that you
routed in Lesson 5, as myboard6.brd. In this way, you can archive the
entire tutorial for later reference.
Starting the Tutorial
Now that you have set up a working directory as described in Board
databases used in this tutorial, you're ready to start the first lesson.
The first lesson explains how to navigate within the PCB Editor using
zoom and pan commands. These principles hold true for moving around in
SI 230/610/630 and SigWave, which you are asked do in later lessons.
2. Click the change directory check box to ensure that your design is
saved to the working directory that you set up.
3. Double-click tutboard1.brd.
The board database is loaded into the PCB Editor with all ratsnest
displayed.
This section is only for reference. You do not perform any exercises.
There are many zoom commands; however, in this tutorial, we'll limit our
discussion In, Out, Points, Fit, and Pan.
The following depicts zoom commands available from the PCB Editor.
The equivalent menu commands from SI 230/610/630 and SigWave are
also shown.
Save the Design
You have not modified the board in this lesson, but to maintain continuity
between the board number and the lesson number, if you are using your
own board files choose File > Save As and specify myboard2.brd (or
whatever naming convention you chose).
Lesson 2
Objectives
In this lesson, you:
• highlight a net in the PCB Editor for extraction into Allegro PCB
SI 230/610/630.
• become familiar with the Topology Template dialog box.
• attempt to extract a net from the PCB Editor for topology
exploration in Allegro PCB SI 230/610/630.
• prepare a net for extraction by running the Database Setup
Advisor.
In this exercise, you will isolate the clock net so that it is easier to work
with. You accomplish this in two steps.
To begin this lesson, you should have tutboard2.brd open in the PCB
Editor.
1. From the PCB Editor, choose Display - Show Rats - Net. (For
Allegro PCB SI 230/610/630, choose Display - Ratsnest...)
4. Press Return
Notice the net connects connector J7, the clock driver U9, and the
processor chipset.
You will run the Database Setup Advisor to identify and correct this
problem.
The selected net (cclock) will seed the Signal Analysis form. Pick
View Topology to extract the net topology.
3. Click Yes.
The Database Setup Advisor guides you through the following five steps
that prepare a net for extraction into SI 230/610/630.
• Cross-section
• DC Nets
• Devices
• SI Models
• SI Audit
Consult Getting Started with Allegro PCB SI 230/610/630 for
information on using the Database Setup Advisor.
From the previous exercise, you should have the advisor displayed.
1. Click Next three times to advance to the Device Setup form in the
advisor.
5. Click OK.
With the correct CLASS properties (IO) on Connectors J7 and J9, the clock
net is now prepared for extraction.
You repeat the net extraction process in the next lesson. If you are using
your own board files, in the PCB Editor, choose File - Save As and specify
myboard3.brd (or whatever naming convention you chose).
Lesson 3
Objectives
In this lesson, you:
• extract a net from the PCB Editor for topology exploration in Allegro PCB SI
230/610/630.
• explore the extracted circuit topology in SI 230/610/630.
• set up reflection measurements in SI 230/610/630.
• simulate a net topology in SI 230/610/630.
• analyze the resulting spreadsheet- and waveform-data in SI 230/610/630.
The following message appears - because no signal models have been assigned to
components on the net:
3. Select 'No' to launch SigXplorer and extract the topology using default Cadence
SI buffer models.
1. Click the horizontal border separating the canvas and the spreadsheet, then drag
the border vertically.
With the topology extracted from your design in the PCB Editor and visible in SI
230/610/630, you should make the following observations. You may have to zoom and
pan as appropriate.
Notice that:
• The off-board connector (J7) along with a single driver (U9, Pin 9) and many
receivers
• Transmission lines with delays based on length (derived from Manhattan distance
estimates)
• The driver and all receivers default to Tristate on initial extraction.
• Default IOCell models were assigned to drivers and receivers based on PINUSE
Click Parameters and expand all circuit parameters by clicking the + signs until the
spreadsheet shows all - signs, indicating the lowest level.
Note the characteristic impedances for the transmission lines in the circuit. You can click
in the attribute Name field and change any of these values. The topology element in the
canvas will be updated with the new value.
Examine the attribute and value (IOCell buffer model) field of receiver U69.
You can select a different IOCell buffer model based on your requirements.
Note: Consult the ` online help for a thorough discussion of signal integrity models.
Specifying Stimulus
The receivers are preset to their default tri-state condition. You must set the driver to
either a Pulse, Rise, or Fall state. You can simulate with only one active driver at a time,
which is not an issue with the cclock net as it has only a single driver (U9, Pin 9).
4. Click OK.
4. Click the circle adjacent to the reflection label, and then right-click and choose All
Off from the pop-up window.
Once simulation is complete, the Results View appears showing the spreadsheet data.
Notice in the Overshoot Low column, many of the receivers approach negative 900
millivolts.
Next, SigWave appears showing the output waveforms from the simulation.
Observations include: (1) skew at the clock input to the receivers; (2), a fair amount of
ringing; (3), a noticeable negative overshoot of 900 mV below ground; and (4), some
non-monotonic activity.
In SigWave, you are going to take a closer look at the problem areas of the waveforms.
The input protection diodes in the receivers are designed to fire at -700 millivolts. You
are going to measure the duration that the waveforms dip below this threshold.
Finishing Up
A .sim file extension is automatically added to the base file name. In the next lesson, you
will use this for making comparisons.
If you are using your own board files, in the PCB Editor, choose File - Save As and
specify myboard4.brd (or whatever naming convention you chose).
Lesson 4
Objectives
• move the clock driver chip in the PCB Editor to a location that is
central to other components on the clock circuit.
• swap components in the PCB Editor to reduce the length of the
clock circuit.
• simulate this revised circuit topology in Allegro PCB SI
230/610/630.
• analyze the resulting spreadsheet- and waveform-data in Allegro
PCB SI 230/610/630.
To begin this lesson, you should have tutboard4.brd open in the PCB
Editor.
The clock driver (U9) is located in the lower-left quadrant of the board,
which is some distance from many of the chips (receivers) that it controls.
To minimize delays at the receivers, it is best to centralize the placement
of this driver.
To move the clock chip
Swapping Components
Although the clock driver is now closer to the receivers, you can shorten
the length of the clock net even more by swapping some of the receivers,
with chips of the same type, that are even closer to the driver.
In this exercise, you will swap U93 with U70, and U85 with U16.
To swap components
The view now focuses on the chips that you will swap. Allegro
PCB SI 230/610/630 menus do not have a component swap
sselection, but the command can still be accessed by typing
helpcmd.
Put these skills to work and simulate the revised circuit topology. The
measurements that you previously specified are still in effect. You do not
have to reselect them. If SigXplorer is still open, confirm that you want to
overwrite the old topology.
You then examine pre- and post-placement waveforms with all signals
displayed, followed by a signal-to-signal comparison.
4. Size the SigWave window (as shown) so that you can view the
signal names.
You should observe that all signals from both waveforms display with
minimal deviation.
Note: The composite drawing below captures the resulting waveform and
spreadsheet data from pre-placed and placed simulations.
Finishing Up
If you are using your own board files, in the PCB Editor, choose File - Save
As and specify myboard5.brd (or whatever naming convention you chose).
Lesson 5
Objectives
To begin this lesson, you should have tutboard5.brd open in the PCB
Editor.
The PCB Router routes your board in the background. RMB and
pick done when the route completes.
Exploring the Extracted Circuit Topology
Using the skills that you learned in previous lessons, extract the topology
of net cclock.
• Specify Stimulus
• Specify Measurements
• Simulate
• Compare resulting simulation waveforms
Put these skills to work and simulate the routed circuit topology.
The pre-routed topology that you extracted in the previous
lesson was based on a virtual representation. The routed
topology that you are about to extract is based on a physical
layout with layer and via information; therefore, before you
simulate from SI 230/610/630, you must choose Analyze -
Reset Sim Data to reload the interconnect library that
contains the electrical model for the extracted via.
If SigXplorer is still open, confirm that you want to overwrite the old
topology. You should observe results similar to the following.
Note: The composite drawing below captures the resulting waveform and
spreadsheet data from pre-route and post-route simulations.
Notice that the post-route waveforms are even more ideal than the
waveforms from the modified placement. There is less skew among the
receivers, the negative overshoot was reduced from -148.9 mV to -95.5
mV.
Finishing Up
If you are using your own board files, in the PCB Editor, choose File - Save
As and specify myboard6.brd (or whatever naming convention you chose).