 3D Integrated circuit is a chip which accommodates

two or more layers of active electronic components

 They are integrated both horizontally and vertically

onto a single circuit.
To reduce wastage of space on the substrate.

To improve interconnections among different wafers.

To reduce the length of interconnections which in turn

reduces heat dissipation and also RC delays.

Can be used to accommodate both homogenous and

heterogeneous chips.

Thus there is a great urge to switch over

from 2D ICs to 3D ICs
•The substrate is divided into blocks

•The similar characterized active components are stacked

in the same block.

•This results in ease of interconnection.

•Each block is called a tier.

LOCAL TIERS

•Independent responding blocks

SEMI-GLOBAL TIERS

•Blocks used for intra communication

GLOBAL TIERS

•Inter communicating blocks used for clock and power supply

BEAM RECRYSTALLISATION:

This method involves deposition of polysilicon.

This is used to fabricate TFTs which in turn are used in

fabrication of 3D ICs.

PROCESSED WAFER BONDING:

This method bonds processed wafers together, and it is

independent of temperature.

SOLID PHASE CRYSTALLISATION:

It offers flexibility for fabricating multiple layers, used

mostly for stacking SRAM and EPROM.
Timing

Energy performance

Interconnection structures
In current technologies, timing is interconnect driven.

Reducing interconnect length in designs can dramatically

reduce RC delays and increase chip performance
 Wire length reduction has an impact on the cycle
time and the energy dissipation

Energy dissipation decreases with the number of

layers used in the design
3D Cell Placement
Placement by min-cut partitioning

3D Global Routing

Inter-wafer vias

Circuit layout management

MAGIC
Natural to think of a 3D
integrated circuit as being
partitioned into device
layers or planes

Min cut partitioning

along the 3rd dimension is
same as minimizing vias
•Routing in 3D consists of routing a set of aligned
congruent routing regions on adjacent wafers.

•Wires can enter from any of the sides of the routing

region in addition to its top and bottom

•3D router must consider routing on each of the layers

in addition to the placement of the inter-waver vias
ILLUSTRATION OF ROUTING AREAS

y y

x x

z z

Detailed routing of net when

routing areas are known

LOOSE ROUTING DETAILED ROUTING

 MAGIC is an open source layout editor developed at UC Berkeley

 It is an extension to MAGIC by providing support for Multi-layer

IC design.

 The difference is that it has a new Command “bond”.

 Bond places inter-layer vias in the design file.

 Once Two layers are bonded they are treated as one entity.
The 3D Integrated circuits are a great relief to
interconnected IC technologies.

 This opens up a new era in chip designing which has

many aspects still to be explored and exploited.

These can be used in many facets of our lives like

smartphones,microprocessor based memory stacks etc.

Thus it can be concluded that

“3D IC – A GREAT UPLIFTMENT TO IC WORLD”