10-Gb/s 0.

13-µm CMOS Inductorless

Modified-RGC Transimpedance Amplifier
M.H. Taghavi, Student Member, IEEE, L. Belostotski, Senior Member, IEEE, J.W. Haslett, Life Fellow, IEEE,
and P. Ahmadi, Student Member, IEEE,

VDD VDD VDD

Abstract—This paper presents an inductorless 0.13-µm CMOS
TIA structure that is a modified version of a regulated cas-
code (RGC) TIA. An immittance converter is incorporated to R‘L RL‘ Rc‘
vout node X ‘
reduce power consumption while increasing transimpedance gain. vout
Measured 3-dB bandwidth is 7 GHz, sufficient for 10-Gb/s Cout
CPD Vb
operation, in the presence of 250 fF capacitance at the TIA M3‘ Vb M‘2
CPD
input, representative of typical CMOS photodiode capacitance. iin iin M‘3
The transimpedance gain of the single-stage TIA is 50 dBΩ, M‘1
and the group-delay variation is less than ±19 ps over the 3-dB Ibias Ibias
bandwidth. The circuit occupies an active area of 180µm×90µm Auxiliary
amplifier
and consumes 7 mW from a 1.5-V supply. The measured √ Zin‘
average input-referred current noise of the TIA is 31 pA/ Hz. (a) (b)
Simulations and analysis show that the proposed single-stage VDD
TIA architecture is capable of achieving improvement in the
transimpedance limit over a single-stage RGC TIA designed for
the same data rate and the same input photodiode capacitance. RL‘
vout M2‘
A comparison of measurement results to published TIAs also
demonstrates the competitive performance of the proposed TIA L‘in
CPD M3‘ Zin‘ Cin‘
in terms of the TIA transimpendance gain, bandwidth, area, and
power consumption. iin M1‘ Rin‘
Index Terms—Transimpedance amplifier, regulated cascode Ibias
transimpedance amplifier, cross-coupled immittance converter. Auxiliary
amplifier
(c) (d)
I. I NTRODUCTION Fig. 1. (a) CG TIA, (b) RGC TIA, (c) Modified RGC TIA in [3], and (d)
A model of an RGC TIA input impedance.
Optical communication data rates are continually increasing
the transimpedance gain and the bandwidth. A common-
due to the need to handle growing amounts of data generated
gate (CG) transistor shown in Fig. 1(a) can be used as a
by electronic systems. III-V technologies are well suited for
TIA, since low input resistance can be achieved when the
optical communication systems due to their large transcon-
transistor transconductance, gm , is large. This type of TIA
ductance, low added noise, and high operating frequencies.
is straightforward to design, however large gm requires either
However, they suffer from low integration densities and higher
a large transistor and/or a large amount of current. A large
costs compared to those of CMOS technologies. The challenge
transistor limits the TIA bandwidth, whereas the large current
in designing a wideband CMOS optical receiver front-end,
creates a large voltage drop across the load resistor. In [2] a
consisting of a CMOS photodiode and transimpedance ampli-
feedback resistor was introduced from the CG TIA buffer to
fier (TIA), arises because of the large photodiode capacitance,
the TIA input, which reduced the TIA input resistance and
usually in the range of 0.2 to 0.5 pF [1]. For a given data
power consumption at the expense of the TIA transimpedance
rate, CMOS technology, and photodiode capacitance, each
gain. Another way to increase the effective gm is by using
of many possible TIA topologies has a certain maximum
a regulated cascode (RGC) TIA, shown in Fig. 1(b). This
transimpedance gain, i.e. the transimpedance limit. The tran-
TIA is based on a CG TIA with an auxiliary gain-boosting
simpedance limit is used as a figure of merit for comparison
amplifier to decrease its input impedance [4], [5]. When the
of different TIAs and for understanding trade-offs between
RGC TIA frequency response is free of amplitude peaking, its
0
Manuscript received on XXXX XX, 2015. This work was supported by transimpedance limit RT is given by [6]
The University of Calgary, the Natural Sciences and Engineering Research
Council of Canada Grant RGPIN/358707-2013, Alberta Innovates-Technology 2
0 (A0 f0 )
Futures, the Alberta Provincial Government’s iCORE program, and CMC RT ≤ 0 , (1)
Microsystems. 2πCT χ0 2 BW 0 3
M. Taghavi, L. Belostotski, J. Haslett, and P. Ahmadi are with the
Department of Electrical and Computer Engineering, University of Calgary, where A0 f0 is the gain (A0 ) bandwidth (f0 ) product of the
Calgary, AB, T2N 1N4, Canada. CG amplifier, where a single-dominant pole is assumed, and
Copyright (c) 2015 IEEE. Personal use of this material is permitted. 0
However, permission to use this material for any other purposes must be is roughly proportional to fT of the technology, CT is the
obtained from the IEEE by sending an email to pubs-permissions@ieee.org. sum of the photodiode capacitance (CP D ) and the amplifier
 0 0
input capacitance (Cin ), BW is the 3-dB bandwidth of the VDD VDD
0
TIA, and χ is the pole spacing, defined as the ratio of
frequencies of the complex-conjugate pole-pair and the output
real pole, which are present in the transfer function describing RL Rc Lin,MIC

Cin,MIC
the TIA behavior. Three important conclusions can be realized Cout Zin,MIC
from (1). First, the transimpedance-gain-bandwidth trade-off Rin,MIC
is not linear and the transimpedance gain increases rapidly M3 M2
for small bandwidths. Second, with A0 f0 /CT being technol-
ogy dependent, the transimpedance-gain-bandwidth trade-off
vin
is also technology dependent. Third, the transimpedance limit
0
degrades as the pole spacing χ increases and the optimum (a) (b)
0 Zin,MIC
transimpedance limit can be obtained for χ ≈ 1. VDD VDD
There are a number of ways the transimpedance limit
can be increased. An often-favored way is by adding post-
amplifier buffer stages [6]. As will be seen later in the RL Rc
performance summary table in Section III, the addition of vout
buffer amplifiers is also an effective method for increasing the Cout
TIA transimpedance gain RT IA . However, cascading buffer
M3 M2
stages results in reduced bandwidth and increased power
CPD
consumption.
Other transimpedance limit enhancement techniques include
inductive peaking [7]–[12], distributed TIAs [13], [14], and iin
recent multi-path inductorless TIAs [15]. There are also mod- (c)
ifications to the conventional RGC TIA that address some of Fig. 2. (a) MIC circuit, (b) its input equivalent impedance, and (c) TIA
its shortcomings and improve the transimpedance limit with circuit using the MIC in (a).
power- and area-efficient bandwidth extension. For example, in gL = RL −1
. For gL2
 ω 2 Cout
2
, Zin,M IC ≈ gm3 −1
+
[3], a modified RGC TIA, shown in Fig. 1(c), was introduced. 2
gm2 Rc (sCout − gL ) /gL and the input impedance can be
This TIA uses an inverter-based auxiliary amplifier, instead of modeled as a series Rin,M IC − Lin,M IC circuit in parallel
a common-source amplifier for gain-boosting. This addresses with a capacitance Cin,M IC as shown in Fig. 2(b). In this
the problem encountered within the conventional RGC TIA, −1
circuit Rin,M IC ≈ gm3 − gm2 RL Rc can be designed to be
where the auxiliary amplifier suffers from limited gain due to small as required for a broadband TIA. The presence of the
the limited supply voltage. The modified RGC in [3] achieves negative term in Zin,M IC breaks the trade-off between power
the performance of the conventional RGC TIA but with ~30% consumption and bandwidth, since gm3 can be made small,
reduction in the power consumption. thus reducing the power consumption, while Rin,M IC can still
This paper presents an inductorless TIA topology in Section be made small.
II to further increase the maximum achievable transimpedance
gain of an RGC TIA by further decoupling the input resistance While the circuit in Fig. 2(a) exhibits desirable input
of the circuit from the power consumption. The proposed impedance characteristics, when used as a TIA with low
TIA is synthesized using an immittance converter that can be input resistance as shown in Fig. 2(c) and in [17] or as a
configured as either a negative impedance converter in order differential TIA in [18], this circuit is expected to have an
to generate an active -C element or a positive impedance unsatisfactory stability behavior when large gain is desired.
converter to generate an active inductance. Either the -C or To illustrate this, consider that when Rin,M IC ≈ 0 a lossless
the L element can be used to mitigate the effect of the large resonant network is formed by the input active inductance,
2
photodiode capacitance at the input of the TIA. The measured Lin,M IC = = {Zin,M IC } /ω ≈ gm2 Rc RL Cout , and the
results of a designed and fabricated TIA are shown in Section photodiode capacitance. To avoid oscillations when Rin,M IC
III, and finally the conclusion is given in Section IV. In is small, such a TIA should be designed such that Lin,M IC is
this paper, all primed parameters pertain to an RGC TIA to small. This suggests that RL must be chosen small. Since the
distinguish them from unprimed parameters pertaining to the transimpedance gain at low frequencies is RL , the stability
proposed TIA. A review of RGC TIAs is given in Appendix of this circuit is traded-off against the transimpedance gain.
A. In other words, the input resistance can be made zero if
the input complex-conjugate pole-pair frequency, which is
II. I MMITTANCE -C ONVERTER - BASED TIA associated with Lin,M IC and the capacitance at the input,
A. Immittance converter is much larger than the desired bandwidth. However, despite
To explain the operation of the proposed TIA, we start by having lower transimpedance gain than the RGC TIA, this
examining the MOS-based immittance converter (MIC) [16] circuit can be utilized as a TIA that is insensitive to large
in Fig. 2(a). photodiode capacitance and can tolerate large variations of
The input impedance of the MIC can be calculated total capacitance at the input since Rin,M IC ≈ 0 [18].
−1 −1
as Zin,M IC ≈ gm3 − Rc gm2 (sCout + gL ) , where To avoid the stability problems but still to utilize the low
 VDD VDD TABLE I
L OW- FREQUENCY VOLTAGE GAINS OF THE CIRCUIT IN F IG . 3( C ),
ASSUMING THAT gds2,3 = 0. T HE APPROXIMATE GAINS ARE OBTAINED
vout RL Rc BASED ON THE CIRCUIT PARAMETERS OF THE IMPLEMENTED TIA
node X
DISCUSSED IN S ECTION III.
Cx
Cout
M3 M2
Voltage gain Approximation
Lin
CPD node Y Zin Cin
iin vx −Rc gm2 (gm1 +RL gm3 gds1 ) Rc gm1
Gxi = vin = gm2 ×∆+gds1 Gxi ≈ − ∆
M1 Rin
Ibias vout gm3 RL [gm2 (1+Rc gm1 )+gds1 ]
Gox = vx =− Gox ≈ −gm3 RL
Rc gm2 (gm1 +RL gm3 gds1 )
Zin
(a) (b) vy RL gm2 gm3 (1+Rc gm1 )−gm1 RL Rc gm1 gm3
Gyi = vin = gm2 ×∆+gds1 Gyi ≈ ∆
Cdb3 RL Rc Cdb2 Cout RL Rc Cx
Cgd3+Cgd2 vout RL gm3 (gm2 (1+Rc gm1 )+gds1 )
Goy = vy = RL gm2 gm3 (1+Rc gm1 )−gm1
Goy ≈ 1
vx vout node X
vout
gm2v2 gm2v2 gm3 RL [gm2 (1+Rc gm1 )+gds1 ]
gm3v3 gm3v3 Goi =
vout
= = RL gm3 (1 − Gxi )
v2 node Y vin gm2 ×∆+gds1
v3 v2 v3
Cgs3 Cgs2 vy Cy
vin Cin gm1v1 ∆ ≡ 1 − RL Rc gm3 gds1
Cgd1 gm1v1
iin v1 gds1 CPD iin gds1
CPD v1
Cgs1 B. Input impedance of the MIC TIA
CT=CPD+Cin
(c) (d) The input impedance of the MIC TIA (Zin ) can be modeled
Fig. 3. (a) Proposed MIC TIA, (b) model of its input equivalent impedance,
as a shunt-peaked equivalent circuit as shown in Fig. 3(b). To
(c) its small-signal model, and (d) its small-signal model simplified by using do so, the TIA small-signal model in Fig. 3(c) is first simplified
Miller capacitances. by using Miller capacitances to reflect all important capaci-
input resistance and the active Lin,M IC properties discussed tances to the input node (Cin ), the output node (Cout ), and
above, the MIC can be combined with the RGC TIA to form nodes X and Y (Cx and Cy ) as shown in Fig. 3(d). In this sim-
1
the MIC TIA shown in Fig. 3(a), which originates from a plification, low-frequency voltage gains

, shown in Table I, are
−1
low noise amplifier (LNA) discussed in [16] but differs in its used to obtain Cy ≈ Cgd1 1 − Gyi +Cdb1 +Cgs2 (1 − Goy
),
design procedure and the location of the output node. The Cx ≈ (1 − Gox ) (Cgd2 +
Cgd3 ) + Cdb2 + Cgs3 1 − G−1 xi
,
main differences in the designs of the LNA in [16] and the Cout ≈ Cdb3 + 1 − G−1 ox (C gd2 + Cgd3 ) + C gs2 1 − G −1
oy ,
MIC TIA stem from different performance requirements for and Cin , which is a part of the shunt-peaked model in Fig.
the two circuits. The LNA is driven by a 50-Ω signal source 3(b), as
and its input capacitance is dominated by the gate-source and
Miller capacitances of its input transistors. The design of such Cin ≈ Cgs1 + (1 − Gxi ) Cgs3 + (1 − Gyi ) Cgd1 . (2)
an LNA focuses on noise- and power-matching for achieving
reasonable power gain from the gate of M1 to the drain of M2 Capacitance at node Y is ignored in the following because
and low noise figures. The MIC TIA is driven by the large of its relatively insignificant effect on the input impedance.
capacitance of the photodiode. There is no need to optimize While simulations show that gds2 and gds3 have little effect
power gain in this case and noise figure is not defined but the on the input impedance, gds1 is not negligible as it appears
goal is to have most of the photodiode current flowing into in the term2 ∆, as defined in Table I, which can be made
the source of M3 . The transimpedance gain from input to the smaller than 1 (∆ ≈ 0.65 in the optimized TIA in Section
drain of M3 and the frequency response are the main design III), thus increasing the magnitudes of Gyi and Gxi . Large Gyi
parameters for the TIA. creates a large negative Miller capacitance due to Cgd1 (see
the last term in (2)), whereas large Gxi increases the Miller
Considering the circuit in Fig. 3(a) at low frequencies, the capacitance due to Cgs3 (see the middle term in (2)). Since in
transimpedance gain of the MIC TIA is the same as that of our design M3 is smaller than M1 , we have Cgs3 < Cgd1 , and
the RGC TIA in (A2). As in the conventional RGC TIA, there Cin and CT ≡ CP D + Cin are reduced due to ∆ < 1. Large
is more than one signal path between input and output in the Gxi also reduces the Miller effect of Cgs3 on Cx , which will
MIC TIA. The extra paths can create zeros in the transfer be shown to be important for this circuit. In addition, since
function of the circuit. However, for the practical MIC TIA Gxi is the voltage gain of the auxiliary amplifier, the increase
discussed in this work, the zeros occur at high frequencies and ef f
in Gxi increases the effective gm3 ≡ gm3 (1 − Gxi ), which
are neglected in the further analysis. results in larger Goi and in lower input resistance, Rin that is

In order to acquire circuit design insights, we employ 1 In this context the voltage gains are the ratios of node voltages of the
Miller effect to analyze the circuit. Rather than analyzing operating TIA.
the third-order transimpedance transfer function, shown for 2 In the limiting case when g
ds1 = 0, an RGC TIA performance improves
completeness in the Appendix B, the following discussions and all equations presented in this work and pertaining to the MIC TIA
become identical to equivalent equations for the RGC TIA. In a practical
are focused on the analysis of the MIC TIA input impedance, situation when gds1 6= 0, an MIC TIA will be shown to outperform an
which largely determines the TIA behavior. equivalent RGC TIA.
 120 simulated MIC TIA to that obtained with a simulation of
Desired BW the TIA small-signal model shown in Fig. 3(c), with the
100 TIA simplified shunt-peaked model in Fig. 3(b), parameters
of which are described by (2)-(4), and a simplified small-
80
Real (Ω)

signal model in Fig 3(d). As shown, within the bandwidth

of interest the simplified small-signal model in Fig. 3(d)
60 closely follows the more accurate model in Fig. 3(c) thus
confirming the validity of using Miller approximations to
40 BSIM simulation in Fig. 3(a) simplify the analysis. The BSIM4 circuit simulation results
Shunt-peaked RLC model in Fig. 3(b) agree reasonably well with results obtained with models in
20 Small-signal circuit in Fig. 3(c) Figs. 3(b)-(d) within the entire TIA bandwidth with some
Simplified small-signal circuit in Fig. 3(d) discrepancy in the order of 10% due to simplifications such
0 as gds2,3 ≈ 0. Therefore, the shunt-peaked model is seen
0 5 10 15 as suitable for an intuitive analysis of the TIA behavior
√
−1 at
(a) Frequency (GHz) frequencies that are well below ωin = Lin Cin , which
20 can be designed to be much higher than the desired operating
Desired BW frequency range for the MIC TIA3 . The simulation results
also demonstrate that the input impedance of the MIC TIA
10 is inductive for the entire TIA bandwidth thus potentially
Imaginary (Ω)

resonating out some of the input photodiode capacitance.

0 C. Discussion on the shunt-peaked model parameters

BSIM simulation in Fig. 3(a) We now investigate the relative difference between the
shunt-peaked input impedance representations of the MIC and
-10 Shunt-peaked RLC model in Fig. 3(b) RGC TIAs that are assumed to have been designed with iden-
Small-signal circuit in Fig. 3(c) tical circuit components. This will be helpful in determining
Simplified small-signal circuit in Fig. 3(d) the expected MIC TIA transimpedance limit improvement.
-20 1) Rin : From (3) and gain Goi shown in Table I, the input
0 5 10 15 resistance can be adjusted to zero by fulfilling the following
(b) Frequency (GHz) condition: gds1 ≈ gm2 /(gm2 gm3 RL Rc − 1). If this is fulfilled,
Fig. 4. MIC TIA input impedance: (a) the real part and (b) the imaginary part. then the MIC TIA would have a large bandwidth. However,
The impedance is obtained from simulations with BSIM4 transistor models, in this case the TIA is prone to oscillations as discussed in
small-signal analysis, and the shunt-peaked model in Fig. 3(b). For the small- Section II-A. The negative term in ∆ in the denominator
signal model simulations, the parameters from the implemented MIC TIA
discussed in Section III are used. of Goi in (3) can be also used to relax constraints on gm3 ,
found from [16] or by analyzing Fig. 3(c) as present in CG TIAs and RGC TIAs, for a given desired input
 −1 resistance. Therefore, the amount of current that is needed for
Rin = RL G−1 ef f biasing gm3 can be reduced and a large resistor, instead of
oi ≡ gm3 . (3)
a current source Ibias in Fig. 3(a), can be used to lower the
The remaining parameter of the shunt-peaked model, Lin , is noise contribution of that part of the circuit. Furthermore, the
found from Fig. 3(d) with Cin set to zero, as it is accounted for lower current draw reduces voltage drop across RL , alleviates
in the shunt-peaked model on its own, and with Cy at the low a possible voltage headroom problem, and allows for a larger
impedance node Y ignored due to its insignificant contribution RL , which makes the MIC TIA a good candidate for low-
to Lin . Analysis of the input impedance shows power design.
  Further examination of (3) and Goi in Table I reveals
Rin Gxi 0
that the only difference between Rin and Rin in (A1), is
Lin |gds2,3=0 ≈ Cout RL (1 − ∆) + Cx Rc
∆ + ggds1
m2
Gxi − 1 the ∆ term multiplying gm2 in the numerator and Rin =
(4) 0 0 0 0
(gm2 × ∆ + gds1 ) Rin / gm2 + gds1 ≈ ∆Rin . This how-
where the quality factor of Lin is
ever brings about an important feature of the MIC TIA in
−1


Gxi ∆ + gds1 gm2 that Rin decreases with increasing RL . Thus, unlike the RGC
QLin ≈  . (5) TIA, increasing RL not only increases the transimpedance
Gxi
ω Cout RL (∆ − 1) + Cx Rc 1−G xi gain, since RT = RL , but also decreases Rin , which can
Note that the shunt-peaked equivalent circuit in Fig. 3(b) improve the TIA bandwidth.
omits some higher-order components, such as Cy , that become 2) Effective Lin : Expressions for an RGC TIA input in-
0 0

important at high frequencies. In practice, Cy can affect Lin ductance, Lin , with an associated QLin are very similar to (4)
0

somewhat at high frequencies and may need to be accounted and (5) and are obtained by substituting ∆ = 1. As Lin and
for with simulations. 3 In BSIM4 simulations reported in Fig. 4, ω
in is nearly 17 GHz whereas
Fig. 4 compares input impedance behavior of the BSIM4- the TIA bandwidth is <10 GHz.
 0 0 0
QLin do not depend on Cout , Lin > Lin for an MIC TIA and Having the two TIAs achieve Rin = Rin through (3) and (A1)
an RGC TIA built with the same components. The effective leads to
inductance due to the Rin -Lin branch of the shunt-peaked 0
gm3 (gm2 × ∆ + gds1 ) gm2
network is Lef f
in ≡ Lin (1 + Rin /ωL
in QLin ), which can be 0 ≈ 0 0

≈ ∆ ≤ 1. (8)
ef f −1 gm3 gm2 + gds1 gm2
shown to be Lin ≈ Lin 1 − G
 xi . Similarly, for an RGC
0
 0 0
TIA, Lef f
= Lin 1 − Gxi−1 . The relative sizes of Lef f 0
in in Based on the assumption that ωp1 = ωp1 , then with (A6) and
0
and Lef f
is a function of not only the circuit parameters but (7), it can be shown that
in
also parasitic capacitors and are difficult to estimate accurately.
 
ωp1 1 1−∆ 0 0

Simulations have shown that for the MIC TIA implemented in 0 = + gm3 RL = 1, (9)
ωp1 g R
m3 L g R
m1 c
this work and an RGC TIA0 implemented with the same circuit
components, Lef f ef f
by a ratio of ∼ 0.8. where gain-bandwidth products of main amplifiers and axil-
in < Lin
lary amplifiers are assumed equal. From this, a relationship
3) Cin : As was demonstrated in (2), Cin consists of Cgs1 , 0 0
between gm1 Rc and gm3 , RL , gm3 , and RL is obtained. This
the negative Miller capacitance from Cgd1 , and the positive 0
relationship, (8), and the same assumptions as for the RGC RT
Miller capacitance due to Cgs3 . Therefore, as the sum of the derivations at the end of Appendix A, lead to the MIC-TIA
Cgd1 term and the Cgs3 term stays nearly unchanged with transimpedance limit
∆, the input capacitances of MIC and RGC TIAs are nearly  0 0

the same when TIAs are built from identical components. gm2 + gds1 gm2 (A0 f0 )2 1 (A0 f0 )2
Simulations of an MIC TIA and an RGC TIA implemented RT ≤ 0 ≈ .
0
(gm2 × ∆ + gds1 ) gm2 2πCT χ2 BW 3 ∆ 2πCT χ2 BW 3
with the same circuit components show Cin . Cin . (10)
As a result
 0 0

D. Poles of the MIC TIA transfer function RT gm2 + gds1 gm21
0 ≈ 0 ≈ . (11)
The complex-conjugate pole-pair natural frequency and the RT (gm2 × ∆ + gds1 ) gm2 ∆
quality factor, governing in-band ripple and TIA stability, are In order to demonstrate the transimpedance limit advantage
found as of the MIC TIA, an RGC TIA and an MIC TIA in Fig. 3(a)
q −1 were optimized in a standard IBM 0.13-µm CMOS technology
ef f −1
ω0 = CT Lin and Q0 ≈ (ω0 Rin CT ) . (6) with a 1.5-V supply. Both TIAs were optimized to achieve
the maximum possible transimpedance gain for a given 3-
In addition to the complex-conjugate pole-pair, the transfer dB bandwidth of 10 GHz and a total current draw of 2 mA
function has a real pole at the output node. To find the while the quality factors of their complex-conjugate poles were
location of the pole, the b2 coefficient in (B3) of the s3 -term limited so that within the passband the transimpedance-gain
in the denominator of the MIC TIA transfer function (B1) is frequency response exhibited no more than 0.1dB deviation
analyzed. For a system with one complex-conjugate

−1 pole pair from a 3rd-order Butterworth response. For the MIC TIA,
at ω0 and a real pole at ωp1 , b2 = ω02 ωp1 . Comparing a transimpedance limit of 380 Ω was achieved (optimum

−1
(B3) to b2 = ω02 ωp1 and by using (4) in (6) it can be ∆ = 0.79), whereas the RGC TIA achieved a transimpedance
shown that limit of 310 Ω. Therefore a transimpedance limit improvement
of 23% was simulated and is similar to 27% predicted by (11).
1 1−∆ 1 gm3
ωp1 ≈ + = + RL gds1 . (7)
RL Cout Rc C x RL Cout Cx
F. Noise Analysis of the MIC TIA
Therefore, the location of the real pole at the output node
can be altered by the selection of the Rc Cx time constant The noise behavior of the MIC TIA determines the sensi-
if ∆ is held constant. In other words, if RL is selected tivity of the optical receiver. In this paper we use the input-
large to improve the transimpedance gain, the reduction in the referred noise current spectral density and the average input-
1/RL Cout term can be compensated with the 1/Rc Cx term. referred noise current [19] to characterize the noise perfor-
If ∆ is not held constant, ωp1 dependence on RL is seen from mance of the MIC TIA. Assuming CT  Cx , CT  Cout ,
the last part of (7). gds1  gm2 , and using the simplified model in Fig. 3(d), the
total equivalent input-referred mean-squared noise current of
the MIC TIA is obtained by adding the uncorrelated input-
E. Transimpedance limit improvement referred mean-squared noise contributions from each circuit
The advantages of an MIC TIA over an RGC TIA translate component, i.e. M1 , M2 , M3 , Rc and RL , shown in Fig. 5,
into an improvement of the MIC TIA transimpedance limit,
RT . To roughly estimate the improvement, if it is assumed
i2n,eq ≈ i2n,eq,M 1 + i2n,eq,M 2 + i2n,eq,M 3 + i2n,eq,Rc + i2n,eq,RL
that an MIC TIA and an RGC TIA are designed for the same
(12)
frequency response and the same time-domain response (i.e.
0 0 0 where the individual mean-squared noise currents are
Q0 = Q0 , ω0 = ω0 , ωp1 = ωp1 ), that the gains of their
0 0 0
auxiliary amplifiers gm1 Rc ≈ gm1 Rc , and that CT ≈ CT , ω 2 CT2 gm1 Rc2 Γ1
0 0
f0 i2n,eq,M 1 ≈ 4kBT , (13)
then the two TIAs should have Rin = Rin and Lefin
f
= Lef
in . (1 + Rc gm1 )
2
 the beginning of this section, (12)-(17) are the same as for an
in,RL C RGC TIA and therefore when designed with the same circuit
out RL Rc Cx components, the noise performance of the two TIAs should
in,Rc be very similar but the MIC TIA would have lower Rin and
wider bandwidth. If an MIC TIA is designed to have the same
vout frequency response as an RGC TIA, according to (8) its gm3
gm2v2 would be reduced, which would increase the equivalent input-
in,d3 referred noise as seen from (15) and (17) but reduce its power
gm3v3 v3 v2 in,d2 consumption.

G. Design procedure
Having investigated the characteristics of the MIC TIA, the
gm1v1 in,d1 following design procedure is suggested. First, for a given
CT gds1 desired transimpedance gain RT , RL = RT is chosen. Then,
v1
we start by assuming that ∆ ≈ 1. This makes the MIC TIA
performance resemble that of an RGC TIA, whose design can
proceed using standard RGC design steps [4]. Once the circuit
Fig. 5. MIC TIA small-signal model for noise analysis. Only major noise components of an RGC TIA are selected, it is re-connected in
sources are shown. an MIC TIA configuration. Relative to the RGC TIA, for the
2
ω 2 CT2 gds1 Rc2 Γ2
i2n,eq,M 2 ≈ 4kBT 2, (14) MIC TIA, Q0 and ω0 will increase whereas ωp1 will either
gm2 (1 + Rc gm1 ) increase, if Cout is dominated by the TIA load as ∆ becomes
less than 1, or otherwise decrease. Circuit parameters are then
h i
2
ω 2 CT2 1 + (ωCx Rc ) Γ3
i2n,eq,M 3 ≈ 4kBT , (15) tuned to achieve the desirable performance.
2
gm3 (1 + Rc gm1 ) Since the improved behavior of the MIC TIA over an RGC
TIA comes from the term ∆ defined in Table I, which is
ω 2 CT2 Rc
i2n,eq,Rc ≈ 4kBT 2, (16) dependent on gds1 , a way of adjusting the TIA operation
(1 + Rc gm1 ) when it is a part of an optical receiver is needed. In this
and work, to adjust ∆, Rc was tuned. This way, ω0 and Q0 of
the MIC TIA complex-conjugate poles can be adjusted to set
! the appropriate amount of peaking. In an optical receiver, a
4kBT ω 2 CT2 simple yet effective procedure described in [22] can be used
i2n,eq,RL ≈ 1+ 2 , (17)
RL 2 (1 + R g
gm3 c m1 ) to adjust Rc .
where k is Boltzmann’s constant, T is the reference tem-
perature of 290 K, B is the equivalent noise bandwidth, and III. M EASUREMENT RESULTS
Γ1,2,3 are Ogawa’s excess noise factors of M1,2,3 [20], [21]. As a proof of concept the proposed MIC TIA was fabricated
The mean-squared noise current contributed by a large resistor in a 0.13-µm IBM 8SRF CMOS technology. The implemented
(600 Ω in the implemented TIA), used instead of Ibias in Fig. circuit schematic of the MIC TIA, along with its parameter
3(a), is ignored as this current is relatively small. The currents values, is shown in Fig. 6(a). The chip micrograph of the
in (13)-(17) are found by using Miller approximation and implemented TIA is shown in Fig. 7. A 250 fF MIM capacitor
ignoring the higher order terms, which results in inaccuracy is used at the input to emulate the photodiode to evaluate the
at frequencies above the MIC TIA bandwidth as will be circuit performance [23]–[25]. Because not all design trade-
visible in the measured data in Section III. As seen from offs were understood at the time of tape out, the pre-layout
(13)-(17), the thermal noise contribution of RL is dominant simulated circuit had ω0 = 9.4 GHz with Q = 1.6 and
at low frequencies and the terms containing ω 2 CT2 become χ ≈ 1.4 with a transimpedance gain of 330 Ω. A better-
dominant at high frequencies. Since Rc gm1 appears in every optimized MIC TIA for the maximum transimpedance limit
denominator of the noise currents in (13)-(17), gm1 must would have achieved ω0 = 9.8 GHz with Q = 1.1, χ ≈ 1, and
be large to reduce noise at high frequencies. However, gm1 a transimpedance gain of 530 Ω. However, since the optimized
cannot be increased indefinitely since its increase increases parameters were not available at the time of the tape-out,
Goi and reduces Rin (see (3)) resulting in a larger Q0 (see parameters identified as “Implemented” in Fig. 6 were used.
(6)) and, thus, in ripple in the frequency response. The noise The pole locations of the implemented circuit and optimized
contributions from M2 and M3 can be reduced by increasing circuit are shown in Fig. 6(b).
gm2 and gm3 , respectively. Hence, there is a trade-off between To estimate the process, voltage, and temperature (PVT)
low-power design, low-noise design, large transimpedance variation effects on the proposed TIA, a 200-iteration Monte-
gain, and bandwidth. Low-noise design is often overlooked Carlo simulation was performed with its results shown in Fig.
for a larger bandwidth and/or transimpedance gain. In our 8. As seen, the variations are mainly in the peaking in the
circuit, the sizes of the transistors are designed to optimize the transfer function as is expected because of its dependence on
transimpedance gain. Note that under the assumptions made at gds1 . A PMOS transistor in triode in parallel with Rc was used
 Transimpedance gain (dBΩ)
jω
VDD VDD Implemented 50 15
Wt Optimized
Rc Vtune
RL 2π×5 GHz
40 12

k factor
vout Mt
W3 W2
σ 0
M3 M2 30 9
W1
CPD M1 -2π×5 GHz
Rbias
20 6
-2π×5 GHz
(a) (b) 10 Simulated 3
Design parameters Implemented Optimized Measured
0 Estimated 0
W1, W2, W3, Wt (µm) 22, 10, 12, 12 16, 7, 7,12 1 10
Rbias, RL, Rc (Ω) 600, 285, 250 900, 530, 220 Frequency (GHz)
Fig. 6. (a) Circuit schematic of the implemented TIA with parameter Fig. 9. Transimpedance gains obtained with post-layout simulations, mea-
values and all minimum length transistors and (b) pole locations of the sured, and estimated using (B1)-(B5). Measured stability factor is shown.
final implemented circuit and the optimized circuit using the procedure in
Section II-G. If used in the fabricated TIA, the optimized parameters would 80
have improved the TIA performance by increasing its bandwidth and making

GDV=±19 ps
χ closer to 1. At the time of the tape-out not all design trade-offs were
understood and the implemented circuit was built with design parameters
identified as “Implemented”. Group Delay (ps) 60 Td=100ps

40
GND GND
180 µm
20
90 µm

VDD
IN OUT 3dB bandwidth

GND GND GND

0

0 5 10 15 20
Fig. 7. Chip micrograph of the MIC TIA in 0.13-µm CMOS. Frequency (GHz)
Fig. 10. Measured transimpedance group-delay along with the extracted
output eye diagram for a 10 Gb/s 29 −1 pseudo-random bit sequence (PRBS).
during measurements to compensate for this and adjust gain
60 peaking to less than 1dB. This transistor would be used when
the TIA is calibrated as part of an optical receiver.
Transimpedance gain (dBΩ)

Additional bond pads were also separately implemented

50 for accurate de-embedding. The TIA was wafer-probed to
measure its S-parameters. From these measurements, the tran-
40 simpedance gain is evaluated from
2S21
Z21 = Z0 , (18)
30 (1 − S11 )(1 − S22 ) − S12 S21
where Z0 = 50Ω [26]. The measured transimpedance gain and
20 the stability factor of the MIC TIA are shown in Fig. 9 where
the expected gain from post-layout simulations, and estimated
10 gain with (B1)-(B5), which ignore some high-frequency poles,
are also shown. The gain is 50.1 dBΩ at DC and the 3-
dB bandwidth is 7 GHz. The TIA is unconditionally stable
0 with a minimum k-factor of 1.6 calculated from the measured
1 10
Frequency (GHz) S-parameters. The group-delay variation (GDV), determined
Fig. 8. A 200-iteration Monte-Carlo simulation of the transimpedance gain.
from the measured S-parameters, is shown in Fig. 10 to be less
than ±19 ps over the 3-dB bandwidth. Since the implemented
circuit is a single-stage TIA, the eye diagram cannot be
Input equivalent noise current (pA/sqrt(Hz)) 70 TIA in [3] benefits from lower parasitic capacitance and
Calculated much larger intrinsic operating frequency of 40-nm CMOS
60 Small-signal circuit transistors to trade off the TIA power consumption with gain.
Post-layout simulation
Measurement
Even though the implemented MIC TIA consists of only a
single stage, its performance in terms of the transimpedance
50
gain is comparable with other published circuits that employ
a larger number of stages and larger power consumption to
40 improve their gain.
IV. C ONCLUSION
30
An MIC TIA is proposed in this paper. Simulations show
that the performance of an RGC TIA can be substantially
20
improved by using the MIC circuit. The proposed configura-
tion relaxes the input impedance limitation of the RGC TIA,
10 achieving higher transimpedance limit and bandwidth while
3dB Bandwdith consuming less power than a conventional RGC TIA. The TIA
0 concept was validated with a single-stage inductorless TIA de-
0 2 4 6 8 signed for 10-Gb/s data rate and fabricated in 0.13-µm CMOS
Frequency (GHz)
technology. The measured TIA achieved 7 GHz banwidth and
Fig. 11. Measured, simulated, and calculated equivalent input-referred noise 50.1 dBΩ transimpedance gain, while consuming 7.5 mW of
current . Equation (12) is used to calculate the equivalent noise-current with
Γ = 2. Two simulation results are shown: a more complete small-signal power.
circuit than was shown in Fig. 5 with all other parasitic capacitances, biasing
resistor in Fig. 6 and a post-layout simulation. A PPENDIX A
measured directly. However, since in practical applications R EVIEW OF RGC TIA S
with CMOS photodiodes, the input signals at the TIA input An RGC TIA in Fig. 1(b) is reviewed in this appendix to
are small, the eye diagram can be estimated from the measured highlight the advantages of the proposed MIC TIA. In the
S-parameters as recommended by [27], [28]. The resultant eye model of the RGC TIA input impedance in Fig. 1(d), the input
diagram, shown in Fig. 10, indicates that group delay is small resistance at low frequencies is
but does ignore the circuit noise, not captured by the measured
0 0
S-parameters. 0 g +g
Rin |gds0 2,3=0 ≈  0 m2 0 ds10 , (A1)
In order to determine the input-referred noise current density 0 0
gm3 gm2 (1 + gm1 Rc ) + gds1
of the TIA, the noise parameters were measured from 1 GHz 0 0 0
to 10 GHz. The input-referred equivalent noise current was where gm1,3 are the transconductances of M1,3 , and gds1,2,3
0
extracted from the noise parameters and illustrates a reason- are the output conductances of M1,2,3 . Drain-source conduc-
0
able agreement with simulations over the 3-dB bandwidth tance gds1 was deliberately included in the derivations of
shown in Fig. 11. Fig. 11 also shows calculated input-referred (A1), as its equivalent (gds1 of the MIC TIA) is important
equivalent noise-current using (12) as well as simulated input- for the MIC TIA input resistance as shown in Section II-B.
referred equivalent noise-current of a more complete small- The transimpedance gain of this circuit at low frequencies is
signal model, which includes all gate-drain and gate-source given by
capacitances, biasing resistor, Rbias , in Fig. 6, and bond pads. 0 0
Fig. 11 illustrates that, while the noise currents in (13)-(17) are RT = RL . (A2)
derived for a simplified circuit in Fig. 5 and by using Miller The transimpedance transfer function is of the form
effect, a more accurate estimate requires a more complete
model, which accounts for higher order poles and better 0

s

predicts the high-frequency gain of the MIC TIA that is used vout RT 1 + 0
ωz1
when referring noise to the TIA input. The rms noise current of ZT (s) = =  , (A3)
iin s2
2.6 µA was obtained by integrating the measured noise current 1 + ωs0 1+ 0
s
ω0 Q0
+ 0
ω02
p1
density up to twice the 3-dB bandwidth as noise contributions
where an analysis of the small-signal model of the circuit in
beyond that frequency become insignificant [19]. By dividing
Fig. 1(b) gives
the rms
√ noise current by the root of the TIA bandwidth, 31.3
pA/ Hz average input noise current is obtained. 0 1 0 1 + gm1 Rc
0 0

Table II summarizes the performances of the TIA, other re- ωp1 = 0 0 , ωz1 = , (A4)
RL Cout Rc0 Cx0
cently published 10-Gb/s TIA, which proposed improvements
to the RGC topology [3], [9], [24], and a TIA employing an r
0
(1+gm1 Rc0 ) 0
CT Rc0 Cx0
s
immittance converter [18]. All previously published TIAs in 0
0 0
gm3 (1 + gm1 Rc ) 0
0 0
gm3
Table II employ extra stages, and [9], [24] use inductors, to ω0 = 0 0 0 , Q0 = 0 ,
CT Rc Cx CT
+ Rc0 Cx0
increase their transimpedance gains. With the exception of 0
gm3
the TIA in [3], the TIAs also consume more power. The (A5)
 TABLE II
P ERFORMANCE SUMMARY OF THE PROPOSED AND OTHER PUBLISHED 10-Gb/s TIA S .
Ref This work [24] [3] [9] [18]
BW(GHz) 7 7 8 5 4
RT (dBΩ) 50.1 55 47 56.7 46
√
Noise (pA/ Hz) 31.3 17.5 22 - 10
CP D (fF) 250 300 450 500 250
Vdd (V) 1.5 1.8 1.1 1.8 1.8
Power (mW) 7.5a 18.6 2.03 27.2 10.7b
Number of stages 1 3 3 3 2
Inductors 0 1 0 1 0
Group-Delay (ps) ±19 ±10 - - ±25
Active area (mm2 ) 0.016 0.1c 0.0002 - 0.35c
Immittance-converter RGC with Inverter-based Modified RGC with Cross-coupled
TIA topology
RGC series peaking RGC series peaking Immittance converter
Technology 0.13-µm CMOS 0.18-µm CMOS 40-nm CMOS 0.18-µm CMOS 0.18-µm CMOS
a Out of total 7.5 mW, M consumes 1.65 mW;b The power consumption excludes a 50-Ω output-matching buffer.
3
c Area includes an input bond pad

0 0
and Cx is the total capacitance at node X , which is identified where a0 = RL ,
0
in Fig. 1(b). The frequency of zero ωz1 is normally high
0 √
−1 Cx Rc RL (gm2 + gds1 )
enough to be neglected. Setting Q0 ≤ 2 guarantees a1 = , (B2)
gm2 (1 + Rc gm1 ) + gds1
a flat frequency transimpedance response with the 3-dB band-
width being smaller than either the output pole frequency
0 0 Cout CT Cx Rc RL (gds1 + gm2 )
2πBW ≤ ωp1 or the frequency of the complex-conjugate b2 = . (B3)
0 0 gm3 [gm2 (1 + Rc gm1 ) + gds1 ]
pole-pair 2πBW ≤ ω0 . Equalities are obtained in the first
0 0 0
case when χ = ω0 /ωp1 is large, and in the second case when and other definitions are shown in (B4)-(B5).
0
χ is small.
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(B4)
(B5)
Mohammad Hossein Taghavi received the B.S.
degree in electrical engineering from the Amirkabir
University of technology, Tehran, in 2004, and the
M.S. degree in electrical engineering from Sharif
University of Technology in 2006. He is currently
working toward the Ph.D. degree in electrical en-
gineering at the University of Calgary. His research
interests include high-speed analog/RF circuit design
for wireless and wired communications. Mr. Taghavi
was a recipient of the Research Productivity Award
from University of Calgary, 2013, and the Outstand-
ing Student Designer Award from Analog Devices, Inc., 2014.
Leonid Belostotski (S’97–M’01-SM’14) received
the B.Sc. and M.Sc. degrees in electrical engineering
from the University of Alberta, Edmonton, AB,
Canada, and the Ph.D. degree from the University of
Calgary, Calgary, AB, Canada, in 1997, 2000, and
2007, respectively. From 2001 to 2004, he was an
RF Engineer with Murandi Communications Ltd. He
is currently an Associate Professor with the Univer-
sity of Calgary, Calgary, AB, Canada, and Canada
Research Chair in High-Sensitivity Radiometers and
Receivers. His current research interests include RF
and mixed-signal ICs, high sensitivity receiver systems, antenna arrays, and
terahertz systems. Dr. Belostotski was a recipient of the IEEE Microwave
Theory and Techniques MTT-11 Contest on Creativity and Originality in
Microwave Measurements in 2008 and the Outstanding Student Designer
Award from Analog Devices, Inc., in 2007. He is an IEEE Southern Alberta
Solid-State Circuits and Circuits and Systems Chapters’ Chair.
James W. Haslett (S’64–M’66–SM’79–F’02–
LF’10) is a Lifetime Professor Emeritus in the De-
partment of Electrical and Computer Engineering at
the University of Calgary. He has been an academic
staff member for the past 44 years, and was the
Head of the EE Department at Calgary from 1986-
1997. Dr. Haslett is currently the Director of the
provincial iCORE (informatics Circle of Research
Excellence)-funded Advanced Technology Informa-
tion Processing Systems (ATIPS) Lab at the Uni-
versity of Calgary, and Co-director of the Advanced
Micro/nanosystems Integration Facility. He held the TRLabs/iCORE/NSERC
Senior Industrial Research Chair in Wireless Communications from 2002
to 2007, specializing in radio frequency integrated circuit (RFIC) design
for wireless communications applications. His current research focuses on
radio frequency integrated circuit design for next-generation radio astronomy
applications, and on time-based circuits for wireless and wireline data com-
munications. He has published over 200 papers in peer-reviewed journals and
conference proceedings, and holds/co-holds 12 patents, several of which have
been licensed to industry. He has graduated over 40 MSc and PhD students
during his career. Dr. Haslett is a Life Fellow of the Institute of Electrical
and Electronics Engineers (IEEE), a Fellow of the Engineering Institute of
Canada, and a Fellow of the Canadian Academy of Engineering.
Peyman Ahmadi graduated from Noushirvani Uni-
versity, Babol, Iran, in 2007 with B.S. degree. He
received his M.S degree from University of Cal-
gary, Calgary, Canada, in 2011, and he is currently
working toward his Ph.D. degree at the University
of Calgary. His research activity is focused on RF
circuits and systems, including delay circuits and RF
beamforming. Currently, he is conducting research
on first- and second-order all-pass filters and their
applications and on the design and fabrication of
wideband spatial beamformers.