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1996 DFIG Using Back-To-back PWM Converters and Its Application To Vs Wind EG
1996 DFIG Using Back-To-back PWM Converters and Its Application To Vs Wind EG
8, AUGUST 2013
Abstract—In this paper, an FPGA-based fault-tolerant back- like steering, fuel pumps, and brake-by-wire [1]–[3]. Also, in
to-back converter without redundancy is studied. Before fault oc- power generation units like distributed generation and renew-
currence, the fault-tolerant converter operates like a conventional able power units, halt of the system after a fault results in
back-to-back six-leg converter, and after the fault, it becomes
a five-leg converter. Design, implementation, and experimental financial loss.
verification of an FPGA-based reconfigurable control strategy for Therefore, to prevent unscheduled shutdown, real-time fault
this converter are discussed. This reconfigurable control strategy detection and converter reconfiguration schemes for back-to-
allows the continuous operation of the converter with minimum back converter must be implemented.
affection from a fault in one of the semiconductor switches. A very In order to make a suitable reaction to a fault in one of the
fast detection scheme is used to detect and locate the fault. Im-
plementation of the fault detection and of the fully digital control semiconductor devices, the first step consists of fast detection
schemes on a single FPGA is realized, based on a suited method- of the fault and its location. Several papers have discussed
ology for rapid prototyping. FPGA in loop and also experimental fault detection schemes for power electronic converters. Fault
tests are carried out, and the results are presented. These results detection in a multilevel converter is studied in [4], [5]. A de-
confirm the capability of the proposed reconfigurable control and tection method for faults in IGBT switches based on gate signal
fault-tolerant structure.
monitoring is presented in [6]. An observer-based method is
Index Terms—Back-to-back converter, fault detection, fault- used in [7] to detect the fault in the sensors of a converter.
tolerant converter, field programmable gate array (FPGA), five-leg Open-circuit faults in matrix converters are studied in [8].
converter, hardware in the loop (HIL).
Nonlinear observers are used in [9] to detect open-switch faults
in induction motor drives. Another method for detection of
I. I NTRODUCTION
open-switch faults in voltage source inverters feeding ac drives
D. Reconfigurable Control
Fig. 6 shows the proposed reconfigurable control for the
fault-tolerant 6/5-leg converter. The fault detection and recon-
figuration unit decides whether to use the commands from the
“six-leg PWM” block, or to compute and use the appropri-
ate five-leg PWM signals based on the fault’s location. It is
important to detect the fault and change the control strategy
as soon as possible, to avoid any discontinuity or undesirable Fig. 7. One leg of converter during an open-circuit fault in the upper switch.
transient in the inputs and outputs of the converter. Therefore,
the proposed reconfigurable control of Fig. 6 is implemented
on an FPGA, due to its parallel structure and high speed. In the fault quickly and efficiently. In [11] and [12], it is shown
fact, system monitoring for fault detection must be performed in that the fault occurrence in each leg can be diagnosed by
parallel with other system tasks. Therefore, more conventional comparing the measured and estimated pole voltages. However,
software-based processors like DSPs are not the most suited to in reality, due to measurement and discretizing errors, and
perform very fast fault detection and control reconfiguration. mainly because of nonideal behaviors of switches and drivers
This is mostly because the main performance limitation of such (turn-off and turn-on propagation time and dead time generated
processors is their serialized treatment of the instructions to ex- by the drivers), the voltage error is not zero during normal
ecute the code, also having to wait for interrupt service routine operation. To avoid false fault detections, two adjustments are
loops [14]. On the other hand, FPGA can execute all its tasks employed to compensate the effect of the measurement errors
simultaneously by hardware implementation of the design. This and delays. For this purpose, first the absolute value of the error
characteristic can lead to drastic reduction in execution time between measured and estimated pole voltage is calculated.
[26], [27]. Moreover, particularly in the studied fault-tolerant Then, this value is applied to a comparator with a threshold
application for power electronic converters, processing at logic value “h,” to determine if the difference between the measured
level seems to be the best choice for real-time consideration. and estimated voltages is large enough to be considered as an
Programmable logic enables rapid control/corrective action, error. Then, this signal is applied to an up-counter that computes
which is mandatory in fault-tolerant applications. Therefore, the number of pulses while the output of the first comparator is
FPGA appears as an excellent choice for our application. On high. In the other words, the output of the up-counter corre-
the other hand, it could be possible to use a software-based sponds to the time during which vknm (measured voltage) and
processor to compute the switching orders and use an FPGA for vknes (estimated voltage) are different. Consequently, the fault
fault detection and compensation. However, since the feasibility occurrence is detected using simultaneously a “time criterion”
of FPGA for a variety of power electronics applications is and a “voltage criterion.” To do this, the up-counter output is
already approved [13]–[16], in this paper, a single FPGA is applied to a second comparator with a threshold value of “N.”
used for both purposes. In this manner, potential interface In this way, false fault detection due to semiconductor switching
problems are avoided. In Section V, the FPGA implementation is avoided, and fault can be detected very fast. Fig. 7 shows one
is discussed. A methodology for rapid prototyping, developed leg of the converter, while there is an open-circuit fault in the
in our laboratory, is used and expanded for fast implementation upper switch. Note that in some cases, based on the direction
of the proposed reconfigurable control for the fault-tolerant of the current ik , there might be a condition that Dk conducts
6/5-leg converter. instead of Sk ; therefore, in this case, the converter operates
normally, and the fault cannot be detected. For example, while
Tk = 1 and ik < 0, Dk is on. Here, Tk is the command signal
IV. FAULT D ETECTION AND R ECONFIGURATION
for the upper switch of the leg k. Tk = 0 indicates that the
Fast fault detection is essential for FTSs. Here, the method switch is commanded to be open, while Tk = 1 means that the
detailed in our earlier contributions is used for detection of fault switch is commanded to be closed. The switch commands in
and its location [11]. Using this method, it is possible to detect each leg are complementary.
SHAHBAZI et al.: FPGA-BASED RECONFIGURABLE CONTROL FOR FAULT-TOLERANT BACK-TO-BACK CONVERTER 3365
A. HIL Results
For HIL experiment, the controller and detection schemes are
implemented on the same FPGA chip and the power system
is modeled in MATLAB/Simulink environment using the Sim-
PowerSystem toolbox. As stated earlier, three-phase voltages at
the source side are controlled to provide the ability of the dc-
link voltage regulation at unity input power factor. This is done
using a well-known source-voltage-oriented control method for
Fig. 11. FPGA implementation flow.
three-phase controlled rectifiers [28]. Voltage references at the
load side are balanced and sinusoidal.
FPGA devices. However, some of desired functions are not Two sets of voltage references obtained from these con-
available in Dspbuilder library and must be constructed from trol schemes are sent to the appropriate six-leg or five-leg
basic blocks or imported using HDL programming. The power PWM blocks, based on the state of the converter. PWM block
part (fault-tolerant converter, sources, and charges) is remained for a five-leg converter has a preprocessing unit as stated in
unchanged in this step, modeled by using SimPowerSystem (1) and (2).
blocks. Appropriate Dspbuilder input and output blocks are System parameters are reported in Table I. An open-circuit
necessary to convert the Simulink signals to fixed point signals fault is introduced in one of the semiconductor switches in order
for Dspbuilder. to evaluate the response of the fault detection scheme and to
Finally, in the third step, having validated Dspbuilder model- validate the effectiveness of the fault-tolerant converter.
ing by simulations, the blocks are translated into VHDL. This First, an open-switch fault is applied at time t = 0, 5 s in the
is done by using the signal compiler block which is available lower switch of the leg “3 ” in the inverter side (consisted of
in the Dspbuilder library. After this step, a single HIL block S3 and S6 , in Fig. 3). The goal is to evaluate the proposed
replaces all of the Dspbuilder blocks. The VHDL design is reconfigurable control and its implementation on the FPGA.
compiled and downloaded to the FPGA via a Joint Test Action Fig. 13 shows the fault occurrence and detection and also
SHAHBAZI et al.: FPGA-BASED RECONFIGURABLE CONTROL FOR FAULT-TOLERANT BACK-TO-BACK CONVERTER 3367
TABLE I
S YSTEM PARAMETERS
Fig. 13. Fault occurrence and detection. Fault is detected when the counter
output reaches the value of 32.
Fig. 17. Zoomed view of detection waveforms when i3 > 0 (fault at t = Fig. 19. Vdc for fault when i3 > 0 (fault at t = 0.486 s).
0.486 s).
Fig. 23. From top to bottom: dc-link voltage (50 V/div), fault- (x-axis:
100 μs/div).
Fig. 22. From top to bottom: fault, fault detection, and counter output-(x-axis: Fig. 24. Fault occurrence when i3 > 0; from top to bottom: fault, fault
100 μs/div). detection, counter’s output, load current (5 A/div)—(x-axis: 5 ms/div).
can continue supplying the load, and the proposed fault de-
VII. C ONCLUSION
tection and reconfigurable control produces satisfactory results.
These results show excellent operation of the proposed recon- This paper presents and validates a high-performance fault
figurable fault detection and control, as well as its FPGA imple- detection and reconfigurable control for a fault-tolerant con-
mentation and the studied fault-tolerant back-to-back converter. verter. A three-phase fault-tolerant back-to-back converter with
3370 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 8, AUGUST 2013
Mahmoud Shahbazi was born in Mahallat, Iran, Shahrokh Saadate was born in Tehran, Iran, on
in 1983. He received the B.S. degree in electrical May 6, 1958. He received the Diplôme D’ingenieur,
engineering from the Isfahan University of Technol- DEA, Thèse de Doctorat degrees, and Habilitation à
ogy, Isfahan, Iran, in 2005, and the M.S. degree in diriger les recherches from ENSEM, INPL, GREEN
electrical engineering from Amirkabir University of Laboratory, Nancy, France, in 1982, 1982, 1986, and
Technology, Tehran, Iran, in 2007. Currently, he is 1995, respectively.
working toward the Ph.D. degree in a collaboration Currently, he is the Head of GREEN Laboratory at
between the Université de Lorraine, Nancy, France, the University of Lorraine, Nancy, France. His main
and the Sharif University of Technology, Tehran, research domain is power systems reliability, power
Iran. quality, and renewable energies.
His research interests are wind energy conversion
systems, power electronic converters, and fault-tolerant converters.
Mohammad Reza Zolghadri (M’05) received the
B.S and M.S. degrees in electrical engineering from
the Sharif University of Technology, Tehran, Iran,
and the Ph.D. degree in electrical engineering from
Philippe Poure (M’08) was born in 1968. He re- the Institute National Polythechnique de Grenoble,
ceived the Engineer degree and Ph.D. degree in Grenoble, France, in 1989, 1992, and 1997,
electrical engineering from INPL-ENSEM-GREEN, respectively.
Vandoeuvre-lès-Nancy, France, in 1991 and 1995, Since 1997, he is with the Department of Electrical
respectively. Engineering, Sharif University of Technology. From
From 1995 to 2004, he was an Associate Profes- 2000 to 2003, he was a Senior Researcher in the
sor and worked at the University Louis Pasteur of Electronics Laboratory, SAM Electronics Company,
Strasbourg, France, in the field of mixed-signal Tehran, Iran. From 2003 to 2005, he was a Visiting Professor in the North
system-on-chip for control and measurement in elec- Carolina A&T State University, Greensboro. His fields of interests are appli-
trical engineering. Since September 2004, he joined cation of power electronics in renewable energy systems and hybrid electric
the Université de Lorraine, Nancy, France, and works vehicle, variable speed drives, and modeling and control of power electronic
on fault-tolerant power systems and field-programmable gate array-based real converters. He is the author of more than 70 publications in power electronics
time applications. and variable speed drives.