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ASIC InterviewQuestions PDF
ASIC InterviewQuestions PDF
Ans:
uvm_config_db#(virtual pcie_monitor_phy_if)::set(this, “phy_agent”,”pcie_monitor_phy_vif”,
pcie_monitor_phy_vif_handle);
uvm_config_db#(virtual pcie_monitor_phy_if)::set(this,””,”pcie_monitor_phy_vif”,
pcie_monitor_phy_vif_handle);
2. Write constraint to get address field value for power of 2 , and aligned at boundary of
4.data== address.
Ans :
(Didnt get what does data==address want to indicate here, though I will write ans as per my understanding)
rand bit [31:0] addr ;
rand int temp[31:0] ;
constraint c_power_of_2 {
addr[1:0] == 2'b0 ; // THis will align the address at boundary of four.
temp.sum() == 2'b01;
foreach(temp[i]) {
temp[i] == addr[i];
}
}
3. Instantiation of environment class in testcase.
Ans:
in sv,
env = new();
env.build();
env.run();
or env.start(); whatever method we have created
in uvm
env=my_env_class::type_id::create(“env”,this);
4. Establishing question between driver and agent.
Ans: Driver has port of type uvm_seq_item_pull_port and sequencer has port of type
uvm_seq_item_pull_export. They are connected inside agent. Whenver driver calls get_next_item method of
seq_item_pull_port, it ultimately commands sequencer to generate a transaction.
5. Implicit execution of sequence through config db.
Ans: Every sub phase of run_phase can have its default sequence. Default sequence can be set by user
with following syntax :
uvm_config_db#(uvm_object_wrapper)::set(this,”path.to.sequencer.main_phase”, “default_sequence”,
sequnce::type_id::get());
6. Driver code to get request and process request .
seq_item_port.get_next_item(req);
…
item_done(rsp);
or
item_done();
seq_item_port.put_response(rsp);
or
rsp_port.write(rsp);
Coverage related question :
Code coverage and functional coverage.
One candidate was asked:
Please find the questions attached herewith. questions were asked related to these topics and further
discussion on same, like crossquestioning on your given answer.
1)
What is factory?
A: Factory is used to create objects based on type or name. For that the uvm_components and uvm_objects
should be registered with factory so that whenever required, objects can be created using factory.
2)
what does `uvm_component_does?
A: Registers the class with factory and also same macro can be utilized to implement copy/compare/print etc
default methods.
3)
uvm_env hierarchy, who is instantiated where?
A:
uvm_env contains uvm_agent, uvm_sequencer(virtual sequencers)
uvm_agent contains uvm_sequencer, uvm_driver and uvm_monitor
4)
how is driver & sequencer connected?
A: Already answered above
5)
test plan to verify a simple memory model?
6)
if you have a target of 100% coverage, what would be your approach?
Holes should be targeted, based on priority, required tests needs to be debugged/developed, if not
present.
Exclusion can be used to eliminate low priority bins and boost the coverage number
Coverage model implementation and sampling mechanism should be rechecked if test is already
present for the missing bin.
7)
what is code coverage, explain types of code coverage?
A: Coverage of RTL code, line coverage, fsm coverage(sub types:state coverage and transition coverage),
toggle coverage
8)
what does a typical uvm_driver contain?
Handle to virtual interface to be driven
mechanism to drive the interface(including unpacking transaction etc processes as per protocol)
callback implementation to change the transaction through callback
mechanism to extract the response from the bus
mechanism to provide response to sequencer(any one out of 3 methods)
9) explain polymorphism & why do we need it?
A: method of same names can have different functionality based on their implementation in different classes
of same heirarchy. we need it so that we can override base class method implementation in an extended
class method. It provides reusability of designs.
A small project where, lines of code was missing and I am supposed to fill the same.
two constraints in data_class, questions related to uvm_transaction_class, seq_item,etc
A: transaction class is not preferred over seq_item because sequencers deal in seq_item type and not in
uvm_Transaction type. Since in any tb, seq_item is mostly requried to frame the transaction,
uvm_transaction becomes obsolate and it is not used to avoid unnecessary level of heirarcy in transactions.
connect_phase driver & sequencer in agent
driver.seq_item_port.connect(sequencer.seq_item_export);
get_cfg_db virtual interface in agent
instantiate env in testcase in uvm
fill driver code few lines.
Another candidate was asked:
Subject: Re: UVM Interview Questions
11. How can you randomize dynamic array to generate unique values.
rand int d_arr[];
constraint c_dyn_arr {
d_arr.size() inside {[10:100]};
foreach(d_arr[i])
{
foreach(d_arr[j])
{
if(i != j) d_arr[i] != d_arr[j];
}
}
}
Here are the UVM testbench interview questions.
1. Asked questions about my Qualcomm Project. He spend good amount of time here asking
questions.
2. Which SystemVerilog data type you can use to generate sine wave. Answer is : Real
3. How can you randomize real data type.
a. Fraction and intgral parts can be randomized separately.
rand int frac, inte ;
real r_num;
constraint c_real{
frac inside {[10:100]};
inte inside {[30:300]};
}
function post_randomize();
r_num = inte + (frac/1000) ; // << instead of fixed value of 1000, it can also be
randomized with min value of 1000 till level of decimal
endfunction
b.
4. Explain about UVM factory.
5. What are the phases of factory.
Ans: uvm_factory doesn’t have any phase..if its about uvm ‘s phases then we have build, connect
etc.
6. Later he asked about question when I explained about factory.
7. How can you take an advantage of Polymorphysm.
a. Overriding methods in extended classes.
8. Explain about functional coverage. Give examples .
Ans: coverage of a feature, like a type of transaction is functional coverage.
9. Which project/customer you are currently working on.
Here are the PCIe Interview questions by Broadcom.
Please let me know if you want me to discuss ANSWERS with the engineers needed?
1. Do you know about Denali PCIe VIP.
2. Can you explain different layers in PCIe.
3. Do you know what is MRRS.
Ans: Max Read Request Size, a device should not send a read request greater than MRRS. It is
introduced to control the bandwidth occupied by each device.
4. Lets say EP wants to send data to RC. EP wants to transfer 1K Bytes of data from RC. But
RC supports only 256 bytes of transfer at a time. Explain how this transfer will happen.
Explain different major fields affected during this transfer.
Ans:
EP sends MrD pkt with Length = 256, Addr = xyz
RC will split the CPL and send min 4 CPLs. Here I write ‘min’ because splitting the cpl requires RC to
comply with a rule which says splitting can be done at only addresses which are naturally aligned multiples
of RCB (Read Completion Boundary whcih can be 64 or 128 bytes for RC). with length of intermediate
packets having payload in multiples of RCB.
5. Explain above same scenario for Read transaction.
Ans: above example was with read only because ep wants data from RC, so it has to read. For
MemWr scenario instead, RC initiates write transfer to EP with multiple MWr packets if MPS value is less
than total intended payload.
6. If there are no transfers happening between two PCIe devices (say RC and EP). What will
be your approach to debug this issue.
Ans : First link should be checked, then DL Link up should be checked and after that TL’s BAR
registers should be checked if they are properly configured or not.
7. Lets say EP wants to Write to Host memory which is connected to RC. Everything is fine
between two devices, Link is up. Only transfer is not happening. What do you think the
problem will be? How will you debug this?
Ans: BAR may not be configured and if BARs are configured properly address of TLP might not be
falling inside RC’s bar OR it might not be falling outside EP’s BARs(These two conditions can only route the
packet upstream, either address fallinginside RC’s Bar OR addr falling outside sender device’s own bar)
8. In Parallel PCIe protocol : there was some approach like.. iRequest and iReady.. Do you know if we
have something similar to that in PCI express?
9. Do you know "Slow Control" approach?
10. Can you explain Credit based flow control?
Ans : Credits are allocated to each device. They can not transfer more data than their available
credits.
11. We currently have PCIe Gen 2 VIP and test cases.. Do you think we can use existing test
cases when we move to PCIe Gen 3?
Ans: Yes they can be used but new tests needs to be developed.
12. What are thing we will have to change going from PCIe Gen 2 to PCIe Gen 3?
Ans: Phy layer needs to be changed for few things like encoding method, scrambling, mac needs
changes as new LTSSM state of equalization is introduced in Gen3, TL needs some changes for OBFF
msgs etc.
13. What is Replay Buffer? Explain how it works?
Ans: Replay buffer stores the transmitted TLP and upon not receiving ACK in stipulated time OR
receiving NAK all the packets in Replay buffer for whom ACK is not received OR NAK is received are
retransmitted. Replay buffer can be replayed 4 times max.
14. Do you know what is ASP? Explain..
Ans: Do you mean ASPM ? It is Active State Power management. Which is optional feature, if
enabled can be used to enter into low power states after sending DLLPs.
15. Have you work on Low power verification side?
16. Since how long that you worked on PCIe last?
Interviewer 1:
1. Explain your experience.
2. What is your relevant experience in UVM.
3. Explain the test bench in general in UVM.
4. How Dirver and Sequencer is connected.
Ans: Explained in one of the above questions
5. How Sequencer and Sequences communicate.
Ans: When driver calls get_next_item, sequencer calls body of sequence associated with it at that
time.
6. What are the phases of OVM_DO.
Ans : explaining uvm_do because I dont know uvm_do. seq.randomize(),
seq.start(sequencer_handle)
7. How to do you start a sequence on a particular sequencer.
Ans: seq.start(sequencer_handle), `uvm_do_on(seq, sequencer_handle)<< this will randomize the
sequence also
8. Explain virtual interface.
Ans: virtual interface is a handle/pointer to physical interface. physical interface can be synthesized
as part of design while virtual interface can not be. and it can point to actual interface and pointer can be
changed run time to another physical interface of same type.
9. Why do we not use physical interface instead of virtual interface.
Ans: Testbench uses classes and classes are dynamic data type(they get created and destroyed
run time) hence physical interface can not be used inside class and we need a pointer to physical interface
which is virtual interface.
10. If i have to modify my existing driver for some additional functionality in the environment, how will I
do it? Answer is : Factory and then asked questions on factory.
11. How monitor is connected with other components. answer is Analysis port.
12. How Analysis port is different than normal port and exports.
Ans: it uses function which can not be blocked(exits at zero sim time). there can be one tomany
connection using analysis port.
13. Explain scoreboard.
Ans: Scoreboard contains queues of transactions to be compared. Depending upon in order
comparison or out of order comparison implementation. Scoreboard can have three channels : Stimulus,
Expected and Response. Stimulus is taken from monitor at the input of RTL, based on Stimulus queue,
Expected transaction queues are created and stored. Monitor at output interface of RTL is stored as
Response. Everytime stimulus queue is updated, Emulation model takes the entry of Stimulus queue and
generates Expected trasaction(predicts output). WHich is compared when Output monitor delivers
Response transaction. Transactions are removed everytime a successful match happens. At the end of
simulation ( in check phase amy be) all queus are checked to be empty. Upon nonempty queue Error
should be reported.
14. She gave one example and asked to build scoreboard for the same.
following are the sequence of transaction
Write with addr 0
Write with addr 1
Read with add 0
Read with addr 1
Only one monitor is used to capture all above transaction. So in scoreboard how will you make sure
Write of addr 0 will be compared to read of addr 0 only.
She asked mostly everything to explain on the white board with the diagrams.
Interviewer 2:
1. How much have you work on UVM test benches.
2. Are you comfortable with module, subsystem level test benches?
3. Asked me to draw entire test bench for subsystem level. I drew entire test bench starting from Test
plan to Code coverage and funtional coverage closure.
Virtual sequencers and Virtual sequences.
Ans: Virtual sequencers are basically generic sequencers and they don’t connect themselves to any driver
and hence do not generate a transaction. Virtual sequencers control different data sequencers. Typical code
of virtual sequencer contain the handles to data sequencers. Sequences running on virtual sequencers can
have handles to different data sequences and data sequencers via p_sequencer handle. Virtual sequence
can initiate different data sequences on their respective data sequencers and control each of them
individually.
Possible Broadcom Interview questions
Following are the questions that were asked to one of our engineers:
This round was kind of introduction and project related queries like, what did I work on, what was test plan,
what language, scripting, etc. There was no technical SV/UVM questions or PCIe questions.
2nd Round
1. Tell me about your self
2. What would you rate yourself for UVM and SV out of 110 ratings
3. PCIe PHY Layer LTSSM, explain in detail with Substate details
4. What is use of FTS sequence.
Ans: To get out of L0s, FTS is transmitted. Number FTS OS depends upon value of symbol3 of TS1/2 OS.
5. Why 810bit encoding is required?
To reduce number of consecutive 1s and 0s and hence to avoid inter symbol interference.
6. How synchronization is done?
7. What is link and lane in PCIe? Max Lane number supported by PCIe? Ans: Link=num of lanes, 32 is
max supported lanes
8. Explain last PCIe project. What was your role?
9. What kind of tests you developed?
10. What error injection scenarios?
11. What is the role of Data Link layer? Explain ACK/NAK protocol.
Ans: too long to explain here everything. In brief : TLPs when reach to DLL of receiver without any error,
they are ACKed and if not received correctly receiver of TLP sends NAK. If TLP doesn’t reach at all and lost
in transmission line, they are retransmitted from transmitter after certain time interval is elapsed.
12. What will be seq number in ACK packet and NAK packet?
Ans: Last good received TLP.
13. Have you worked on C++? What is difference between C++ and SV in respect to memory?
14. Example, explain what will be output and at what simtime?
Clock is generated for about 30 time units and posedge is @ 5, 15, 25 units
initial begin
...
...
fork
@ (posedge clk); $display("I am clk");
join
end
Ans: ‘I am clk’ will be printed at the time when fork is called(zero time if it is called at begining without any
delay) and at the end of posedge, statements after join will be executed.
15. In above code, explain simulator phases. Which statement will be executed in which region?
16. Does fork.... join block anything special on simulator phases?
17. Did you work on Gate level simulation? What kind of issues observed? Was it in control path/data path?
18. What causes X propagation in gate level simulation?
19. What kind I2C and SPI protocol you worked for? Was it Master/Slave?
20. What were SPI interface signals?
1. Tell about yourself.
2. How familiar are you in system verilog and uvm.
3. Explain the uvm testbench.
4. What is polymorphism.
Ans: Explained somewhere above
5. What is queue and mailbox and difference between them.
Ans: Queue has different methods to search and get etc, mailboxes doesn’t have such mechanism. One can
access any location of queue, contents of mailboxes are meant to be accessed in order. One can not know
the number of transactions inside mailbox, while one can easily know the size of queue. Queues are static
data types, mailbox are basically sv objects, needs to be created using =new() method.
2.round
1. What is a virtual interface and what is a physical interface . Why cant you directly connect the
interface as such by instanstiaing in the top level like write it as top.tb.if ??
Ans: Didnt get the question here...
2. From where does the sequencer gets the sequence item ?? Who generates this and how is it
given to the sequencer.
when a sequence is started on sequencer, a pointer to the sequence is contained inside sequencer and the
seq_item related to the sequence is pushed into a fifo. When driver connected to the sequencer calls the
get_next_item of seq_item_port, sequencer’s queue of transaction is checked, if queue is empty, null is
returned and driver’s execution gets halted at get_next_item. If the queue has an entry, it randomizes
seq_item and passed to driver and now the stimulus reaches to the driver.
3. What are different tlm ports how are they implemented ??
get, put , tlm_Fifo etc.
4. What tlm port is used to connect between a monitor and a scoreboad and explain how its done.
Ans: analysis port. Write method is implemented inside scoreboard and a port is declared inside scoreboard.
that port is connected to monitor via ‘connect’ method inside connect_phase function.
5. Where exactly is the interface instantiated in a given testbench.
Ans: Answering as per my understanding. Interface is instantiated inside wrapper module of DUT which
connects its signals with DUT signals and it is passed to program block(tb top). tb_top and wrapper both are
instantiated inside top module containing clock generation module.
6. Is it required to manually connect the ports or is it readily available as such in uvm.
Ans: We have to manually connect all the ports. Types of ports are fixed for the ports of driver such as
uvm_seq_pull_port which is same as type of transaction of driver. User defined ports needs to be provided
with type of trnascation.
7. How do u drive the stimulus from the tests and then hows it given to the sequencer and driver.
Ans: Testcase starts the sequence on a sequencer handle which means the sequencer can now process the
sequence everytime get_next_item is called from driver connected to that sequencer. Since driver’s
execution is halted at get_next_item till it gets a transaction, sequencer upon “start” call gives the
sequence_item generated inside the body of sequence to the driver via uvm_seq_item_pull_port.
8. What are different transfers in USB2.0 and what is the transfer size of an interrupt transfer .
9. How do you perform an interrupt transfer verification, explain with a testcase.
1. Introduce yourself.
2. What is RAL?
Ans: RAL means Register Abstraction Layer. When there is a register model to be tested, equivalent RAL
model is developed in testbench to compare the DUT’s values with expected values and also to easily
create reading and writing scenarios, RAL can be developed. It provides API at top abstraction layer which
can be called inside testcases and at layer below RAL, sequences or task/functions can be called for
reading/writing. RAL gives better understandability and faster testing capability by providing APIs.
3. What are the different scenarios you write to verify register block ?
Ans: From testing perspective registers are grouped as per its attributes(RO, RW, RW1C, ROC,RWS, ROS
etc). First test should be reset test which checks the reset values of registers after reset is applied. Second
testing should done on different groups as per their attribute. like RO registers should be checked that after
writing them through backdoor, they are not changed and they remain as ReadOnly. RW1C should be
checked by writing through backdoor and then reading it correctly and writing 1 and reading back to check if
the value is cleared or not. etc. There are many such scenarios.
4. What exactly you verify in walking 1s and walking 0s test while verifying a register?
Ans:
Walking 1s: 0 to 1 and 1 to 0 successive transitions doesn’t corrupt register
walking 0s: 1 to 0 and 0 to 1 successive transitions doesn’t corrupt register.
5. Interview gave a design and asked me to create a testbench ni UVM.
6. Various questions asked in that testbench.
7. What is virtual sequencer and virtual sequence?
Ans: Explained somewhere above
8. What is clocking block? Why it is used?
Ans: Clocking block is used to align any signal with a clock inside interface itself. So that whoever accesses
the signal through clocking block, gets the signal aligned to whatever applicable clock of clocking block.
9. Have you worked on coverage? Have you worked on assertions?
questions asked.
1. Tell me about yourself.
2. What are the methodologies you used?
3. Tell me about creating objects.(in uvm) Ans : handle = class_name :: type_id::create(“name”);
4. What is a factory?
Ans: Explained somewhere above
5. Why factory needed?
Ans: Explained somewhere above
6. Have you worked on gate sim?
7. What are the issues faced in gate sim?
8. How good are you in debug of ARM processor issues?
9. What are the protocols you know?
10. How error handling done in AXI, AHB and APB?
Ans: response signal is provided by slave which says if its an error request or Okay request.
11. How good are you in scripting?