A B C D E

1 1

2
Compal confidential 2

JBK00 LA-4093P Schematics Document

Mobile AMD S1G2 CPU with ATI
3
RX781 & SB700 core logic with M86-M 3

2009-03-25
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 1 of 58
A B C D E
 A B C D E

Compal Consumer AMD Discrete 17"

confidential
DDR2 667MHz 1.8V
72QFN
1
Thermal Sensor AMD S1G2 CPU DDR2 800MHz 1.8V DDR2-SO-DIMM X2 1

BANK 0, 1, 2, 3 P8, 9 Clock Generator

GDDRVRAM ADM1032ARMZ SLG8SP626
1GMB 638-PIN uFCPGA 638
P6 P26
Dual Channel
page 21,22,23,24 P4, 5, 6, 7

Fan conn P4
Hyper Transport Link 2.6GHz
16X16
Discrete
ATI M86M PCI-E Lane*16
P15,16,17,18,19,20

ATI RX781 Finger Print

P43
LVDS Panel
Interface P28
USB Camera
2
P10, 11, 12, 13, 14 with Digital MIC P28
2
CRT
P27
USB2.0 X12
A-Link Express II USB conn x4
P43
4X PCI-E
HDMI
P29
BT Conn
P43
PCI-E BUS*5 Azalia

ATI SB700 SATA Master-1

SATA Master-2
Touch Screen
SATA Slave P43
RTL8111C Mini-Card*2 Express Card
SATA Slave
WLAN & TV Tunner P38
10/100/1000 P30 31 32 33 34
Dock
P36 P37 P47

3
RJ45 Conn. LPC BUS Audio CKT AMP & Audio Jack 3
P36 Codec_92HD71B7 TPA6020A2 P41
P40
LED
P46
MDC V1.5 SUBAMP
SPI ENE P42
TPA3007D1 P42
JMB380 SPI ROM KB926 P45
RTC CKT. P38 P44
P30 SATA HDD Connector
P35
Int.KBD Subwoofer
P38
CardReader 1394 Conn. Touch Pad CONN.
P45
P38 P38 P46
Docking CKT. CIR SATA ODD Connector
P47 P35
P42

SATA 2nd HDD Connector

P35
DC/DC Interface CKT.
P48
4 4
e-SATA Connector
P43

ACCELEROMETER.
LIS302DLTR P39 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 2 of 58
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 A B C D E

Voltage Rails

Symbol Note :
@ : means just reserve , no build
+5VS : means Digital Ground 45@ : means need be mounted when 45 level assy or rework stage.
1
+3VS 1

power +2.5VS RX781R1@ : means just reserve for R1 FRU BOM

plane +1.8VS : means Analog Ground SBR1 @ : means just reserve for R1 FRU BOM
+1.5VS
+1.1VS M86R1@ : means just reserve for R1 FRU BOM
+B +1.8V @ : means just reserve , no build
+3VL
+5VALW
+3VALW +0.9V
+VGA_CORE DEBUG@ : means just reserve for debug.
+1.2VALW +1.2V_HT
+5VL +3V_LAN
+CPU_CORE_NB Layout Notes
State L
+CPU_CORE_0
U5
+CPU_CORE_1
M86M
M86M R1
M86R3@

U3
S0
O O O O
RX781
S1
2
O O O O RX781 R1
2
RX781R3@

S3
O O O X U15

S5 S4/AC SB700
O O X X
SB700 R1
S5 S4/ Battery only SBR3@
O X X X
ZZZ
S5 S4/AC & Battery
don't exist X X X X
PCB
O MEANS ON X MEANS OFF PCB LA-4093P REV1.0 M/B

I2C / SMBUS ADDRESSING

SMBUS Control Table
THERMAL
DEVICE HEX ADDRESS SOURCE INVERTER BATT
SERIAL
EEPROM
SENSOR
CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
ADM1032 I / II Slot 2
3
DDR SO-DIMM 0 A0 10100000 3
SMB_EC_CK1
DDR SO-DIMM 1 A4 10100100
SMB_EC_DA1
KB926 X V V X X X X X X X
CLOCK GENERATOR (EXT.) D2 11010010
SMB_EC_CK2
ACCELEROMETER 3A 00111010
SMB_EC_DA2
KB926 X X X V X X X X X X
I2C_CLK
I2C_DATA
RS780M
X X X X X X X V X X
DDC_CLK0
DDC_DATA0
RS780M X X X X X X X X V X
DDC_CLK1
EC SM Bus1 address EC SM Bus2 address RS780M X X X X X X X X X X
DDC_DATA1
Device HEX Address Device HEX Address SCL0

Smart Battery 16H 0001 011X b

ADI1032-2 CPU 9AH 1001 101X b SDA0
SB700 X X X X V V X X X V
ADI1032-1 VGA 98H 1001 100X b SCL1
24C16
CPU SIC interface
A0H
98H
1010 000X b
1001 100X b
SDA1
SB700 X X X X X X V X X X
SCL2
SDA2
SB700 X X X X X X X X X X
4 4
SCL3
SDA3
SB700 X X X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 3 of 58
A B C D E
 A B C D E

1 1

+1.2V_HT
VLDT CAP.
250 mil

1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10

Near CPU Socket

+1.2V_HT
JP1A

2 2
VLDT=500mA D1 VLDT_A0 HT LINK VLDT_B0 AE2 +VLDT_B 1 2
D2 AE3 C7 4.7U_0805_10V4Z
VLDT_A1 VLDT_B1
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5

H_CADIP0 E3 AD1 H_CADOP0

H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15
H_CADIN15
N5
P5
L0_CADIN_L14
L0_CADIN_H15
L0_CADOUT_L14
L0_CADOUT_H15 T4
T3
H_CADOP15
H_CADON15
PWM Fan Control circuit +5VS
L0_CADIN_L15 L0_CADOUT_L15

10 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 10

10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
J5 Y4 JP2
10 H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 10

1
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10 1 1 1 1
C8 C9 2
D1 @ 0.1U_0402_16V4Z 2
10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10
P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3
10 H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 10 2 2 GND
10 H_CTLIP1 P3 T5 H_CTLOP1 10 4

2
L0_CTLIN_H1 L0_CTLOUT_H1 GND
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10
ACES_88231-02001
+VCC_FAN
6090022100G_B CONN@

1
2
5
6

1
CONN@ D Q1 @ D2
G
3 RLZ5.1B_LL34
45 FAN_PWM S SI3456BDV-T1-E3_TSOP6

2
4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 4 of 58
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 A B C D E

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH JP1C
9 DDR_B_D[63..0]
MEM:DATA
DDR_A_D[63..0] 8
DDR_A_CLK0 DDR_B_D0 C11 G12 DDR_A_D0
1 +1.8V DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDR_B_D2 A14 H14 DDR_A_D2
C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
B14 MB_DATA3 MA_DATA3 G14
2

1.5P_0402_50V9C DDR_B_D4 G11 H11 DDR_A_D4

R1 DDR_A_CLK#0 2 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDR_B_D6 D12 C13 DDR_A_D6
DDR_A_CLK1 DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7
A13 MB_DATA7 MA_DATA7 E13
1 DDR_B_D8 A15 H15 DDR_A_D8
1

+MCH_REF DDR_B_D9 MB_DATA8 MA_DATA8 DDR_A_D9

A16 MB_DATA9 MA_DATA9 E15
1000P_0402_25V8J
0.1U_0402_16V4Z

C11 DDR_B_D10 A19 E17 DDR_A_D10

MB_DATA10 MA_DATA10
2

1 1 1.5P_0402_50V9C DDR_B_D11 A20 H17 DDR_A_D11

2 MB_DATA11 MA_DATA11
C12

C13

R2 DDR_A_CLK#1 DDR_B_D12 C14 E14 DDR_A_D12

1K_0402_1% DDR_B_D13 MB_DATA12 MA_DATA12 DDR_A_D13
D14 MB_DATA13 MA_DATA13 F14
DDR_B_D14 C18 C17 DDR_A_D14
2 2 DDR_B_CLK0 DDR_B_D15 MB_DATA14 MA_DATA14 DDR_A_D15
D18 G17
1

DDR_B_D16 MB_DATA15 MA_DATA15 DDR_A_D16

1 D20 MB_DATA16 MA_DATA16 G18
DDR_B_D17 A21 C19 DDR_A_D17
C14 DDR_B_D18 MB_DATA17 MA_DATA17 DDR_A_D18
D24 MB_DATA18 MA_DATA18 D22
1.5P_0402_50V9C DDR_B_D19 C25 E20 DDR_A_D19
DDR_B_CLK#0 2 DDR_B_D20 MB_DATA19 MA_DATA19 DDR_A_D20
B20 MB_DATA20 MA_DATA20 E18
DDR_B_D21 C20 F18 DDR_A_D21
DDR_B_CLK1 DDR_B_D22 MB_DATA21 MA_DATA21 DDR_A_D22
B24 MB_DATA22 MA_DATA22 B22
1 DDR_B_D23 C24 C23 DDR_A_D23
DDR_B_D24 MB_DATA23 MA_DATA23 DDR_A_D24
E23 MB_DATA24 MA_DATA24 F20
C15 DDR_B_D25 E24 F22 DDR_A_D25
1.5P_0402_50V9C DDR_B_D26 MB_DATA25 MA_DATA25 DDR_A_D26
G25 MB_DATA26 MA_DATA26 H24
DDR_B_CLK#1 2 DDR_B_D27 DDR_A_D27
G26 MB_DATA27 MA_DATA27 J19
DDR_B_D28 C26 E21 DDR_A_D28
DDR_B_D29 MB_DATA28 MA_DATA28 DDR_A_D29
D26 MB_DATA29 MA_DATA29 E22
DDR_B_D30 G23 H20 DDR_A_D30
+0.9V +0.9V DDR_B_D31 MB_DATA30 MA_DATA30 DDR_A_D31
G24 MB_DATA31 MA_DATA31 H22
JP1B DDR_B_D32 AA24 Y24 DDR_A_D32
2 DDR_B_D33 MB_DATA32 MA_DATA32 DDR_A_D33 2
AA23 MB_DATA33 MA_DATA33 AB24
D10 W10 DDR_B_D34 AD24 AB22 DDR_A_D34
VTT1 MEM:CMD/CTRL/CLK VTT5 DDR_B_D35 MB_DATA34 MA_DATA34 DDR_A_D35
Place them close to CPU within 1" C10 VTT2 VTT6 AC10 AE24 MB_DATA35 MA_DATA35 AA21
B10 AB10 DDR_B_D36 AA26 W22 DDR_A_D36
VTT3 VTT7 DDR_B_D37 MB_DATA36 MA_DATA36 DDR_A_D37
AD10 VTT4 VTT8 AA10 AA25 MB_DATA37 MA_DATA37 W21
R4 39.2_0402_1% A10 DDR_B_D38 AD26 Y22 DDR_A_D38
VTT9 DDR_B_D39 MB_DATA38 MA_DATA38 DDR_A_D39
1 2 AF10 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
+1.8V 1 2 AE10 Y10 VTT_SENSE DDR_B_D40 AC22 Y20 DDR_A_D40
MEMZN VTT_SENSE PAD T1 MB_DATA40 MA_DATA40
R3 39.2_0402_1% DDR_B_D41 AD22 AA20 DDR_A_D41
+MCH_REF DDR_B_D42 MB_DATA41 MA_DATA41 DDR_A_D42
T2 PAD H16 RSVD_M1 MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18
DDR_B_D43 AF20 AB18 DDR_A_D43
DDR_A_ODT0 DDR_B_D44 MB_DATA43 MA_DATA43 DDR_A_D44
8 DDR_A_ODT0 T19 MA0_ODT0 RSVD_M2 B18 PAD T3 AF24 MB_DATA44 MA_DATA44 AB21
DDR_A_ODT1 V22 DDR_B_D45 AF23 AD21 DDR_A_D45
8 DDR_A_ODT1 MA0_ODT1 MB_DATA45 MA_DATA45
U21 W26 DDR_B_ODT0 DDR_B_D46 AC20 AD19 DDR_A_D46
MA1_ODT0 MB0_ODT0 DDR_B_ODT0 9 MB_DATA46 MA_DATA46
V19 W23 DDR_B_ODT1 DDR_B_D47 AD20 Y18 DDR_A_D47
MA1_ODT1 MB0_ODT1 DDR_B_ODT1 9 MB_DATA47 MA_DATA47
Y26 DDR_B_D48 AD18 AD17 DDR_A_D48
DDR_CS0_DIMMA# MB1_ODT0 DDR_B_D49 MB_DATA48 MA_DATA48 DDR_A_D49
8 DDR_CS0_DIMMA# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D50 AC14 W14 DDR_A_D50
8 DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# 9 MB_DATA50 MA_DATA50
U20 W25 DDR_CS1_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
MA1_CS_L0 MB0_CS_L1 DDR_CS1_DIMMB# 9 MB_DATA51 MA_DATA51
V20 U22 DDR_B_D52 AF19 Y17 DDR_A_D52
MA1_CS_L1 MB1_CS_L0 DDR_B_D53 MB_DATA52 MA_DATA52 DDR_A_D53
AC18 MB_DATA53 MA_DATA53 AB17
DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB DDR_B_D54 AF16 AB15 DDR_A_D54
8 DDR_CKE0_DIMMA MA_CKE0 MB_CKE0 DDR_CKE0_DIMMB 9 MB_DATA54 MA_DATA54
DDR_CKE1_DIMMA J20 H26 DDR_CKE1_DIMMB DDR_B_D55 AF15 AD15 DDR_A_D55
8 DDR_CKE1_DIMMA MA_CKE1 MB_CKE1 DDR_CKE1_DIMMB 9 MB_DATA55 MA_DATA55
DDR_B_D56 AF13 AB13 DDR_A_D56
DDR_B_D57 MB_DATA56 MA_DATA56 DDR_A_D57
N19 MA_CLK_H0 MB_CLK_H0 P22 AC12 MB_DATA57 MA_DATA57 AD13
N20 R22 DDR_B_D58 AB11 Y12 DDR_A_D58
DDR_A_CLK0 MA_CLK_L0 MB_CLK_L0 DDR_B_CLK0 DDR_B_D59 MB_DATA58 MA_DATA58 DDR_A_D59
8 DDR_A_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDR_B_CLK0 9 Y11 MB_DATA59 MA_DATA59 W11
DDR_A_CLK#0 F16 A18 DDR_B_CLK#0 DDR_B_D60 AE14 AB14 DDR_A_D60
8 DDR_A_CLK#0 MA_CLK_L1 MB_CLK_L1 DDR_B_CLK#0 9 MB_DATA60 MA_DATA60
DDR_A_CLK1 Y16 AF18 DDR_B_CLK1 DDR_B_D61 AF14 AA14 DDR_A_D61
8 DDR_A_CLK1 MA_CLK_H2 MB_CLK_H2 DDR_B_CLK1 9 MB_DATA61 MA_DATA61
DDR_A_CLK#1 AA16 AF17 DDR_B_CLK#1 DDR_B_D62 AF11 AB12 DDR_A_D62
8 DDR_A_CLK#1 MA_CLK_L2 MB_CLK_L2 DDR_B_CLK#1 9 MB_DATA62 MA_DATA62
P19 R26 DDR_B_D63 AD11 AA12 DDR_A_D63
MA_CLK_H3 MB_CLK_H3 MB_DATA63 MA_DATA63
P20 MA_CLK_L3 MB_CLK_L3 R25 9 DDR_B_DM[7..0] DDR_A_DM[7..0] 8
3 DDR_B_DM0 DDR_A_DM0 3
8 DDR_A_MA[15..0] DDR_B_MA[15..0] 9 A12 MB_DM0 MA_DM0 E12
DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM1 B16 C15 DDR_A_DM1
DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM2 MB_DM1 MA_DM1 DDR_A_DM2
M20 MA_ADD1 MB_ADD1 N24 A22 MB_DM2 MA_DM2 E19
DDR_A_MA2 N22 P26 DDR_B_MA2 DDR_B_DM3 E25 F24 DDR_A_DM3
DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM4 MB_DM3 MA_DM3 DDR_A_DM4
M19 MA_ADD3 MB_ADD3 N23 AB26 MB_DM4 MA_DM4 AC24
DDR_A_MA4 M22 N26 DDR_B_MA4 DDR_B_DM5 AE22 Y19 DDR_A_DM5
DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM6 MB_DM5 MA_DM5 DDR_A_DM6
L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
DDR_A_MA6 M24 N25 DDR_B_MA6 DDR_B_DM7 AD12 Y13 DDR_A_DM7
DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 MB_DM7 MA_DM7
L21 MA_ADD7 MB_ADD7 L24
DDR_A_MA8 L19 M26 DDR_B_MA8 DDR_B_DQS0 C12 G13 DDR_A_DQS0
MA_ADD8 MB_ADD8 9 DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 8
DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
MA_ADD9 MB_ADD9 9 DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 8
DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS1 D16 G16 DDR_A_DQS1
MA_ADD10 MB_ADD10 9 DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 8
DDR_A_MA11 L22 L26 DDR_B_MA11 DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
MA_ADD11 MB_ADD11 9 DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 8
DDR_A_MA12 K20 L25 DDR_B_MA12 DDR_B_DQS2 A24 C22 DDR_A_DQS2
MA_ADD12 MB_ADD12 9 DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 8
DDR_A_MA13 V24 W24 DDR_B_MA13 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
MA_ADD13 MB_ADD13 9 DDR_B_DQS#2 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS#2 8
DDR_A_MA14 K24 J23 DDR_B_MA14 DDR_B_DQS3 F26 G22 DDR_A_DQS3
MA_ADD14 MB_ADD14 9 DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 8
DDR_A_MA15 K19 J24 DDR_B_MA15 DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
MA_ADD15 MB_ADD15 9 DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 8
DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
9 DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 8
DDR_A_BS#0 R20 R24 DDR_B_BS#0 DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
8 DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 9 9 DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 8
DDR_A_BS#1 R23 U26 DDR_B_BS#1 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
8 DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 9 9 DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 8
DDR_A_BS#2 J21 J26 DDR_B_BS#2 DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
8 DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 9 9 DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 8
DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
9 DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 8
DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
8 DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# 9 9 DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 8
DDR_A_CAS# T22 U24 DDR_B_CAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
8 DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# 9 9 DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 8
DDR_A_WE# T24 U23 DDR_B_WE# DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
8 DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# 9 9 DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 8

6090022100G_B
CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 5 of 58
A B C D E
 A B C D E

+2.5VDDA
VDDA=300mA
L1
+2.5VS 1 2 3300P_0402_50V7K
1 FBM_L11_201209_300L_0805
1 1 1 +1.8V 1 2
C16 + R10 10K_0402_5%
@ 100U_D2_10VM 4.7U_0805_10V4Z C17 C18 C19 1 2
0.22U_0603_16V4Z R5 300_0402_5%
2 2 2 2

2
B
1 R6 2 ENTRIP2 50
SI2: remove 100uF Q3 @ 0_0402_5%
JP1D

E
1 CPU_THERMTRIP#_R R7 1
3 1 1 2 H_THERMTRIP# 32,45

C
0_0402_5%
F8 M11 MMBT3904_NL_SOT23-3
VDDA1 KEY1
F9 VDDA2 KEY2 W18

1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC

26 CLK_CPU_BCLK CLKIN_H SVC CPU_SVC 56
C20 CPU_CLKIN_SC_N A8 A4 CPU_SVD
CLKIN_L SVD CPU_SVD 56

1
LDT_RST# B7
R8 H_PWRGD RESET_L
A7 PWROK +1.8V 1 2
169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R R9 300_0402_5%
CPU_LDT_REQ# LDTSTOP_L THERMTRIP_L CPU_PROCHOT#_1.8 R11
C6 AC7

2
LDTREQ_L PROCHOT_L CPU_PROCHOT#_1.8
26 CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 2 1 +1.8V 1 2 H_PROCHOT# 30
C21 3900P_0402_50V7K CPU_SIC AF4 R48 300_0402_5% @ 0_0402_5%
CPU_SID SIC
Address:100_1100 AF5 SID
+1.8VS AE6 W7 THERMDC_CPU PV:change PROCHOT# & delete Q2
ALERT_L THERMDC THERMDA_CPU
Place close to CPU wihtin 1.5" THERMDA W8
R13 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
2

R14 1 2 44.2_0402_1% CPU_HTREF1 P6

R15
+1.2V_HT HT_REF1 +1.8V sense no support
300_0402_5% 56 CPU_VDD0_FB_H CPU_VDD0_FB_H F6 W9 +CPU_CORE_NB
VDD0_FB_H VDDIO_FB_H PAD T22
56 CPU_VDD0_FB_L CPU_VDD0_FB_L E6 Y9
+CPU_CORE_0 VDD0_FB_L VDDIO_FB_L PAD T21
R484 10_0402_5%
1

LDT_RST# R487 10_0402_5% 56 CPU_VDD1_FB_H CPU_VDD1_FB_H Y6 H6 VDD_NB_FB_H VDD_NB_FB_H 1 2

30 LDT_RST# VDD1_FB_H VDDNB_FB_H VDD_NB_FB_H 56
1 2CPU_VDD0_FB_H 56 CPU_VDD1_FB_L CPU_VDD1_FB_L AB6
VDD1_FB_L VDDNB_FB_L G6 VDD_NB_FB_L
VDD_NB_FB_L 56
VDD_NB_FB_L 1 2
1 1 2CPU_VDD0_FB_L R485 10_0402_5%
C22 R486 10_0402_5% CPU_DBRDY G10
0.01U_0402_25V4Z CPU_TMS DBRDY CPU_DBREQ#
AA9 TMS DBREQ_L E10 Close to CPU
@ CPU_TCK AC9
2 CPU_TRST# TCK CPU_TDO
AD9 TRST_L TDO AE9
Close to CPU CPU_TDI AF9 TDI
2 CPU_TEST23_TSTUPD CPU_TEST28_H_PLLCHRZ_P 2
AD7 TEST23 TEST28_H J7 PAD T5 route as differential
+CPU_CORE_1 H8 CPU_TEST28_L_PLLCHRZ_N as short as possible
+1.8VS TEST28_L PAD T6
R489 10_0402_5% CPU_TEST19_PLLTEST0 H10 testpoint under package
TEST18
1 2CPU_VDD1_FB_H CPU_TEST18_PLLTEST1 G9 TEST19 TEST17 D7 CPU_TEST17_BP3
PAD T7
1 2CPU_VDD1_FB_L @ 30.1_0402_1%
TEST16 E7 CPU_TEST16_BP2
PAD T8
2

R493 1 2 CPU_TEST25_H_BYPASSCLK_H E9 F7 CPU_TEST15_BP1 +1.8V

TEST25_H TEST15 PAD T10
R21 R488 10_0402_5% 1 2 CPU_TEST25_L_BYPASSCLK_L E8 C7 CPU_TEST14_BP0 0718 AMD --> 1K ohm
TEST25_L TEST14 PAD T12
300_0402_5% +1.8V R492
@ 30.1_0402_1% CPU_TEST21_SCANEN AB8 C3 CPU_SVC 1 2
CPU_TEST20_SCANCLK2 TEST21 TEST7 CPU_SVD R22 1K_0402_5%
MV:follow ANT 0E CRB AF7 K8 1 2
1

H_PWRGD CPU_TEST24_SCANCLK1 TEST20 TEST10 R23 1K_0402_5%

30,56 H_PWRGD change R493 to GND AE7 TEST24
CPU_TEST22_SCANSHIFTEN AE8 C4
& R492 to +1.8V CPU_TEST12_SCANSHIFTENB TEST22 TEST8 CPU_TEST27_SINGLECHAIN
1 AC8 TEST12 1 2
CPU_TEST27_SINGLECHAIN AF8 R24 @ 300_0402_5%
C23 TEST27 CPU_TEST29_H_FBCLKOUT_P
TEST29_H C9 PAD T13
@ 0.1U_0402_16V4Z +1.8VS 1 R25 2 0_0402_5% C2 C8 CPU_TEST29_L_FBCLKOUT_N CPU_TEST21_SCANEN R26 1 2 300_0402_5%
2 TEST9 TEST29_L PAD T14
AA6 CPU_TEST20_SCANCLK2 R27 2 1@ 300_0402_5%
TEST6 CPU_TEST24_SCANCLK1 R28 2 1 300_0402_5%
2

A3 H18 CPU_TEST22_SCANSHIFTEN R29 2 1@ 300_0402_5%

R30 RSVD1 RSVD10 CPU_TEST12_SCANSHIFTENB R31
A5 RSVD2 RSVD9 H19 MV:unmount strap pin 2 1@ 300_0402_5%
300_0402_5% B3 AA7 CPU_TEST15_BP1 R32 2 1@ 300_0402_5%
+1.8VS RSVD3 RSVD8 CPU_TEST14_BP0 R33
B5 RSVD4 RSVD7 D5 2 1@ 300_0402_5%
C1 C5 CPU_TEST19_PLLTEST0 R34 2 1@ 300_0402_5%
1

CPU_LDT_REQ# RSVD5 RSVD6 CPU_TEST18_PLLTEST1 R35

CPU_LDT_REQ# 11,30 2 1@ 300_0402_5%
2

CPU_TEST23_TSTUPD R49 2 1@ 300_0402_5%

R36 1 6090022100G_B
300_0402_5% C24 PV:AMD 4.1 recommend
0.01U_0402_25V4Z
@ CONN@
1

LDT_STOP# 2
11,30 LDT_STOP#
1
3 C25 3
0.01U_0402_25V4Z
@
2
1 2

@ C939 0.1U_0402_16V4Z
R175
R814
+3VS 2 1 2 1
2.09V for Gate
@ 20K_0402_5% @ 34.8K_0402_1%~N
+1.8V
R18

+1.8V 2 1
HDT Connector
2
G

@ 220_0402_5% R37

@ 220_0402_5% R38

@ 220_0402_5% R39

@ 220_0402_5% R40

300_0402_5% R41
2.2K_0402_5%

1
CPU_SID 3 1 SMB_EC_DA1 44,45,46,54
S

PV:change to 2.2K Q127 @ FDV301N_NL_SOT23-3 FDV301N, the Vgs is: JP3

min = 0.65V 1 2
R19

2
Typ = 0.85V 3 4
EC is PU to 5VALW 5 6
+1.8V 2 1 Max = 1.5V CPU_DBREQ#
7 8
2

+3VS
G

2.2K_0402_5% CPU_DBRDY
CPU_TCK
9 10
CPU_SIC CPU_TMS 11 12 +3VS
3 1 SMB_EC_CK1 44,45,46,54 13 14
S

CPU_TDI
15 16
0.1U_0402_16V4Z

1 CPU_TRST#
17 18

5
Q129 @ FDV301N_NL_SOT23-3 CPU_TDO U1
C26 19 20 LDT_RST#
2

P
21 22 HDT_RST# B
23 24 4 Y
2
26 A 1 SB_PWRGD 32,45,56 4

G
4 U2 NOTE: HDT TERMINATION IS REQUIRED
1 8 SMB_EC_CK2 @ NC7SZ08P5X_NL_SC70-5
SMB_EC_CK2 25,45 FOR REV. Ax SILICON ONLY.

3
VDD SCLK CONN@ SAMTEC_ASP-68200-07
THERMDA_CPU 2 7 SMB_EC_DA2
D+ SDATA SMB_EC_DA2 25,45
C27
1 2 THERMDC_CPU 3 6
2200P_0402_50V7K D- ALERT#
2200p change to 4 5
1000p for ADT7421
THERM# GND Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
ADM1032ARMZ-2REEL_MSOP8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
Address:100_1101 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 6 of 58
A B C D E
 A B C D E

JP1F

VDD(+CPU_CORE) decoupling. +CPU_CORE_0 JP1E +CPU_CORE_1

AA4
AA11
VSS1
VSS2
VSS66
VSS67
J6
J8
AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE_0 +CPU_CORE_1 J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 VDD0_4 VDD1_4 R7 AB2 VSS7 VSS72 J18
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 VDD0_6 VDD1_6 R11 AB9 VSS9 VSS74 K7
1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 VDD0_8 VDD1_8 T6 AB25 VSS11 VSS76 K11
+ C30 + C28 + C31 + C29 K12 T8 AC11 K13
1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M VDD0_9 VDD1_9 VSS12 VSS77 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2
L7 VDD0_12 VDD1_12 T14 AC17 VSS15 VSS80 L6
L9 VDD0_13 VDD1_13 U7 AC19 VSS16 VSS81 L8
L11 U9 AC21 L10
Near CPU Socket L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15 U11 AD6
VSS17
VSS18
VSS82
VSS83 L12
L15 VDD0_16 VDD1_16 U13 AD8 VSS19 VSS84 L14
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
M8 VDD0_19 VDD1_19 V8 AE13 VSS22 VSS87 M7
+CPU_CORE_0 M10 V10 AE15 M9
+CPU_CORE_1 VDD0_20 VDD1_20 VSS23 VSS88
N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 1 VDD1_24 Y2 AE23 VSS27 VSS92 N8
C32 C33 C34 C35 1 1 1 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C36 C37 C38 C39 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.8V V16 VDDNB_5 VDDIO26 V25 B11 VSS32 VSS97 P7
VDDIO25 V23 B13 VSS33 VSS98 P9
+CPU_CORE_0 H25 V21 B15 P11
+CPU_CORE_1 VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C40 C41 C42 C43 C44 C45 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 VDDIO7 VDDIO18 T18 D6 VSS40 VSS105 T7
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2
M21 VDDIO9 VDDIO16 P25 D9 VSS42 VSS107 T11
M23 P23 D11 T13
Under CPU Socket M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D13
VSS43
VSS44
VSS108
VSS109 T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
6090022100G_B D21 U8
Athlon 64 S1 VSS48 VSS113
D23 U10
VDDIO decoupling. Processor Socket
CONN@
D25
E4
VSS49
VSS50
VSS51
VSS114
VSS115
VSS116
U12
U14
F2 U16

+1.8V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
+CPU_CORE_NB F19 V11
VSS57 VSS122
F21 VSS58 VSS123 V13
1 1 1 1 1 1 F23 VSS59 VSS124 V15
C46 C47 C48 C49 C50 C51 1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C52 C53 C54 VSS60 VSS125
H7 VSS61 VSS126 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M @ 22U_0805_6.3V6M H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 VSS63 VSS128 Y23
2 2 2
H23 VSS64 VSS129 N6
J4 VSS65
SI2: reserve 22u
6090022100G_B
Under CPU Socket Athlon 64 S1
Processor Socket
CONN@

Between CPU Socket and DIMM

+1.8V +0.9V
3 3
Near Power Supply
1
C55
1
C56
1
C57
1
C58
VTT decoupling. 1
C: Change to NBO CAP
+ C59
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 220U_Y_4VM
2 2 2 2 2

180PF Qt'y follow the distance between

+1.8V +1.8V CPU socket and DIMM0. <2.5inch> +0.9V

1 1 1 1 1 1
C60 C61 C62 C63 C64 C65 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C66 C67 C68 C69 C70 C71 C72 C73
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 2 2 2 2 2 2 2 2
to follow AMD Layout
+1.8V
review recommand for
EMI Near CPU Socket Right side.
+0.9V
1
1 1 1 1 C: Change to NBO CAP
+ C78
C74 C75 C76 C77 220U_Y_4VM 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C79 C80 C81 C82 C83 C84 C85 C86
2 2 2 2 2 @ 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 7 of 58
A B C D E
 A B C D E

+V_DDR_MCH_REF

+1.8V JP4 +1.8V

1 VREF VSS 2
3 4 DDR_A_D4 DDR_A_D[0..63]
DDR_A_D0 VSS DQ4 DDR_A_D5 DDR_A_D[0..63] 5 +0.9V +1.8V
5 DQ0 DQ5 6
DDR_A_D1 7 8 DDR_A_DM[0..7] RP1
DQ1 VSS DDR_A_DM[0..7] 5
9 10 DDR_A_DM0 DDR_A_MA6 1 8 1 2
DDR_A_DQS#0 VSS DM0 DDR_A_DQS[0..7] DDR_A_MA7 C87 0.1U_0402_16V4Z
11 DQS0# VSS 12 DDR_A_DQS[0..7] 5 2 7
DDR_A_DQS0 13 14 DDR_A_D6 DDR_A_MA11 3 6 1 2
DQS0 DQ6 DDR_A_D7 DDR_A_MA[0..15] DDR_A_MA14 C88 0.1U_0402_16V4Z
15 VSS DQ7 16 DDR_A_MA[0..15] 5 4 5
1 DDR_A_D2 1
17 DQ2 VSS 18
DDR_A_D3 19 20 DDR_A_D12 DDR_A_DQS#[0..7] 47_0804_8P4R_5%
DQ3 DQ12 DDR_A_D13 DDR_A_DQS#[0..7] 5 RP2
21 VSS DQ13 22
DDR_A_D8 23 24 DDR_CKE0_DIMMA 8 1 1 2
DDR_A_D9 DQ8 VSS DDR_A_DM1 DDR_A_BS#2 C90 0.1U_0402_16V4Z
25 DQ9 DM1 26 7 2
27 28 DDR_A_MA15 6 3 1 2
DDR_A_DQS#1 VSS VSS DDR_CKE1_DIMMA C89 0.1U_0402_16V4Z
29 DQS1# CK0 30 DDR_A_CLK0 5 5 4
DDR_A_DQS1 31 32
DQS1 CK0# DDR_A_CLK#0 5
33 34 47_0804_8P4R_5%
DDR_A_D10 VSS VSS DDR_A_D14 RP3
35 DQ10 DQ14 36
DDR_A_D11 37 38 DDR_A_D15 +1.8V DDR_A_MA0 1 8 1 2
DQ11 DQ15 DDR_A_BS#1 C91 0.1U_0402_16V4Z
39 VSS VSS 40 2 7
DDR_A_MA2 3 6 1 2

2
DDR_A_MA4 4 5 C92 0.1U_0402_16V4Z
41 42 R43
DDR_A_D16 VSS VSS DDR_A_D20 1K_0402_1% 47_0804_8P4R_5%
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21 RP4
DQ17 DQ21 DDR_A_MA5
47 48 8 1 1 2

1
DDR_A_DQS#2 VSS VSS +V_DDR_MCH_REF DDR_A_MA8 C93 0.1U_0402_16V4Z
49 DQS2# NC 50 +V_DDR_MCH_REF 9 7 2

0.1U_0402_16V4Z
DDR_A_DQS2 51 52 DDR_A_DM2 DDR_A_MA9 6 3 1 2
DQS2 DM2

1000P_0402_25V8J
53 54 1 1 DDR_A_MA12 5 4 C94 0.1U_0402_16V4Z
VSS VSS

2
C96
DDR_A_D18 55 56 DDR_A_D22
DQ18 DQ22

C95
DDR_A_D19 57 58 DDR_A_D23 R44 47_0804_8P4R_5%
DQ19 DQ23 1K_0402_1% RP5
59 VSS VSS 60
DDR_A_D24 DDR_A_D28 2 2 DDR_A_BS#0
61 DQ24 DQ28 62 8 1 1 2
DDR_A_D25 63 64 DDR_A_D29 DDR_A_MA1 7 2 C98 0.1U_0402_16V4Z

1
DQ25 DQ29 DDR_A_MA10
65 VSS VSS 66 6 3 1 2
DDR_A_DM3 67 68 DDR_A_DQS#3 DDR_A_MA3 5 4 C97 0.1U_0402_16V4Z
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 72 47_0804_8P4R_5%
DDR_A_D26 VSS VSS DDR_A_D30 RP6
73 DQ26 DQ30 74
DDR_A_D27 75 76 DDR_A_D31 DDR_CS1_DIMMA# 8 1 1 2
2 DQ27 DQ31 DDR_A_ODT1 C100 0.1U_0402_16V4Z 2
77 VSS VSS 78 7 2
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA DDR_A_WE# 6 3 1 2
5 DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA 5
81 82 DDR_A_CAS# 5 4 C99 0.1U_0402_16V4Z
VDD VDD DDR_A_MA15
83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14 47_0804_8P4R_5%
5 DDR_A_BS#2 BA2 NC/A14
87 88 RP7
DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_ODT0
89 A12 A11 90 1 8 1 2
DDR_A_MA9 91 92 DDR_A_MA7 DDR_A_MA13 2 7 C102 0.1U_0402_16V4Z
DDR_A_MA8 A9 A7 DDR_A_MA6 DDR_A_RAS#
93 A8 A6 94 3 6 1 2
95 96 DDR_CS0_DIMMA# 4 5 C101 0.1U_0402_16V4Z
DDR_A_MA5 VDD VDD DDR_A_MA4
97 A5 A4 98
DDR_A_MA3 99 100 DDR_A_MA2 47_0804_8P4R_5%
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 5
DDR_A_BS#0 107 108 DDR_A_RAS#
5 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 5
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
5 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 5
111 VDD VDD 112
DDR_A_CAS# 113 114 DDR_A_ODT0
5 DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 5
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
5 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
DDR_A_ODT1 119 120
5 DDR_A_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138
DQ35 VSS DDR_A_D44
139 VSS DQ44 140
3 DDR_A_D40 DDR_A_D45 3
141 DQ40 DQ45 142
DDR_A_D41 143 144
DQ41 VSS DDR_A_DQS#5
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_A_CLK1 5
165 VSS CK1# 166 DDR_A_CLK#1 5
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60
DDR_A_D57 DQ56 DQ60 DDR_A_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
193 194 DDR_A_D63
VSS DQ63
9,26,32,39 SMB_CK_DAT0 195 SDA VSS 196
9,26,32,39 SMB_CK_CLK0 197 SCL SAO 198
+3VS 199 VDDSPD SA1 200
1
4 C103 P-TWO_A5692B-A0G16-P 4
0.1U_0402_16V4Z CONN@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 8 of 58
A B C D E
 A B C D E

+1.8V
JP5 +1.8V +0.9V +1.8V
1 2 DDR_B_D[0..63] RP8
8 +V_DDR_MCH_REF VREF VSS DDR_B_D[0..63] 5
3 4 DDR_B_D4 DDR_B_BS#1 1 8 2 1
DDR_B_D0 VSS DQ4 DDR_B_D5 DDR_B_DM[0..7] DDR_B_MA2 C105 0.1U_0402_16V4Z
5 DQ0 DQ5 6 DDR_B_DM[0..7] 5 2 7
DDR_B_D1 7 8 DDR_B_MA0 3 6 1 2
DQ1 VSS

1000P_0402_25V8J
1 9 10 DDR_B_DM0 DDR_B_DQS[0..7] DDR_B_MA6 4 5 C106 0.1U_0402_16V4Z
DDR_B_DQS#0 VSS DM0 DDR_B_DQS[0..7] 5
11 DQS0# VSS 12

C104
DDR_B_DQS0 13 14 DDR_B_D6 DDR_B_MA[0..15] 47_0804_8P4R_5%
1 DQS0 DQ6 DDR_B_MA[0..15] 5 1
15 16 DDR_B_D7
2 DDR_B_D2 VSS DQ7 DDR_B_DQS#[0..7] RP9
17 DQ2 VSS 18 DDR_B_DQS#[0..7] 5
DDR_B_D3 19 20 DDR_B_D12 DDR_B_MA4 1 8 2 1
DQ3 DQ12 DDR_B_D13 DDR_B_MA14 C108 0.1U_0402_16V4Z
21 VSS DQ13 22 2 7
DDR_B_D8 23 24 DDR_B_MA7 3 6 1 2
DDR_B_D9 DQ8 VSS DDR_B_DM1 DDR_B_MA11 C107 0.1U_0402_16V4Z
25 DQ9 DM1 26 4 5
27 VSS VSS 28
DDR_B_DQS#1 29 30 47_0804_8P4R_5%
DQS1# CK0 DDR_B_CLK0 5
DDR_B_DQS1 31 32
DQS1 CK0# DDR_B_CLK#0 5
33 34 RP10
DDR_B_D10 VSS VSS DDR_B_D14 DDR_B_BS#2
35 DQ10 DQ14 36 8 1 2 1
DDR_B_D11 37 38 DDR_B_D15 DDR_CKE0_DIMMB 7 2 C109 0.1U_0402_16V4Z
DQ11 DQ15 DDR_CKE1_DIMMB
39 VSS VSS 40 6 3 1 2
DDR_B_MA15 5 4 C110 0.1U_0402_16V4Z

41 42 47_0804_8P4R_5%
DDR_B_D16 VSS VSS DDR_B_D20
43 DQ16 DQ20 44
DDR_B_D17 45 46 DDR_B_D21 RP11
DQ17 DQ21 DDR_B_MA5
47 VSS VSS 48 8 1 2 1
DDR_B_DQS#2 49 50 DDR_B_MA8 7 2 C111 0.1U_0402_16V4Z
DDR_B_DQS2 DQS2# NC DDR_B_DM2 DDR_B_MA9
51 DQS2 DM2 52 6 3 1 2
53 54 DDR_B_MA12 5 4 C112 0.1U_0402_16V4Z
DDR_B_D18 VSS VSS DDR_B_D22
55 DQ18 DQ22 56
DDR_B_D19 57 58 DDR_B_D23 47_0804_8P4R_5%
DQ19 DQ23
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D28 RP12
DDR_B_D25 DQ24 DQ28 DDR_B_D29 DDR_B_BS#0
63 DQ25 DQ29 64 8 1 2 1
65 66 DDR_B_MA10 7 2 C114 0.1U_0402_16V4Z
DDR_B_DM3 VSS VSS DDR_B_DQS#3 DDR_B_MA3
67 DM3 DQS3# 68 6 3 1 2
69 70 DDR_B_DQS3 DDR_B_MA1 5 4 C113 0.1U_0402_16V4Z
NC DQS3
71 VSS VSS 72
DDR_B_D26 73 74 DDR_B_D30 47_0804_8P4R_5%
2 DDR_B_D27 DQ26 DQ30 DDR_B_D31 2
75 DQ27 DQ31 76
77 78 RP13
DDR_CKE0_DIMMB VSS VSS DDR_CKE1_DIMMB DDR_B_ODT1
5 DDR_CKE0_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMB 5 8 1 2 1
81 82 DDR_CS1_DIMMB# 7 2 C116 0.1U_0402_16V4Z
VDD VDD DDR_B_MA15 DDR_B_CAS#
83 NC NC/A15 84 6 3 1 2
DDR_B_BS#2 85 86 DDR_B_MA14 DDR_B_WE# 5 4 C115 0.1U_0402_16V4Z
5 DDR_B_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11 47_0804_8P4R_5%
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6 RP14
A8 A6 DDR_B_MA13
95 VDD VDD 96 1 8 2 1
DDR_B_MA5 97 98 DDR_B_MA4 DDR_B_ODT0 2 7 C118 0.1U_0402_16V4Z
DDR_B_MA3 A5 A4 DDR_B_MA2 DDR_B_RAS#
99 A3 A2 100 3 6 1 2
DDR_B_MA1 101 102 DDR_B_MA0 DDR_CS0_DIMMB# 4 5 C117 0.1U_0402_16V4Z
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1 47_0804_8P4R_5%
A10/AP BA1 DDR_B_BS#1 5
DDR_B_BS#0 107 108 DDR_B_RAS#
5 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 5
DDR_B_WE# 109 110 DDR_CS0_DIMMB#
5 DDR_B_WE# WE# S0# DDR_CS0_DIMMB# 5
111 VDD VDD 112
DDR_B_CAS# 113 114 DDR_B_ODT0
5 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 5
DDR_CS1_DIMMB# 115 116 DDR_B_MA13
5 DDR_CS1_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
DDR_B_ODT1 119 120
5 DDR_B_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D34 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D35 137 138
3 DQ35 VSS DDR_B_D44 3
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_B_CLK1 5
165 VSS CK1# 166 DDR_B_CLK#1 5
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D58 189 190
DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
193 194 DDR_B_D63
VSS DQ63
8,26,32,39 SMB_CK_DAT0 195 SDA VSS 196
8,26,32,39 SMB_CK_CLK0 197 SCL SAO 198 +3VS
+3VS 199 VDDSPD SA1 200
1
4 4
C119 PTI_A5652D-A0G16-P
0.1U_0402_16V4Z
2
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 9 of 58
A B C D E
 A B C D E

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
15 PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] 15
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
15 PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] 15

U3B
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C120 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C121 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_GTX_C_MRX_N1
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
PCIE_MTX_GRX_P1
2
C122 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
A3 GFX_RX1P GFX_TX1P A4 2
PCIE_GTX_C_MRX_P1 B3 B4 PCIE_MTX_GRX_N1 C123 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
1 PCIE_GTX_C_MRX_P2 GFX_RX1N GFX_TX1N PCIE_MTX_GRX_P2 C124 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 1
C2 GFX_RX2P GFX_TX2P C3 2
PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C125 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C126 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
E5 D1 2
PCIE_GTX_C_MRX_N3 F5
GFX_RX3P GFX_TX3P
D2 PCIE_MTX_GRX_N3 C127 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3 Polarity inversion
PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4 C128 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
G5 GFX_RX4P GFX_TX4P E2 2
PCIE_GTX_C_MRX_N4 G6 E1 PCIE_MTX_GRX_N4 C129 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
PCIE_GTX_C_MRX_P5 GFX_RX4N GFX_TX4N PCIE_MTX_GRX_P5 C130 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
H5 GFX_RX5P GFX_TX5P F4 2
PCIE_GTX_C_MRX_N5 H6 F3 PCIE_MTX_GRX_N5 C131 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PCIE_GTX_C_MRX_N6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 C132 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
J6 GFX_RX6P GFX_TX6P F1 2
PCIE_GTX_C_MRX_P6 J5 F2 PCIE_MTX_GRX_N6 C133 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_P7 J7
GFX_RX6N GFX_TX6N
H4 PCIE_MTX_GRX_P7 C134 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7 Polarity inversion
PCIE_GTX_C_MRX_N7 GFX_RX7P GFX_TX7P PCIE_MTX_GRX_N7 C135 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
J8 GFX_RX7N GFX_TX7N H3 2
PCIE_GTX_C_MRX_P8 L5 H1 PCIE_MTX_GRX_P8 C136 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_GTX_C_MRX_N8 GFX_RX8P GFX_TX8P PCIE_MTX_GRX_N8 C137 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
L6 GFX_RX8N GFX_TX8N H2 2
PCIE_GTX_C_MRX_P9 M8 J2 PCIE_MTX_GRX_P9 C138 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 GFX_RX9P GFX_TX9P PCIE_MTX_GRX_N9 C139 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
L8 GFX_RX9N GFX_TX9N J1 2

PCIE I/F GFX

PCIE_GTX_C_MRX_P10 P7 K4 PCIE_MTX_GRX_P10 C140 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_GTX_C_MRX_N10 GFX_RX10P GFX_TX10P PCIE_MTX_GRX_N10 C141 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
M7 GFX_RX10N GFX_TX10N K3 2
PCIE_GTX_C_MRX_P11 P5 K1 PCIE_MTX_GRX_P11 C142 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_GTX_C_MRX_N11 GFX_RX11P GFX_TX11P PCIE_MTX_GRX_N11 C143 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
M5 GFX_RX11N GFX_TX11N K2 2
PCIE_GTX_C_MRX_P12 R8 M4 PCIE_MTX_GRX_P12 C144 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_GTX_C_MRX_N12 P8
GFX_RX12P GFX_TX12P
M3 PCIE_MTX_GRX_N12 C145 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 Polarity inversion
PCIE_GTX_C_MRX_P13 GFX_RX12N GFX_TX12N PCIE_MTX_GRX_P13 C146 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
R6 GFX_RX13P GFX_TX13P M1 2
PCIE_GTX_C_MRX_N13 R5 M2 PCIE_MTX_GRX_N13 C147 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
PCIE_GTX_C_MRX_P14 GFX_RX13N GFX_TX13N PCIE_MTX_GRX_P14 C148 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
P4 GFX_RX14P GFX_TX14P N2 2
PCIE_GTX_C_MRX_N14 P3 N1 PCIE_MTX_GRX_N14 C149 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_GTX_C_MRX_P15 GFX_RX14N GFX_TX14N PCIE_MTX_GRX_P15 C150 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
T4 GFX_RX15P GFX_TX15P P1 2
PCIE_GTX_C_MRX_N15 T3 P2 PCIE_MTX_GRX_N15 C151 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
GFX_RX15N GFX_TX15N
AE3 AC1 PCIE_ITX_PRX_P0 C152 1 2 0.1U_0402_16V7K New Card
37 PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_C_PRX_P0 37
AD4 AC2 PCIE_ITX_PRX_N0 C153 1 2 0.1U_0402_16V7K
37 PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 37
AE2 AB4 PCIE_ITX_PRX_P1 C154 1 2 0.1U_0402_16V7K Cardreader
2 38 PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 38 2
AD3 AB3 PCIE_ITX_PRX_N1 C155 1 2 0.1U_0402_16V7K
38 PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_C_PRX_N1 38
AD1 AA2 PCIE_ITX_PRX_P2 C156 1 2 0.1U_0402_16V7K
37 PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 37
AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2 C157 1 2 0.1U_0402_16V7K WLAN
37 PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 37
V5 Y1 PCIE_ITX_PRX_P3 C158 1 2 0.1U_0402_16V7K
36 PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 36
W6 Y2 PCIE_ITX_PRX_N3 C159 1 2 0.1U_0402_16V7K GLAN
36 PCIE_PTX_C_IRX_N3 GPP_RX3N GPP_TX3N PCIE_ITX_C_PRX_N3 36
U5 GPP_RX4P GPP_TX4P Y4
U6 Y3 H_CADOP[0..15] H_CADIP[0..15]
GPP_RX4N GPP_TX4N 4 H_CADOP[0..15] H_CADIP[0..15] 4
U8 V1 PCIE_ITX_PRX_P5 C160 1 2 0.1U_0402_16V7K
37 PCIE_PTX_C_IRX_P5 GPP_RX5P GPP_TX5P PCIE_ITX_C_PRX_P5 37 H_CADON[0..15] H_CADIN[0..15]
U7 V2 PCIE_ITX_PRX_N5 C161 1 2 0.1U_0402_16V7K TV Tuner
37 PCIE_PTX_C_IRX_N5 GPP_RX5N GPP_TX5N PCIE_ITX_C_PRX_N5 37 4 H_CADON[0..15] H_CADIN[0..15] 4

30 SB_RX0P AA8 AD7 SB_TX0P_C C162 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P 30
30 SB_RX0N Y8 AE7 SB_TX0N_C C163 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N 30
30 SB_RX1P AA7 AE6 SB_TX1P_C C164 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P 30
30 SB_RX1N Y7 AD6 SB_TX1N_C C165 1 2 0.1U_0402_16V7K U3A
SB_RX1N SB_TX1N SB_TX1N 30
30 SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C166 1 2 0.1U_0402_16V7K H_CADOP0 Y25 D24 H_CADIP0
SB_RX2P SB_TX2P SB_TX2P 30 HT_RXCAD0P HT_TXCAD0P
30 SB_RX2N AA6 AC6 SB_TX2N_C C168 1 2 0.1U_0402_16V7K H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
SB_RX2N SB_TX2N SB_TX2N 30 HT_RXCAD0N HT_TXCAD0N
30 SB_RX3P W5 AD5 SB_TX3P_C C169 1 2 0.1U_0402_16V7K H_CADOP1 V22 E24 H_CADIP1
SB_RX3P SB_TX3P SB_TX3P 30 HT_RXCAD1P HT_TXCAD1P
30 SB_RX3N Y5 AE5 SB_TX3N_C C167 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H_CADIN1
SB_RX3N SB_TX3N SB_TX3N 30 HT_RXCAD1N HT_TXCAD1N
H_CADOP2 V25 F24 H_CADIP2
R55 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
PCE_CALRP(PCE_BCALRP) AC8 1 2 V24 HT_RXCAD2N HT_TXCAD2N F25
AB8 R56 1 2 2K_0402_1% +1.1VS H_CADOP3 U24 F23 H_CADIP3
PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
U25 HT_RXCAD3N HT_TXCAD3N F22
RS780M_FCBGA528 H_CADOP4 T25 H23 H_CADIP4
RX781R1@ H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
T24 HT_RXCAD4N HT_TXCAD4N H22

HYPER TRANSPORT CPU I/F

RS780M Display Port Support (muxed on GFX) H_CADOP5 P22 J25 H_CADIP5
H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
P23 HT_RXCAD5N HT_TXCAD5N J24
H_CADOP6 P25 K24 H_CADIP6
GFX_TX0,TX1,TX2 and TX3 H_CADON6 HT_RXCAD6P HT_TXCAD6P H_CADIN6
P24 HT_RXCAD6N HT_TXCAD6N K25
DP0 H_CADOP7 N24 K23 H_CADIP7
AUX0 and HPD0 H_CADON7 HT_RXCAD7P HT_TXCAD7P H_CADIN7
N25 HT_RXCAD7N HT_TXCAD7N K22

H_CADOP8 AC24 F21 H_CADIP8

3 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
DP1 H_CADOP9 AB25 G20 H_CADIP9
AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

4 H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 4

4 H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 4
4 H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 4
4 H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 4
H_CTLOP0 M22 M24 H_CTLIP0
4 H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 4
H_CTLON0 M23 M25 H_CTLIN0
4 H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 4
H_CTLOP1 R21 P19 H_CTLIP1
4 H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 4
H_CTLON1 R20 R18 H_CTLIN1
4 H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 4
1 R57 2 301_0402_1% C23 HT_RXCALP HT_TXCALP B24 1 R58 2 301_0402_1%
A24 HT_RXCALN HT_TXCALN B25

0718 Place within 1" RS780M_FCBGA528 0718 Place within 1"

RX781R1@
layout 1:2 layout 1:2
4 4

NEED CHECK R68 & R69 WITH AMD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 10 of 58
A B C D E
 A B C D E

1 1

PV: follow check list connect to GND

U3C
F12 AVDD1(NC) TXOUT_L0P(NC) A22
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22
F14 AVDDDI(NC) TXOUT_L1P(NC) A21
G15 AVSSDI(NC) TXOUT_L1N(NC) B21
H15 AVDDQ(NC) TXOUT_L2P(NC) B20
H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20
TXOUT_L3P(NC) A19
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19

CRT/TVOUT
F17 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
TXOUT_U0N(NC) A18
G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17
E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20
F18 GREENb(NC) TXOUT_U2N(NC) D21
E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 BLUEb(NC) TXOUT_U3N(NC) D19
+1.8VS +VDDA18HTPLL
L10 A11 B16
14 UMA_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
1 2 14 UMA_VSYNC B11 DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16
BLM18PG121SN1D_0603 1 F8 D16
DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
E8 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17
C179 PV: follow check list connect to GND PV: follow check list connect to GND
2.2U_0603_6.3V4Z G14
2 DAC_RSET(PWM_GPIO1)
VDDLTP18(NC) A13
A12 PLLVDD(NC) VSSLTP18(NC) B13
2 2
D14 PLLVDD18(NC)
B12 A15

LVTM
PLLVSS(NC) VDDLT18_1(NC)
B15

PLL PWR
+1.8VS +VDDA18PCIEPLL VDDLT18_2(NC)
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
L11 B14
VDDLT33_2(NC)
1 2 +VDDA18PCIEPLL D7 VDDA18PCIEPLL1
BLM18PG121SN1D_0603 1 E7 C14
R67 0_0402_5% VDDA18PCIEPLL2 VSSLT1(VSS)
VSSLT2(VSS) D15
C180 1 2 NB_RESET# D8 C16
14,15,30,36,37,38,44,45 PLT_RST# SYSRESETb VSSLT3(VSS)
2.2U_0603_6.3V4Z NB_PWRGD A10 C18
2 32 NB_PWRGD POWERGOOD VSSLT4(VSS)
6,30 LDT_STOP# C10 LDTSTOPb VSSLT5(VSS) C20
+1.8VS C12 E20

PM
6,30 CPU_LDT_REQ# ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
1 2 NB_PWRGD 26 CLK_NBHT C25 HT_REFCLKP
R371 300_0402_5% C24
26 CLK_NBHT# HT_REFCLKN

26 NB_OSC_14.318M E11 REFCLK_P/OSCIN(OSCIN)

CLOCKs
F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9
LVDS_BLON(PCE_RCALRP) F7
For SB700 A12 use +1.1VS 1 2 1 2 26 NBGFX_CLK T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12
R71 R72 T1
26 NBGFX_CLK# GFX_REFCLKN
4.7K_0402_5% 4.7K_0402_5%
U1 GPP_REFCLKP
U2 GPP_REFCLKN

26 CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)
26 CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)
B9 I2C_CLK
A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
DDC_DATA0/AUX0N(NC) HPD(NC)
A8 DDC_CLK0/AUX0P(NC)
3 3
B7 DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) D12 1 2 SUS_STAT# 32
A7 R77 0_0402_5% SUS_STAT_R# 14 Strap pin
DDC_DATA1/AUX1N(NC)
THERMALDIODE_P AE8
+3VS 2 1 B10 STRP_DATA THERMALDIODE_N AD8

R88 10K_0402_5% G11 D13 1 2

RSVD TESTMODE R80
C8 1.8K_0402_5%
14 AUX_CAL AUX_CAL(NC)
Strap pin RS780M_FCBGA528
RX781R1@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 11 of 58
A B C D E
 2 1

U3D
PAR 4 OF 6
AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19

SBD_MEM/DVO_I/F
AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17 MEM_BA1(NC)
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
B B
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
AD18 MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
V14 MEM_ODT(NC)
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
W14 MEM_CKN(NC)
IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18

RS780M_FCBGA528

RX781R1@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 12 of 58
2 1
 A B C D E

U3F
A25 VSSAHT1 VSSAPCIE1 A2
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
1 L16 1
2A H19 VSSAHT7 VSSAPCIE7 G2
+1.1VS 2 1 +VDDHT J22 G4
0_0805_5% VSSAHT8 VSSAPCIE8
L17 VSSAHT9 VSSAPCIE9 H7
1 1 1 1 1 L22 VSSAHT10 VSSAPCIE10 J4
L17 L24 R7
C209 C206 C207 C208 C210 VSSAHT11 VSSAPCIE11
1 2 +1.1VS L25 VSSAHT12 VSSAPCIE12 L1
VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 M20 L2
2 2 2 2 2 U3E VSSAHT13 VSSAPCIE13
N22 VSSAHT14 VSSAPCIE14 L4
J17 A6 +VDDA11PCIE P20 L7
VDDHT_1 VDDPCIE_1 C211 10U_0805_10V4Z VSSAHT15 VSSAPCIE15
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 R19 VSSAHT16 VSSAPCIE16 M6
L16 VDDHT_3 VDDPCIE_3 C6 R22 VSSAHT17 VSSAPCIE17 N4
L18 0.1U_0402_16V4Z 0.1U_0402_16V4Z M16 D6 C212 10U_0805_10V4Z R24 P6
+VDDHTRX VDDHT_4 VDDPCIE_4 VSSAHT18 VSSAPCIE18
2 1 2A P16 VDDHT_5 VDDPCIE_5 E6 R25 VSSAHT19 VSSAPCIE19 R1
0_0805_5% R16 F6 C220 1 2 1U_0402_6.3V4Z H20 R2
VDDHT_6 VDDPCIE_6 C219 1U_0402_6.3V4Z VSSAHT20 VSSAPCIE20
1 1 1 1 T16 VDDHT_7 VDDPCIE_7 G7 1 2 U22 VSSAHT21 VSSAPCIE21 R4
PV:Change C215 from 4.7u to 10u H8 C222 1 2 1U_0402_6.3V4Z V19 V7
C215 C214 C216 C217 C218 VDDPCIE_8 C221 1U_0402_6.3V4Z VSSAHT22 VSSAPCIE22

GROUND
H18 VDDHTRX_1 VDDPCIE_9 J9 1 2 W22 VSSAHT23 VSSAPCIE23 U4
G19 K9 C224 2 1 0.1U_0402_16V4Z W24 V8
2 2 2 2 VDDHTRX_2 VDDPCIE_10 C223 0.1U_0402_16V4Z VSSAHT24 VSSAPCIE24
F20 VDDHTRX_3 VDDPCIE_11 M9 2 1 W25 VSSAHT25 VSSAPCIE25 V6
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21 L9 Y21 W1
VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
D22 VDDHTRX_5 VDDPCIE_13 P9 AD25 VSSAHT27 VSSAPCIE27 W2
0.1U_0402_16V4Z 0.1U_0402_16V4Z B23 R9 W4
VDDHTRX_6 VDDPCIE_14 VSSAPCIE28
A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
L19 V9 M14 W8
+VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30
+1.2V_HT 2 1 2A AE25 VDDHTTX_1 VDDPCIE_17 U9 N13 VSS13 VSSAPCIE31 Y6
0_0805_5% AD24 PJP3 P12 AA4
VDDHTTX_2 VSS14 VSSAPCIE32
1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 +1.1VS 1 2 +NB_VDDC P15 VSS15 VSSAPCIE33 AB5
AB22 VDDHTTX_4 VDDC_2 J14 R11 VSS16 VSSAPCIE34 AB1
C225 C226 C227 C228 C229 AA21 U16 PAD-OPEN 4x4m R14 AB7
VDDHTTX_5 VDDC_3 VSS17 VSSAPCIE35
Y20 VDDHTTX_6 VDDC_4 J11 T12 VSS18 VSSAPCIE36 AC3
2 2 2 2 2
W19 VDDHTTX_7 VDDC_5 K15 U14 VSS19 VSSAPCIE37 AC4

POWER
2
V18 VDDHTTX_8 VDDC_6 M12 VDD_CORE=10A U11 VSS20 VSSAPCIE38 AE1
2
U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T17 L11 V12 AB2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTTX_10 VDDC_8 VSS22 VSSAPCIE40
R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23
P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14

330U_D2E_2.5VM
C247

C240

C241

C242

C243

C230

C231

C244

C232

C233

C245
L22 2A N14 1 AA14 D11
+VDDA18PCIE VDDC_12 VSS26 VSS2
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 VSS27 VSS3 G8

C234
0_0805_5% P10 P13 + AB11 E14
VDDA18PCIE_2 VDDC_14 VSS28 VSS4
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 AB15 VSS29 VSS5 E15

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 AB17 VSS30 VSS6 J15
C235 C246 C236 C237 C238 C239 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
4.7U_0805_10V4Z W9 T11 AE20 K14
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
T10 VDDA18PCIE_8 VDDC_20 U12 K11 VSS34 VSS10 L15
R10 VDDA18PCIE_9 VDDC_21 T14
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Y9 J16 RS780M_FCBGA528
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_10 VDDC_22
AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
VDD_MEM5(NC) AB10
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10
G9 VDD18_2
AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 +3VS
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12

1 RS780M_FCBGA528
C251 RX781R1@
1U_0402_6.3V4Z
2
3
PV: follow check list connect to GND 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 13 of 58
A B C D E
 A B C D E

RS780 DFT_GPIO5 mux at CRT_VSYNC pull high to 3K DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

SI2: Change to 3K pull high
11 UMA_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO.
1 R101 3K_0402_5% 1
1 : Enable (RX780, RS780)
2 1
R102 @ 3K_0402_5% 0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
RS780 use register to control PCI-E configure 010 : 01011
011 : 00100
100 : 01010
101 : 01100
2
111 : 01011 2

DFT_GPIO1: LOAD_EEPROM_STRAPS

11 AUX_CAL 1 2 Selects Loading of STRAPS from EPROM

@R104
@ R104 150_0402_1%
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
D4 @ CH751H-40PT_SOD323-2 0 : I2C Master can load strap values from EEPROM if connected, or use
RS780 DFT_GPIO1 11 SUS_STAT_R# 2 1 PLT_RST# 11,15,30,36,37,38,44,45 default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
3 3

RS780 use HSYNC to enable SIDE PORT (internal pull high)

RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
2 1 0 : Enable
11 UMA_HSYNC
R107 @ 3K_0402_5%
RS780: Enables Side port memory ( RS780 use HSYNC#)
2 1 +3VS 1. Disable (RS780)
R125 3K_0402_5%
0 : Enable (RS780)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 14 of 58
A B C D E
 5 4 3 2 1

PCIE_GTX_C_MRX_P[0..15]
10 PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]
10 PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] Close to connector

10 PCIE_MTX_C_GRX_P[0..15] U5A
D D
PCIE_MTX_C_GRX_N[0..15] PART 1 OF 7
10 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P15 AK33 AG31 PCIE_GTX_MRX_P15 CV9 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P15
PCIE_MTX_C_GRX_N15 AJ33 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_N15 CV10 1
PCIE_RX0N PCIE_TX0N AG30 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N15

PCIE_MTX_C_GRX_P14 AJ35 AF31 PCIE_GTX_MRX_P14 CV11 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P14

PCIE_MTX_C_GRX_N14 AJ34 PCIE_RX1P PCIE_TX1P PCIE_GTX_MRX_N14 CV12 1
PCIE_RX1N P PCIE_TX1N AF30 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N14
C
PCIE_MTX_C_GRX_P13 AH35 I AF28 PCIE_GTX_MRX_P13 CV13 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P13
PCIE_MTX_C_GRX_N13 AH34 PCIE_RX2P PCIE_TX2P PCIE_GTX_MRX_N13 CV14 1
AF27 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N13
PCIE_RX2N - PCIE_TX2N
E
PCIE_MTX_C_GRX_P12 AG35 AD31 PCIE_GTX_MRX_P12 CV15 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P12
PCIE_MTX_C_GRX_N12 AG34 PCIE_RX3P X PCIE_TX3P
AD30 PCIE_GTX_MRX_N12 CV16 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N12
PCIE_RX3N PCIE_TX3N
P
PCIE_MTX_C_GRX_P11 AF33 R AD28 PCIE_GTX_MRX_P11 CV17 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P11
PCIE_RX4P PCIE_TX4P
PCIE_MTX_C_GRX_N11 AE33
PCIE_RX4N
E PCIE_TX4N AD27 PCIE_GTX_MRX_N11 CV18 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N11
S
PCIE_MTX_C_GRX_P10 AE35
PCIE_RX5P
S PCIE_TX5P AB31 PCIE_GTX_MRX_P10 CV19 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P10
PCIE_MTX_C_GRX_N10 AE34 AB30 PCIE_GTX_MRX_N10 CV20 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N10
PCIE_RX5N PCIE_TX5N
I
PCIE_MTX_C_GRX_P9 AD35 AB28 PCIE_GTX_MRX_P9 CV21 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P9
PCIE_MTX_C_GRX_N9 PCIE_RX6P N PCIE_TX6P PCIE_GTX_MRX_N9 CV22 1
AD34 PCIE_RX6N PCIE_TX6N AB27 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N9
T
C C
PCIE_MTX_C_GRX_P8
E PCIE_GTX_MRX_P8 CV23 1
AC35 PCIE_RX7P PCIE_TX7P AA31 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P8
PCIE_MTX_C_GRX_N8 AC34 R AA30 PCIE_GTX_MRX_N8 CV24 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N8
PCIE_RX7N PCIE_TX7N
F
PCIE_MTX_C_GRX_P7 AB33 A AA28 PCIE_GTX_MRX_P7 CV25 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P7
PCIE_MTX_C_GRX_N7 PCIE_RX8P PCIE_TX8P PCIE_GTX_MRX_N7 CV26 1
AA33 PCIE_RX8N C PCIE_TX8N AA27 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N7
E
PCIE_MTX_C_GRX_P6 AA35 W31 PCIE_GTX_MRX_P6 CV27 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N6 PCIE_RX9P PCIE_TX9P PCIE_GTX_MRX_N6 CV28 1
AA34 PCIE_RX9N PCIE_TX9N W30 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N6

PCIE_MTX_C_GRX_P5 Y35 W28 PCIE_GTX_MRX_P5 CV29 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P5

PCIE_MTX_C_GRX_N5 PCIE_RX10P PCIE_TX10P PCIE_GTX_MRX_N5 CV30 1
Y34 PCIE_RX10N PCIE_TX10N W27 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N5

PCIE_MTX_C_GRX_P4 W35 V31 PCIE_GTX_MRX_P4 CV31 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P4

PCIE_MTX_C_GRX_N4 PCIE_RX11P PCIE_TX11P PCIE_GTX_MRX_N4 CV32 1
W34 PCIE_RX11N PCIE_TX11N V30 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N4

PCIE_MTX_C_GRX_P3 V33 V28 PCIE_GTX_MRX_P3 CV33 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P3

PCIE_MTX_C_GRX_N3 PCIE_RX12P PCIE_TX12P PCIE_GTX_MRX_N3 CV34 1
U33 PCIE_RX12N PCIE_TX12N V27 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N3

PCIE_MTX_C_GRX_P2 U35 U31 PCIE_GTX_MRX_P2 CV35 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P2

PCIE_MTX_C_GRX_N2 PCIE_RX13P PCIE_TX13P PCIE_GTX_MRX_N2 CV36 1
U34 PCIE_RX13N PCIE_TX13N U30 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N2

B PCIE_MTX_C_GRX_P1 PCIE_GTX_MRX_P1 CV37 1 B

T35 PCIE_RX14P PCIE_TX14P U28 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 T34 U27 PCIE_GTX_MRX_N1 CV38 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N1
PCIE_RX14N PCIE_TX14N

PCIE_MTX_C_GRX_P0 R35 R31 PCIE_GTX_MRX_P0 CV39 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P0

PCIE_MTX_C_GRX_N0 PCIE_RX15P PCIE_TX15P PCIE_GTX_MRX_N0 CV40 1
R34 PCIE_RX15N PCIE_TX15N R30 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N0

Clock Calibration
AJ31 RV5 2K_0402_1%
26 CLK_PCIE_VGA PCIE_REFCLKP
26 CLK_PCIE_VGA# AJ30 PCIE_REFCLKN PCIE_CALRN AG26 1 2 +PCIE_VDDC
RV6 1.27K_0402_1%
SM Bus AJ27 PCIE_CALRP 1 2
PCIE_CALRP
AK35 NC_SMB_DATA
AK34 NC_SMBCLK NC_DRAM_0 AF3
NC_DRAM_1 AG9
11,14,30,36,37,38,44,45 PLT_RST# AM32 PERSTB NC_AC_BATT AK29
NC_FAN_TACH AK14
216-0683008 A11 M86-M_BGA880

M86R1@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 15 of 58
5 4 3 2 1
 5 4 3 2 1

U5B
PART 2 OF 7

For M86 HDA Enable AM12 VIP_0 TXCAM_DPA0P AN9 HDMI_CLK-_VGA 29 20mA
AL12 AN10 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603 52mA AJ12
VIP_1 TXCAP_DPA0N HDMI_CLK+_VGA 29
+DPA_PVDD 2 1 +1.8VS
0.1U_0402_16V4Z +DPLL_PVDD VIP_3 VIP_2 VIP / I2C LV1
2 1 +3VS_DELAY 1 2 AH12 VIP_3 TX0M_DPA1P AR10 HDMI_TX0-_VGA 29 2 2 2
+1.8VS LV2 1 1 1 RV7 10K_0402_5% AM10 AP10
VIP_4 TX0P_DPA1N HDMI_TX0+_VGA 29
CV47 <BOM Structure> AL10 10U_0603_6.3V6M CV42 CV43 CV44
CV46 1U_0402_6.3V4Z VIP_5 0.1U_0402_16V4Z
AJ10 VIP_6 TX1M_DPA2P AR11 HDMI_TX1-_VGA 29
CV45 1 1 1
AH10 VIP_7 TX1P_DPA2N AP11 HDMI_TX1+_VGA 29
2 2 2
10U_0603_6.3V6M AM9 AR12 1U_0402_6.3V4Z
VHAD_0 TX2M_DPA3P HDMI_TX2-_VGA 29
AL9 VHAD_1 TX2P_DPA3N AP12 HDMI_TX2+_VGA 29
D
AJ9 AR14
20mA BLM18PG121SN1D_0603 D
BLM18PG121SN1D_0603 68mA VPHCTL TXCBM_DPB0P
AP14 +DPB_PVDD 2 1 +1.8VS
0.1U_0402_16V4Z +PCIE_PVDD TXCBP_DPB0N LV3
+1.8VS 2 1 AL7 VPCLK0 1 1 1
LV4 1 1 1 AK7 AR15
CV48 CV49 CV41 VIPCLK TX3M_DPB1P 1U_0402_6.3V4Z CV50 CV51 CV52
TX3P_DPB1N AP15
AM7 10U_0603_6.3V6M
25 PSYNC PSYNC 2 2 2
10U_0603_6.3V6M 1U_0402_6.3V4Z AR16
2 2 2 TX4M_DPB2P
AJ7 DVALID TX4P_DPB2N AP16
0.1U_0402_16V4Z
LCD_DDC_DAT AK6 AR17
28 LCD_DDC_DAT SDA TX5M_DPB3P
LCD_DDC_CLK AM6 AP17
BLM18PG121SN1D_0603 LCD 28 LCD_DDC_CLK SCL TX5P_DPB3N
345mA AN8 AM14 +DPA_PVDD
DVPCNTL__MVP_0 DPA_PVDD
2 1 1U_0402_6.3V4Z +MPVDD AP8 DVPCNTL__MVP_1 DPA_PVSS AL14
LV5 1 1 1 AG1
+VGA_CORE DVPCNTL_0
CV53 CV54 CV55 AH3 INTEGRATED AH17 +DPB_PVDD BLM18PG121SN1D_0603
AH2
DVPCNTL_1 TMDS/DP DPB_PVDD
AG17 +DPA_VDDR 200mA 2 1 +1.1VS
10U_0603_6.3V6M 0.1U_0402_16V4Z DVPCNTL_2 DPB_PVSS LV6
AH1 DVPCLK 2 2 2
2 2 2 +DPB_VDDR
AJ3 DVPDATA_0 DPB_VDDR_1 AN19
AJ2 AN20 10U_0603_6.3V6M CV56 CV57 CV58
DVPDATA_1 MULTI_GFX DPB_VDDR_2 +DPA_VDDR 0.1U_0402_16V4Z
AJ1 DVPDATA_2 EXTERNAL DPA_VDDR_3 AP19
1 1 1
AK2 DVPDATA_3 TMDS DPA_VDDR_4 AR19
AK1 1U_0402_6.3V4Z
DVPDATA_4
100mA AL3 DVPDATA_5 DPB_VSSR_1 AN18
BLM18PG121SN1D_0603 AL2 AP18
0.1U_0402_16V4Z +DPLL_VDDC DVPDATA_6 DPB_VSSR_2 BLM18PG121SN1D_0603
2 1 AL1 AR18
+1.1VS
LV7 1 1 1 AM3
DVPDATA_7 DPB_VSSR_3
AN16 +DPB_VDDR 200mA 2 1 +1.1VS
CV59 DVPDATA_8 DPB_VSSR_4 LV8
AM2 DVPDATA_9 DPB_VSSR_6 AN17 1 1 1
CV60 CV61 AN2 AN15
1U_0402_6.3V4Z DVPDATA_10 DPA_VSSR_5 0.1U_0402_16V4Z CV62 CV63 CV64
AP3 DVPDATA_11 DPA_VSSR_7 AN11
2 2 2 10U_0603_6.3V6M
AR3 DVPDATA_12 DPA_VSSR_8 AN12
10U_0603_6.3V6M 2 2 2
AN4 DVPDATA_13 DPA_VSSR_9 AN13
C C
AR4 DVPDATA_14 DPA_VSSR_10 AN14
AP4 1U_0402_6.3V4Z
DVPDATA_15
AN5 DVPDATA_16 DP_CALR AG15 1 2
AR5 AH18 RV8 150_0402_1%
DVPDATA_17 NC_TPVDDC
AP5 DVPDATA_18 NC_TPVSSC AG18
AP6 DVPDATA_19 HPD1 AG6 HPD 29
25 VRAM_ID0 AR6 DVPDATA_20
25 VRAM_ID1 AN7 DVPDATA_21
+3VS_DELAY AP7 AR31
25 VRAM_ID2 DVPDATA_22 R RED 27
AR7 AP31 BLM18PG121SN1D_0603
25 VRAM_ID3 DVPDATA_23 RB +AVDD 70mA 2 1 +1.8VS
THM_ALERT# 1 2 AG2 AR30 1 1 1 LV9
25 GPIO_0 GPIO_0 G GREEN 27
RV9 10K_0402_5% AF2 AP30
25 GPIO_1 GPIO_1 GENERAL GB
VGA_DDC_DAT 1 2 AF1 CV65 CV66 CV67
RV10 10K_0402_5% GPIO_2 PURPOSE
2 RV11 1 AE3 GPIO_3 B AR29 BLUE 27
1U_0402_6.3V4Z 10U_0603_6.3V6M
VGA_DDC_CLK I/O 2 2 2
1 2 AE2 GPIO_4 BB AP29
RV12 10K_0402_5% 10K_0402_5% AE1 DAC1 0.1U_0402_16V4Z
25 GPIO_5 GPIO_5
LCD_DDC_DAT 1 2 AD3 AN29
GPIO_6 HSYNC CRT_HSYNC 25,27
RV13 10K_0402_5% AD2 AN30
45 ENBKL GPIO_7_BLON VSYNC CRT_VSYNC 27
LCD_DDC_CLK 1 2 AD1
25 SOUT_GPIO8 GPIO_8_ROMSO
RV14 10K_0402_5% AD5 AN31 1 2 BLM18PG121SN1D_0603
HDMIDAT_VGA 1 2 @
25 SIN_GPIO9
SCLK_GPIO10 AD4
GPIO_9_ROMSI RSET RV15 499_0402_1% +A2VDD 65mA 2 1
T4 PAD GPIO_10_ROMSCK
RV16 10K_0402_5% +3VS_DELAY 2 RV108 1 AC3 AR32 +AVDD 1 1 1 LV10 +3VS_DELAY
25 GPIO_11 GPIO_11 AVDD
HDMICLK_VGA 1 2 AC2
25 GPIO_12 GPIO_12
RV17 10K_0402_5% 10K_0402_5% AC1 AP32 10U_0603_6.3V6M CV68 CV69 CV70
25 GPIO_13 GPIO_13 AVSSQ
CLKREQ_GPIO23 1 2 AB3 1U_0402_6.3V4Z
RV18 10K_0402_5% GPIO_14_HPD2 +VDD1DI 2 2 2
55 VGA_PWSELECT AB2 GPIO_15_PWRCNTL_0 VDD1DI AR28
27M_SSIN AB1 AP28 0.1U_0402_16V4Z
GPIO_16_SSIN VSS1DI
For PCIE reference clock @
25 THM_ALERT# AF5 GPIO_17_THERMAL_INT
AF4 GPIO_18_HPD3 R2 AM19
2 RV107 1 AG4 GPIO_19_CTF R2B AL19
AG3 BLM18PG121SN1D_0603
B 10K_0402_5% AD9
GPIO_20_PWRCNTL_1
AM18 +A2VDDQ 10mA 2 1 +1.8VS
B
GPIO_21_BBEN G2 LV11
25 SCS#_GPIO22 AD8 GPIO_22_ROMCSB G2B AL18 1 1 1
CLKREQ_GPIO23 AD7
JMODE_GPIO24 GPIO_23_CLKREQB 10U_0603_6.3V6M CV71 CV72 CV73
2 1 AB4 GPIO_24_JMODE B2 AM17
RV19 1K_0402_5% AB6 AL17 1U_0402_6.3V4Z
GPIO_25_TDI B2B 2 2 2
AB7 GPIO_26_TCK
XTALIN XTALOUT AB9 DAC2 AK19 0.1U_0402_16V4Z
GPIO_27_TMS C
AA9 GPIO_28_TDO Y AK18
@ 1.1 PV ADD +1.8VS AF8 AK17
R234 2 GEN_A COMP
11M_0402_5% AF7 GEN_B
1

RV22 AG5 AL15 BLM18PG121SN1D_0603

499_0402_1% AP9
GEN_C V2SYNC
AM15 +VDD1DI 85mA 2 1 +1.8VS
GEN_D_HPD4 H2SYNC LV12
AR9 GEN_E 1 1 1
YV1 AP13 AM21 +A2VDD
GEN_F A2VDD CV74 CV75 CV76
4 3 AR13
2

GND OUT GEN_G +A2VDDQ 1U_0402_6.3V4Z 10U_0603_6.3V6M

A2VDDQ AL21
+VGA_VREF 2 2 2
1 IN GND 2 1 CV78 AD12 VREFG
1 AK21 0.1U_0402_16V4Z
A2VSSQ
1

@ 27MHz_16PF_6P27000126 @ 22P_0402_50V8J
RV23 1 +DPLL_PVDD AR20 AH22 +VDD1DI
CV77 2 249_0402_1% CV79 DPLL_PVDD VDD2DI
AP20 DPLL_PVSS VSS2DI AG22
2 @ 22P_0402_50V8J
+PCIE_PVDD AM35 AJ21 1 2
2

2 PCIE_PVDD R2SET RV24 715_0402_1% RED 1 2

0.1U_0402_16V4Z AM29 RV25 @ 150_0402_1%
+MPVDD DDC1DATA GREEN
A14 MPVDD DDC1CLK AL29 1 2
B15 PLL RV26 @ 150_0402_1%
75_0402_1% MPVSS CLOCKS DDC BLUE
AJ15 1 2
2 1 XTALIN AR33 DP AUX DDC2DATA AH15 RV27 @ 150_0402_1%
26 27M_CLK XTALIN DDC2CLK
RV28 XTALOUT AP33 XTALOUT
1

AJ5 VGA_DDC_DAT
RV30 +DPLL_VDDC AG19
DDC3DATA_DP3_AUXN
AJ4 VGA_DDC_CLK
VGA_DDC_DAT 27 CRT
A DPLL_VDDC DDC3CLK_DP3_AUXP VGA_DDC_CLK 27 A
100_0402_1%
AG21 TS_FDO DDC4DATA_DP4_AUXN AH14 HDMIDAT_VGA 29
AG14 HDMICLK_VGA 29 HDMI
2

1.1 PV change 100K to 100 THERMAL DDC4CLK_DP4_AUXP

25 D- AK4 DMINUS
25 D+ AM4 DPLUS M86R1@
216-0683008 A11 M86-M_BGA880
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
1 2 27M_SSIN
26 27M_SSC
RV165 @ 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
401621 C
Reserve DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 16 of 58
5 4 3 2 1
 5 4 3 2 1

D D

U5F
320mA PART 7 OF 7
+1.8VS BLM18PG121SN1D_0603 2 1
1 2 1U_0402_6.3V4Z +LVDDR AJ26 AG7 RV33 10K_0402_5%
LV13 LVDDR_1 ControlVARY_BL
1 1 1 AH26 LVDDR_2
DIGON AJ6 VGA_ENVDD 28
CV84 CV82 CV83
+LVDDC AK27
2 2 2 LVDDC_1
AL27 LVDDC_2 TXCLK_UP AK24 LVDS_BCLK+ 28
10U_0603_6.3V6M 0.1U_0402_16V4Z AL24
TXCLK_UN LVDS_BCLK- 28
AM24 LVSSR_1 TXOUT_U0P AN27 LVDS_B0+ 28
LVDDC+LVDDR=400mA AN28 LVSSR_2 TXOUT_U0N AN26 LVDS_B0- 28
C AN21 AP27 LVDS_B1+ 28 C
LVSSR_3 TXOUT_U1P
AN24 LVSSR_4 TXOUT_U1N AR27 LVDS_B1- 28
+1.8VS AN25 LVSSR_5 TXOUT_U2P AG24 LVDS_B2+ 28
1 2 1U_0402_6.3V4Z +LVDDC AM22 AH24 LVDS_B2- 28
LV14 LVSSR_6 TXOUT_U2N
1 1 1 AP21 AK26

LVDS channel
BLM18PG121SN1D_0603 LVSSR_7 TXOUT_U3P
AP26 LVSSR_8 TXOUT_U3N AL26
CV85 CV86 CV87 AM27 LVSSR_9
AR21 LVSSR_10 TXCLK_LP AR22 LVDS_ACLK+ 28
2 2 2
AR26 LVSSR_11 TXCLK_LN AP22 LVDS_ACLK- 28
10U_0603_6.3V6M 0.1U_0402_16V4Z AM26 AN23 LVDS_A0+ 28
LVSSR_12 TXOUT_L0P
AJ22 LVSSR_13 TXOUT_L0N AN22 LVDS_A0- 28
AJ24 LVSSR_14 TXOUT_L1P AP23 LVDS_A1+ 28
TXOUT_L1N AR23 LVDS_A1- 28
40mA TXOUT_L2P AP24 LVDS_A2+ 28
+1.8VS TXOUT_L2N AR24 LVDS_A2- 28
2 1 1U_0402_6.3V4Z +LPVDD AL22 AP25
LV15 LPVDD TXOUT_L3P
1 1 1 AK22 LPVSS TXOUT_L3N AR25
BLM18PG121SN1D_0603
CV88 CV89 CV90
216-0683008 A11 M86-M_BGA880
2 2 2
0.1U_0402_16V4Z 10U_0603_6.3V6M
M86R1@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 17 of 58
5 4 3 2 1
 5 4 3 2 1

U5D
+1.8VS +PCIE_VDDR_M86
PART 5 OF 7 432mA
3.48A D1 AR34 1 2 +1.8VS
VDDR1_1 PCIE_VDDR_1 LV16 BLM18PG121SN1D_0603
A8 VDDR1_2 PCIE_VDDR_2 AL33

+
2 1 1 2 A12 VDDR1_3 PCIE_VDDR_3 AM33 1 2
CV91 330U_V_2.5VM_R9M CV105 1U_0402_6.3V4Z A16 AN33 CV92 10U_0603_6.3V6M
VDDR1_4 PCIE_VDDR_4
1 2 A20 VDDR1_5 PCIE_VDDR_5 AN34 1 2
1 2 CV93 1U_0402_6.3V4Z A24 AN35 CV94 1U_0402_6.3V4Z
CV95 10U_0603_6.3V6M VDDR1_6 PCIE_VDDR_6
1 2 A28 VDDR1_7 PCIE_VDDR_7 AP34 1 2

Memory I/O
1 2 CV96 1U_0402_6.3V4Z B1 AP35 CV106 0.1U_0402_16V4Z
CV97 10U_0603_6.3V6M VDDR1_8 PCIE_VDDR_8
1 2 H1 VDDR1_9
D 1 2 CV98 1U_0402_6.3V4Z H35 R26 D
CV99 10U_0603_6.3V6M VDDR1_10 PCIE_VDDC_1 +PCIE_VDDC
1 2 L18 VDDR1_11 PCIE_VDDC_2 U26
1 2 CV100 1U_0402_6.3V4Z L19 V25
CV101 10U_0603_6.3V6M 1 2 L21
VDDR1_12 PCIE_VDDC_3
V26
1.2A 1 2 +1.1VS
CV107 1U_0402_6.3V4Z VDDR1_13 PCIE_VDDC_4 LV17 BLM18PG121SN1D_0603
1 2 L22 VDDR1_14 W25

PCI-Express
CV102 1U_0402_6.3V4Z PCIE_VDDC_5
1 2 M10 VDDR1_15 PCIE_VDDC_6 W26 1 2
1 2 CV103 1U_0402_6.3V4Z M35 AA25 CV108 10U_0603_6.3V6M
CV109 1U_0402_6.3V4Z VDDR1_16 PCIE_VDDC_7
1 2 P10 VDDR1_17 PCIE_VDDC_8 AD26 1 2
1 2 CV104 1U_0402_6.3V4Z T1 AF26 CV110 1U_0402_6.3V4Z
CV111 1U_0402_6.3V4Z VDDR1_18 PCIE_VDDC_9
Y1 VDDR1_19 PCIE_VDDC_10 AA26 1 2
1 2 B35 AB25 CV112 1U_0402_6.3V4Z
CV113 1U_0402_6.3V4Z VDDR1_20 PCIE_VDDC_11
M1 VDDR1_21 PCIE_VDDC_12 AB26 1 2
D35 CV114 0.1U_0402_16V4Z
VDDR1_22
K10 VDDR1_23 1 2
K12 N13 CV115 1U_0402_6.3V4Z
VDDR1_24 VDDC_1
K24 VDDR1_25 VDDC_2 N15 1 2
K26 N18 CV116 1U_0402_6.3V4Z
VDDR1_26 VDDC_3
L14 VDDR1_27 VDDC_4 N21
L15 VDDR1_28 VDDC_5 N23
BLM18PG121SN1D_0603 L17 P14
76mA VDDR1_29 VDDC_6
P17
+1.8VS +VDDR4 +1.8VS VDDC_7
+VDD_CT

I/O Internal
2 1 AA11 VDD_CT_1 VDDC_8 P19
LV18 AB11 P22
BLM18PG121SN1D_0603 VDD_CT_2 VDDC_9
1 2 AD10 VDD_CT_3 VDDC_10 V18
2 1 CV117 10U_0603_6.3V6M AF10 V21 +VGA_CORE
LV19 VDD_CT_4 VDDC_11
1 2 CV118
1 2
1U_0402_6.3V4Z R11
P VDDC_12 V23
W14
CV119 10U_0603_6.3V6M 2 1 R25
VDD_CT_5
O VDDC_13
W17
18A
CV120 0.1U_0402_16V4Z VDD_CT_6 VDDC_14
1 2 U11 W19

Core
VDD_CT_7 VDDC_15
CV121 1U_0402_6.3V4Z U25 VDD_CT_8 W VDDC_16 W22 1 2 1 2 1 2
1 2 AA15 @ CV122 330U_V_2.5VM_R9M CV123 1U_0402_6.3V4Z CV124 1U_0402_6.3V4Z

+
C CV125 0.1U_0402_16V4Z E VDDC_17 C
AE14 VDDR3_1 VDDC_18 AA18 1 2 1 2
CV126 1U_0402_6.3V4Z CV127 1U_0402_6.3V4Z

+
+3VS_DELAY AE15 AA21 1 2
AF12
VDDR3_2
VDDR3_3
R VDDC_19
VDDC_20 AA23 @ CV128 330U_V_2.5VM_R9M 1 2 1 2
1 2 AE17 AB14 CV129 1U_0402_6.3V4Z CV130 1U_0402_6.3V4Z
CV131 10U_0603_6.3V6M VDDR3_4 VDDC_21
VDDC_22 AB17 1 2 1 2 1 2
1 2 +VDDR4 AP2 AB19 CV132 10U_0603_6.3V6M CV133 1U_0402_6.3V4Z CV134 1U_0402_6.3V4Z
CV135 1U_0402_6.3V4Z VDDR4_1 VDDC_23
AR2 VDDR4_2 VDDC_24 AB22 1 2 1 2 1 2
1 2 1.1 PV ADD AC13 CV136 10U_0603_6.3V6M CV137 1U_0402_6.3V4Z CV138 1U_0402_6.3V4Z
+1.8VS +VDDR5 CV139 1U_0402_6.3V4Z VDDC_25
+VDDR5 AN1 VDDR5_1 VDDC_26 AC15 1 2 1 2 1 2
1.1 PV ADD 1 2 AP1 AC18 CV140 10U_0603_6.3V6M CV141 1U_0402_6.3V4Z CV142 1U_0402_6.3V4Z
BLM18PG121SN1D_0603 CV144 1U_0402_6.3V4Z VDDR5_2 VDDC_27
VDDC_28 AC21 1 2 1 2 1 2
2 1 +VDD_MEM_CLK0 A25 AC23 CV145 10U_0603_6.3V6M CV146 1U_0402_6.3V4Z CV147 1U_0402_6.3V4Z
LV20 +VDD_MEM_CLK1 VDDRHA_1 VDDC_29
A32 VDDRHA_2 VDDC_30 AE18 1 2 1 2 1 2
1 2 AE22 CV149 10U_0603_6.3V6M CV150 1U_0402_6.3V4Z CV151 1U_0402_6.3V4Z
CV152 10U_0603_6.3V6M VDDC_31
B25 VSSRHA_1 VDDC_32 AE19 1 2 1 2

Memory I/O
1 2 B32 AE21 CV153 1U_0402_6.3V4Z CV154 1U_0402_6.3V4Z

Clock
CV148 1U_0402_6.3V4Z VSSRHA_2 VDDC_33
VDDC_34 R13 1 2 1 2
1 2 +VDD_MEM_CLK2 B2 R15 CV155 1U_0402_6.3V4Z CV156 1U_0402_6.3V4Z
CV143 0.1U_0402_16V4Z +VDD_MEM_CLK3 VDDRHB_1 VDDC_35
L1 VDDRHB_2 VDDC_36 R18
VDDC_37 R21
C2 VSSRHB_1 VDDC_38 R23
L2 VSSRHB_2 VDDC_39 U14
VDDC_40 U17
W13 BBN_1 VDDC_41 U19

Back
Back Bias Disable AA13 U22

Bias
BBN_2 VDDC_42
VDDC_43 V15
BLM18PG121SN1D_0603 1U_0402_6.3V4Z +VGA_CORE U13 W11
+VDD_MEM_CLK0 BBP_1 VDDC_44 BLM18PG121SN1D_0603
+1.8VS 2 1 V13 BBP_2
LV21 1 1 2 1 1 M12 +VDDCI 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 1 +VGA_CORE
VDDCI_1 LV22
VDDCI_2 M24 1 1 1 1
CV157 CV158 CV159 CV160 CV161 P11 CV162 CV163 CV164
B 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDDCI_3 CV165 B
VDDCI_4 P25
2 2 1 2 2
10U_0603_6.3V6M 0.1U_0402_16V4Z 216-0683008 A11 M86-M_BGA880 2 2 2 2
1U_0402_6.3V4Z 10U_0603_6.3V6M

BLM18PG121SN1D_0603 1U_0402_6.3V4Z
+1.8VS 2 1 +VDD_MEM_CLK1
LV23 1 1 2
CV166 CV167 CV168 QV3
2 2 1
100mA

S
1 3

D
+3VS_DELAY +3VS
10U_0603_6.3V6M 0.1U_0402_16V4Z
SI2301BDS_SOT23

2
RV34

G
2
100K_0402_5%

BLM18PG121SN1D_0603 1U_0402_6.3V4Z
+1.8VS 2 1 +VDD_MEM_CLK2 From 1.8VS<-->1.1VSP Chip

1
LV24 1 1 2
1 D
CV169 CV170 CV171
1 2 2 Q9
2 2 1 52 1.1VS_POK
R42 0_0402_5% G
10U_0603_6.3V6M 0.1U_0402_16V4Z 1 S 2N7002_SOT23-3
3

+3VS 1 2
R403 4.7K_0402_5% CV172
0.1U_0402_16V4Z
BLM18PG121SN1D_0603 1U_0402_6.3V4Z 2
+1.8VS 2 1 +VDD_MEM_CLK3
A A
LV25 1 1 2
CV173 CV174 CV175
2 2 1
10U_0603_6.3V6M 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 18 of 58
5 4 3 2 1
 5 4 3 2 1

U5E
Part 6 of 7
P33 PCIE_VSS_1 VSS_66 P6
P34 PCIE_VSS_2 VSS_67 M9
P35 PCIE_VSS_3 VSS_68 M26
R27 PCIE_VSS_4 VSS_69 K28
R28 PCIE_VSS_5 VSS_70 M32
R29 PCIE_VSS_6 VSS_71 N14
R32 PCIE_VSS_7 VSS_72 N17
R33 PCIE_VSS_8 VSS_73 N19
U29 PCIE_VSS_9 VSS_74 N22
U32 PCIE_VSS_10 VSS_75 N33
D V29 PCIE_VSS_11 VSS_76 N3 D
V32 PCIE_VSS_12 VSS_77 R5

PCI-Express GND
T33 PCIE_VSS_13 VSS_78 U8
V34 PCIE_VSS_14 VSS_79 P13
V35 PCIE_VSS_15 VSS_80 P15
W29 PCIE_VSS_16 VSS_81 P18
W32 PCIE_VSS_17 VSS_82 P21
W33 PCIE_VSS_18 VSS_83 P23
AA29 PCIE_VSS_19 VSS_84 P26
AA32 PCIE_VSS_20 VSS_85 P29
AB29 PCIE_VSS_21 VSS_86 P30
AB32 PCIE_VSS_22 VSS_87 R1
Y33 PCIE_VSS_23 VSS_88 U5
AB34 PCIE_VSS_24 VSS_89 P9
AB35 PCIE_VSS_25 VSS_90 R10
AC33 PCIE_VSS_26 VSS_91 R14
AD29 PCIE_VSS_27 VSS_92 R17
AD32 PCIE_VSS_28 VSS_93 R19
AF29 PCIE_VSS_29 VSS_94 R22
AF32 PCIE_VSS_30 VSS_95 V3
AD33 PCIE_VSS_31 VSS_96 AK9
AF34 PCIE_VSS_32 VSS_97 U10
AF35 PCIE_VSS_33 VSS_98 U15
AG27 PCIE_VSS_34 VSS_99 U18
AG29 PCIE_VSS_35 VSS_100 U21
AG32 PCIE_VSS_36 VSS_101 U23
AG33 PCIE_VSS_37 VSS_102 V7
AJ29 PCIE_VSS_38 VSS_103 W8
AJ32 PCIE_VSS_39 VSS_104 V10
AH33 PCIE_VSS_40 VSS_105 V14
AL34 PCIE_VSS_41 VSS_106 V17
C AL35 V19 C
PCIE_VSS_42 VSS_107
AK32 PCIE_VSS_43 VSS_108 V22
VSS_109 V1
A2 VSS_1 VSS_110 AK12
A34 VSS_2 VSS_111 V9
C3 VSS_3 VSS_112 W10
C5 VSS_4 VSS_113 W15
A4 VSS_5 VSS_114 W18
C18 VSS_6 VSS_115 W21
A21 VSS_7 VSS_116 W23
C23 VSS_8 VSS_117 AA6
C11 VSS_9 VSS_118 AA10
C13 VSS_10 VSS_119 AA14
C14 VSS_11 VSS_120 AA17
A18 VSS_12 VSS_121 AA19
A11 VSS_13 VSS_122 AA22
C26 VSS_14 VSS_123 AB8
C33 VSS_15 VSS_124 AB10
F35 VSS_16 VSS_125 AB13
R7 VSS_17 VSS_126 AB15
G10 VSS_18 VSS_127 AB18
F15 VSS_19 VSS_128 AB21
H17 VSS_20 VSS_129 AB23
G21 VSS_21 VSS_130 AC14
D29 VSS_22 VSS_131 AC17
A29 VSS_23 VSS_132 AC19
G1 VSS_24 VSS_133 AC22
F14 VSS_25 VSS_134 AF9
J15 VSS_26 VSS_135 AD6
E19 VSS_27 VSS_136 AB5
E22 VSS_28 VSS_137 AD24
B B
E24 VSS_29 VSS_138 W5
D7 VSS_30 VSS_139 AF6
G9 VSS_31 VSS_140 AF14
F26 VSS_32 VSS_141 AF21
G29 VSS_33 VSS_142 AF22
D33 VSS_34 VSS_143 AK10
M5 VSS_35 VSS_144 AF17
G4 VSS_36 VSS_145 AF18
E10 VSS_37 VSS_146 AF19
E12 VSS_38 VSS_147 AA3
F17 VSS_39 VSS_148 AG12
G18 VSS_40 VSS_149 AJ14
G22 VSS_41 VSS_150 AH21
F30 VSS_42 VSS_151 D4
J35 VSS_43 VSS_152 AF15
J18 VSS_44 VSS_153 AG10
H19 VSS_45 VSS_154 AN6
J21 VSS_46 VSS_155 AK15
F7 VSS_47 VSS_156 AJ17
J12 VSS_48 VSS_157 AJ18
J24 VSS_49 VSS_158 AJ19
J26 VSS_50 VSS_159 AF24
K30 VSS_51 VSS_160 AN32
J32 VSS_52 VSS_161 AK3
F33 VSS_53 VSS_162 AN3
K6 VSS_54 VSS_163 AR8
K9 VSS_55 VSS_164 AM1
K14 VSS_56 VSS_165 AK30
K15 VSS_57 VSS_166 V11
K17 VSS_58
A K18 VSS_59 A
K19 VSS_60 MECH_1 A35
K21 VSS_61 MECH_2 AR1
K22 VSS_62 MECH_3 AR35
M28 VSS_63
K3 VSS_64
L33 VSS_65 CORE GND
216-0683008 A11 M86-M_BGA880 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 19 of 58
5 4 3 2 1
 5 4 3 2 1

DQMA#[7..0] MDB[63..0]
DQMA#[7..0] 21,22 MDB[63..0] 23,24
QSA[7..0] MAB[12..0]

QSA#[7..0]
QSA[7..0]

QSA#[7..0]
21,22

21,22
Close to pin N34, N35 BB[2..0]
MAB[12..0]

BB[2..0]
23,24

23,24
MAA[12..0] DQMB#[7..0]
MAA[12..0] 21,22 DQMB#[7..0] 23,24
BA[2..0] +1.8VS QSB[7..0]
BA[2..0] 21,22 +1.8VS QSB[7..0] 23,24
MDA[63..0] QSB#[7..0]
MDA[63..0] 21,22 QSB#[7..0] 23,24

1
D D

1
RV36
100_0402_1% RV37
100_0402_1%

2
+MVREFDA +MVREFSA

1 U5G

1
CV177 1
RV39 0.1U_0402_16V4Z RV38 Part 4 of 7
100_0402_1% 100_0402_1% CV176
U5C 2 0.1U_0402_16V4Z MDB0 MAB0
H15 DQB_0 MAB_0 H2
2 MDB1 MAB1
G14 H3

2
Part 3 of 7 MDB2 DQB_1 MAB_1 MAB2
E14 DQB_2 MAB_2 J3
MDB3 D14 J5 MAB3
MDA0 MAA0 MDB4 DQB_3 MAB_3 MAB4
P27 DQA_0 MAA_0 C27 H12 DQB_4 MAB_4 J4
MDA1 P28 B28 MAA1 MDB5 G12 J6 MAB5
MDA2 DQA_1 MAA_1 MAA2 MDB6 DQB_5 MAB_5 MAB6
P31 DQA_2 MAA_2 B27 F12 DQB_6 MAB_6 G5
MDA3 P32 G26 MAA3 MDB7 D10 J9 MAB7
MDA4 DQA_3 MAA_3 MAA4 MDB8 DQB_7 MAB_7 MAB8
M27 F27 B13 F3

MEMORY INTERFACE B
MDA5 DQA_4 MAA_4 MAA5 MDB9 DQB_8 MAB_8 MAB9
K29 DQA_5 MAA_5 E27 C12 DQB_9 MAB_9 F4
MDA6 K31 D27 MAA6 MDB10 B12 J1 MAB10
MDA7 DQA_6 MAA_6 MAA7 MDB11 DQB_10 MAB_10 MAB11
K32 DQA_7 MAA_7 J27 B11 DQB_11 MAB_11 J2
MDA8 M33 E29 MAA8 MDB12 C9 J7 MAB12
MDA9 DQA_8 MAA_8 MAA9
Close to pin A13, B14 MDB13 DQB_12 MAB_A12 BB2
MEMORY INTERFACE A

M34 DQA_9 MAA_9 C30 B9 DQB_13 MAB_BA2 F1

MDA10 L34 E26 MAA10 MDB14 A9 G2 BB0
MDA11 DQA_10 MAA_10 MAA11 MDB15 DQB_14 MAB_BA0 BB1
L35 DQA_11 MAA_11 A27 B8 DQB_15 MAB_BA1 G3
MDA12 J33 G27 MAA12 MDB16 J10
C MDA13 DQA_12 MAA_A12 BA2 MDB17 DQB_16 DQMB#0 C
J34 DQA_13 MAA_BA2 D26 H10 DQB_17 DQMBb_0 D12
MDA14 H33 C28 BA0 MDB18 F10 C10 DQMB#1
MDA15 DQA_14 MAA_BA0 BA1 +1.8VS +1.8VS MDB19 DQB_18 DQMBb_1 DQMB#2
H34 DQA_15 MAA_BA1 B29 D9 DQB_19 DQMBb_2 E7
MDA16 K27 MDB20 G7 C6 DQMB#3
MDA17 DQA_16 DQMA#0 MDB21 DQB_20 DQMBb_3 DQMB#4
J29 DQA_17 DQMAb_0 M29 G6 DQB_21 DQMBb_4 P3

1
MDA18 J30 K33 DQMA#1 MDB22 F6 R4 DQMB#5
MDA19 DQA_18 DQMAb_1 DQMA#2 RV40 RV41 MDB23 DQB_22 DQMBb_5 DQMB#6
J31 DQA_19 DQMAb_2 G30 D6 DQB_23 DQMBb_6 W3
MDA20 F29 E33 DQMA#3 100_0402_1% 100_0402_1% MDB24 C8 V8 DQMB#7
MDA21 DQA_20 DQMAb_3 DQMA#4 MDB25 DQB_24 DQMBb_7
F32 DQA_21 DQMAb_4 C22 C7 DQB_25
MDA22 D30 H21 DQMA#5 MDB26 B7 J14 QSB0

2
MDA23 DQA_22 DQMAb_5 DQMA#6 +MVREFSB MDB27 DQB_26 QSB_0 QSB1
D32 DQA_23 DQMAb_6 C17 A7 DQB_27 QSB_1 B10
MDA24 G33 G17 DQMA#7 +MVREFDB MDB28 B5 F9 QSB2
MDA25 DQA_24 DQMAb_7 MDB29 DQB_28 QSB_2 QSB3
G34 DQA_25 A5 DQB_29 QSB_3 B6

1
MDA26 G35 M30 QSA0 1 1 MDB30 C4 P2 QSB4

read strobe
DQA_26 QSA_0 DQB_30 QSB_4

1
MDA27 F34 K34 QSA1 CV178 RV43 MDB31 B4 P8 QSB5
MDA28 DQA_27 QSA_1 QSA2 RV42 0.1U_0402_16V4Z 100_0402_1% CV179 MDB32 DQB_31 QSB_5 QSB6
D34 DQA_28 QSA_2 G31 M3 DQB_32 QSB_6 W2
MDA29 C34 E34 QSA3 100_0402_1% 0.1U_0402_16V4Z MDB33 M2 V6 QSB7
MDA30 DQA_29 QSA_3 QSA4 2 2 MDB34 DQB_33 QSB_7
C35 B22 N2

2
MDA31 DQA_30 QSA_4 QSA5 MDB35 DQB_34 QSB#0
B34 F21 N1 H14
read strobe

2
MDA32 DQA_31 QSA_5 QSA6 MDB36 DQB_35 QSB_0B QSB#1
C24 DQA_32 QSA_6 B17 R3 DQB_36 QSB_1B A10
MDA33 B24 D17 QSA7 MDB37 R2 E9 QSB#2
DQA_33 QSA_7 DQB_37 QSB_2B

write strobe
MDA34 B23 MDB38 T3 A6 QSB#3
MDA35 DQA_34 QSA#0 MDB39 DQB_38 QSB_3B QSB#4
A23 DQA_35 QSA_0B M31 T2 DQB_39 QSB_4B P1
MDA36 C21 K35 QSA#1 MDB40 M8 P7 QSB#5
MDA37 DQA_36 QSA_1B QSA#2 MDB41 DQB_40 QSB_5B QSB#6
B21 DQA_37 QSA_2B G32 M7 DQB_41 QSB_6B W1
write strobe

MDA38 C20 E35 QSA#3 MDB42 P5 V5 QSB#7

MDA39 DQA_38 QSA_3B QSA#4 MDB43 DQB_42 QSB_7B
B20 DQA_39 QSA_4B A22 P4 DQB_43
MDA40 J22 E21 QSA#5 MDB44 R9 D2
DQA_40 QSA_5B DQB_44 ODTB0 ODTB0 23
MDA41 H22 A17 QSA#6 MDB45 R8 K5
B DQA_41 QSA_6B DQB_45 ODTB1 ODTB1 24 B
MDA42 F22 E17 QSA#7 MDB46 R6
MDA43 DQA_42 QSA_7B MDB47 DQB_46
D21 DQA_43 U4 DQB_47 CLKB0 A3 CLKB0 23
MDA44 J19 C31 MDB48 U3 K1
DQA_44 ODTA0 ODTA0 21 DQB_48 CLKB1 CLKB1 24
MDA45 G19 C25 MDB49 U2
DQA_45 ODTA1 ODTA1 22 DQB_49
MDA46 F19 MDB50 U1 B3
DQA_46 DQB_50 CLKB0b CLKB0# 23
MDA47 D19 A33 MDB51 V2 K2
DQA_47 CLKA0 CLKA0 21 DQB_51 CLKB1b CLKB1# 24
MDA48 C19 A26 MDB52 Y3
DQA_48 CLKA1 CLKA1 22 DQB_52
MDA49 B19 MDB53 Y2 D3
DQA_49 DQB_53 RASB0b RASB#0 23
MDA50 A19 B33 MDB54 AA2 K7
DQA_50 CLKA0b CLKA0# 21 DQB_54 RASB1b RASB#1 24
MDA51 B18 B26 MDB55 AA1
DQA_51 CLKA1b CLKA1# 22 DQB_55
MDA52 C16 MDB56 U9 C1
DQA_52 DQB_56 CASB0b CASB#0 23
MDA53 B16 A31 MDB57 U7 K4
DQA_53 RASA0b RASA#0 21 DQB_57 CASB1b CASB#1 24
MDA54 C15 D24 MDB58 U6
DQA_54 RASA1b RASA#1 22 DQB_58
MDA55 A15 MDB59 V4 E1
DQA_55 DQB_59 CSB0b_0 CSB0# 23
MDA56 H18 C32 MDB60 W9 E2
DQA_56 CASA0b CASA#0 21 DQB_60 CSB0b_1
MDA57 F18 H26 MDB61 W7
DQA_57 CASA1b CASA#1 22 DQB_61
MDA58 E18 MDB62 W6 L3
DQA_58 DQB_62 CSB1b_0 CSB1# 24
MDA59 D18 A30 MDB63 W4 M4
DQA_59 CSA0b_0 CSA0# 21 DQB_63 CSB1b_1
MDA60 J17 B30
MDA61 DQA_60 CSA0b_1 +MVREFDB
G15 DQA_61 B14 MVREFDB CKEB0 E3 CKEB0 23
MDA62 E15 G24 +MVREFSB A13 K8
DQA_62 CSA1b_0 CSA1# 22 MVREFSB CKEB1 CKEB1 24
MDA63 D15 H24
DQA_63 CSA1b_1
1 2 AM30 TESTEN WEB0b F2 WEB#0 23
+MVREFDA N35 B31 RV44 1 2 1K_0402_5% AA8 M6
MVREFDA CKEA0 CKEA0 21 TEST_MCLK WEB1b WEB#1 24
+MVREFSA N34 F24 RV45 1 2 4.7K_0402_5% AA7
MVREFSA CKEA1 CKEA1 22 TEST_YCLK
RV46 1 2 4.7K_0402_5% AA5 AA4
RV47 240_0402_1% AH19 MEMTEST DRAM_RST
WEA0b C29 WEA#0 21 PLLTEST
AM34 NC_1 WEA1b D22 WEA#1 22
216-0683008 A11 M86-M_BGA880
A A

216-0683008 A11 M86-M_BGA880

M86R1@ Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 20 of 58
5 4 3 2 1
 5 4 3 2 1

BA[2..0]
BA[2..0] 20,22 Close to U6
Close to U7
MAA[12..0]
MAA[12..0] 20,22 +1.8VS
+1.8VS
MDA[31..0] 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
MDA[31..0] 20
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
1 1 1 1 1 1 1 1
DQMA#[7..0] 1 1 1 1 1 1 1 1
DQMA#[7..0] 20,22
D CV180 CV181 CV182 CV183 CV184 CV185 CV186 CV187 D
CV188 CV189 CV190 CV191 CV192 CV193 CV194 CV195
QSA[7..0] 2 2 2 2 2 2 2 2
QSA[7..0] 20,22 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M
QSA#[7..0] 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
QSA#[7..0] 20,22

Bit swap
U6
BA0 L2 B9 MDA7
BA1 BA0 DQ15 MDA5 U7
L3 BA1 DQ14 B1 Group swap
D9 MDA3 BA0 L2 B9 MDA29
MAA12 DQ13 MDA4 BA1 BA0 DQ15 MDA27
R2 A12 DQ12 D1 Group0 L3 BA1 DQ14 B1
MAA11 P7 D3 MDA0 D9 MDA31
MAA10 A11 DQ11 MDA2 MAA12 DQ13 MDA24
M2 A10/AP DQ10 D7 R2 A12 DQ12 D1 Group3
MAA9 P3 C2 MDA1 MAA11 P7 D3 MDA26
MAA8 A9 DQ9 MDA6 MAA10 A11 DQ11 MDA30
P8 A8 DQ8 C8 M2 A10/AP DQ10 D7
MAA7 P2 F9 MDA18 MAA9 P3 C2 MDA25
MAA6 A7 DQ7 MDA19 MAA8 A9 DQ9 MDA28
N7 A6 DQ6 F1 P8 A8 DQ8 C8
MAA5 N3 H9 MDA16 MAA7 P2 F9 MDA11
MAA4 A5 DQ5 MDA21 MAA6 A7 DQ7 MDA12
N8 A4 DQ4 H1 Group2 N7 A6 DQ6 F1
MAA3 N2 H3 MDA22 MAA5 N3 H9 MDA14
MAA2 A3 DQ3 MDA17 MAA4 A5 DQ5 MDA8
M7 A2 DQ2 H7 N8 A4 DQ4 H1 Group1
C MAA1 M3 G2 MDA23 MAA3 N2 H3 MDA10 C
MAA0 A1 DQ1 MDA20 MAA2 A3 DQ3 MDA13
M8 A0 DQ0 G8 M7 A2 DQ2 H7
MAA1 M3 G2 MDA9
MAA0 A1 DQ1 MDA15
M8 A0 DQ0 G8
CLKA0# K8 A9 +1.8VS
CLKA0 CK VDDQ1
J8 CK VDDQ2 C1
C3 CLKA0# K8 A9 +1.8VS
VDDQ3 CLKA0 CK VDDQ1
20 CKEA0 K2 CKE VDDQ4 C7 J8 CK VDDQ2 C1
VDDQ5 C9 VDDQ3 C3
E9 CKEA0 K2 C7
VDDQ6 CKE VDDQ4
VDDQ7 G1 VDDQ5 C9
20 CSA0# L8 CS VDDQ8 G3 VDDQ6 E9
VDDQ9 G7 VDDQ7 G1
K3 G9 CSA0# L8 G3
20 WEA#0 WE VDDQ10 CS VDDQ8
VDDQ9 G7
K7 A1 WEA#0 K3 G9
20 RASA#0 RAS VDD1 WE VDDQ10
VDD2 E1
L7 J9 RASA#0 K7 A1
20 CASA#0 CAS VDD3 RAS VDD1
VDD4 M9 VDD2 E1
DQMA#2 F3 R1 CASA#0 L7 J9
DQMA#0 LDM VDD5 CAS VDD3
B3 UDM VDD4 M9
J1 0.1U_0402_16V4Z +1.8VS DQMA#1 F3 R1
VDDL DQMA#3 LDM VDD5
VSSDL J7 1 1 B3 UDM
K9 J1 0.1U_0402_16V4Z +1.8VS
20 ODTA0 ODT VDDL
CV196 CV197 J7 1 1
ODTA0 VSSDL
K9 ODT
QSA2 2 2 1U_0402_6.3V4Z CV198 CV199
F7 LDQS
+1.8VS QSA#2 E8 A7
LDQS VSSQ1 QSA1 2 2 1U_0402_6.3V4Z
VSSQ2 B2 F7 LDQS
B +1.8VS QSA#1 B
VSSQ3 B8 E8 LDQS VSSQ1 A7
1

VSSQ4 D2 VSSQ2 B2
RV48 QSA0 B7 D8 B8
UDQS VSSQ5 VSSQ3

1
4.99K_0402_1% QSA#0 A8 E7 D2
UDQS VSSQ6 RV49 QSA3 VSSQ4
VSSQ7 F2 B7 UDQS VSSQ5 D8
F8 4.99K_0402_1% QSA#3 A8 E7
2

+VRAM_REF1 VSSQ8 UDQS VSSQ6

J2 VREF VSSQ9 H2 VSSQ7 F2
H8 F8

2
VSSQ10 VSSQ8
1

1 A2 CLKA0# +VRAM_REF2 J2 H2
NC#A2 20 CLKA0# VREF VSSQ9
RV50 E2 A3 H8
NC#E2 VSS1 VSSQ10

1
4.99K_0402_1% BA2 L1 E3 1 A2
NC#L1 VSS2 CLKA0 RV51 NC#A2
R3 NC#R3 VSS3 J3 20 CLKA0 E2 NC#E2 VSS1 A3
2 4.99K_0402_1% BA2
R7 N1 L1 E3
2

CV200 NC#R7 VSS4 NC#L1 VSS2

R8 NC#R8 VSS5 P9 R3 NC#R3 VSS3 J3
0.1U_0402_16V4Z 2
R7 N1

2
RV52 RV53 NC#R7 VSS4
R8 NC#R8 VSS5 P9
HYB18T256161BF-25 56_0402_5% 56_0402_5% CV201
@ 0.1U_0402_16V4Z
HYB18T256161BF-25
Add BA2 for 64M*16 VRAM @
Add BA2 for 64M*16 VRAM
CV202
470P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 21 of 58
5 4 3 2 1
 5 4 3 2 1

Close to U8 Close to U9
BA[2..0]
BA[2..0] 20,21 +1.8VS +1.8VS

MAA[12..0] 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

MAA[12..0] 20,21

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MDA[63..32]
MDA[63..32] 20
CV203 CV204 CV205 CV206 CV207 CV208 CV209 CV210 CV211 CV212 CV213 CV214 CV215 CV216 CV217 CV218

DQMA#[7..0] 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DQMA#[7..0] 20,21
10U_0603_6.3V6M 10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D QSA[7..0] D
QSA[7..0] 20,21

QSA#[7..0]
QSA#[7..0] 20,21

U9
U8 BA0 L2 B9 MDA59
BA0 MDA47 BA1 BA0 DQ15 MDA60
L2 BA0 DQ15 B9 L3 BA1 DQ14 B1
BA1 L3 B1 MDA41 D9 MDA57
BA1 DQ14 MDA44 MAA12 DQ13 MDA62
DQ13 D9 R2 A12 DQ12 D1 Group7
MAA12 R2 D1 MDA40 Group5 MAA11 P7 D3 MDA63
MAA11 A12 DQ12 MDA43 MAA10 A11 DQ11 MDA56
P7 A11 DQ11 D3 M2 A10/AP DQ10 D7
MAA10 M2 D7 MDA45 MAA9 P3 C2 MDA61
MAA9 A10/AP DQ10 MDA42 MAA8 A9 DQ9 MDA58
P3 A9 DQ9 C2 P8 A8 DQ8 C8
MAA8 P8 C8 MDA46 MAA7 P2 F9 MDA50
MAA7 A8 DQ8 MDA36 MAA6 A7 DQ7 MDA52
P2 A7 DQ7 F9 N7 A6 DQ6 F1
MAA6 N7 F1 MDA35 MAA5 N3 H9 MDA48
MAA5 A6 DQ6 MDA39 MAA4 A5 DQ5 MDA53
C N3 A5 DQ5 H9 N8 A4 DQ4 H1 Group6 C
MAA4 N8 H1 MDA32 Group4 MAA3 N2 H3 MDA55
MAA3 A4 DQ4 MDA33 MAA2 A3 DQ3 MDA51
N2 A3 DQ3 H3 M7 A2 DQ2 H7
MAA2 M7 H7 MDA38 MAA1 M3 G2 MDA54
MAA1 A2 DQ2 MDA34 MAA0 A1 DQ1 MDA49
M3 A1 DQ1 G2 M8 A0 DQ0 G8
MAA0 M8 G8 MDA37
A0 DQ0
CLKA1# K8 A9 +1.8VS
CLKA1# CLKA1 CK VDDQ1
K8 CK VDDQ1 A9 +1.8VS J8 CK VDDQ2 C1
CLKA1 J8 C1 C3
CK VDDQ2 CKEA1 VDDQ3
VDDQ3 C3 K2 CKE VDDQ4 C7
20 CKEA1 K2 CKE VDDQ4 C7 VDDQ5 C9
VDDQ5 C9 VDDQ6 E9
VDDQ6 E9 VDDQ7 G1
G1 CSA1# L8 G3
VDDQ7 CS VDDQ8
20 CSA1# L8 CS VDDQ8 G3 VDDQ9 G7
G7 WEA#1 K3 G9
VDDQ9 WE VDDQ10
20 WEA#1 K3 WE VDDQ10 G9
RASA#1 K7 A1
RAS VDD1
20 RASA#1 K7 RAS VDD1 A1 VDD2 E1
E1 CASA#1 L7 J9
VDD2 CAS VDD3
20 CASA#1 L7 CAS VDD3 J9 VDD4 M9
M9 DQMA#6 F3 R1
DQMA#4 VDD4 1.1 PV Change DQMA#7 LDM VDD5
F3 LDM VDD5 R1 B3 UDM
DQMA#5 B3 J1 0.1U_0402_16V4Z +1.8VS
1.1 PV Change UDM 0.1U_0402_16V4Z VDDL
VDDL J1 +1.8VS VSSDL J7 1 1
J7 1 1 ODTA1 K9
VSSDL ODT CV221 CV222
20 ODTA1 K9 ODT CV219 CV220
B 1.1 PV Change QSA6 2 2 1U_0402_6.3V4Z B
F7 LDQS
QSA4 2 2 1U_0402_6.3V4Z QSA#6
F7 LDQS E8 LDQS VSSQ1 A7
+1.8VS 1.1 PV Change QSA#4 E8 A7 +1.8VS B2
LDQS VSSQ1 VSSQ2
VSSQ2 B2 VSSQ3 B8

1
VSSQ3 B8 VSSQ4 D2
1

D2 RV55 QSA7 B7 D8
RV54 QSA5 VSSQ4 4.99K_0402_1% QSA#7 UDQS VSSQ5
B7 UDQS VSSQ5 D8 A8 UDQS VSSQ6 E7
4.99K_0402_1% QSA#5 A8 E7 F2
UDQS VSSQ6 VSSQ7
F2 F8

2
VSSQ7 +VRAM_REF4 VSSQ8
F8 J2 H2
2

+VRAM_REF3 VSSQ8 VREF VSSQ9

J2 VREF VSSQ9 H2 VSSQ10 H8

1
VSSQ10 H8 1 A2 NC#A2
1

1 A2 RV57 E2 A3
RV56 NC#A2 CLKA1# 4.99K_0402_1% BA2 NC#E2 VSS1
E2 NC#E2 VSS1 A3 20 CLKA1# L1 NC#L1 VSS2 E3
4.99K_0402_1% BA2 L1 E3 R3 J3
NC#L1 VSS2 2 NC#R3 VSS3
R3 J3 R7 N1

2
2 NC#R3 VSS3 CLKA1 CV223 NC#R7 VSS4
R7 N1 20 CLKA1 R8 P9
2

CV224 NC#R7 VSS4 0.1U_0402_16V4Z NC#R8 VSS5

R8 NC#R8 VSS5 P9
0.1U_0402_16V4Z
Add BA2 for 64M*16 VRAM HYB18T256161BF-25
HYB18T256161BF-25 RV58 RV59 @
Add BA2 for 64M*16 VRAM @ 56_0402_5% 56_0402_5%

CV225
470P_0402_50V8J
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/11 Deciphered Date 2009/04/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 22 of 58
5 4 3 2 1
 5 4 3 2 1

BB[2..0]
BB[2..0] 20,24 Close to UV7 Close to UV8
MAB[12..0]
MAB[12..0] 20,24 +1.8VS +1.8VS

MDB[31..0] 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

MDB[31..0] 20

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DQMB#[7..0]
DQMB#[7..0] 20,24
CV226 CV227 CV228 CV229 CV230 CV231 CV232 CV233 CV234 CV235 CV236 CV237 CV238 CV239 CV240 CV241

QSB[7..0] 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D QSB[7..0] 20,24 D
10U_0603_6.3V6M 10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
QSB#[7..0]
QSB#[7..0] 20,24

UV7 UV8
BB0 L2 B9 MDB6 BB0 L2 B9 MDB25
BB1 BA0 DQ15 MDB4 BB1 BA0 DQ15 MDB28
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 MDB7 D9 MDB24 Group3
MAB12 DQ13 MDB0 MAB12 DQ13 MDB31
R2 A12 DQ12 D1 Group0 R2 A12 DQ12 D1
MAB11 P7 D3 MDB2 MAB11 P7 D3 MDB29
MAB10 A11 DQ11 MDB3 MAB10 A11 DQ11 MDB26
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
MAB9 P3 C2 MDB1 MAB9 P3 C2 MDB30
MAB8 A9 DQ9 MDB5 MAB8 A9 DQ9 MDB27
P8 A8 DQ8 C8 P8 A8 DQ8 C8
C MAB7 P2 F9 MDB19 MAB7 P2 F9 MDB8 C
MAB6 A7 DQ7 MDB17 MAB6 A7 DQ7 MDB15
N7 A6 DQ6 F1 N7 A6 DQ6 F1
MAB5 N3 H9 MDB22 MAB5 N3 H9 MDB9
MAB4 A5 DQ5 MDB16 MAB4 A5 DQ5 MDB13
N8 A4 DQ4 H1 Group2 N8 A4 DQ4 H1 Group1
MAB3 N2 H3 MDB20 MAB3 N2 H3 MDB14
MAB2 A3 DQ3 MDB18 MAB2 A3 DQ3 MDB10
M7 A2 DQ2 H7 M7 A2 DQ2 H7
MAB1 M3 G2 MDB21 MAB1 M3 G2 MDB11
MAB0 A1 DQ1 MDB23 MAB0 A1 DQ1 MDB12
M8 A0 DQ0 G8 M8 A0 DQ0 G8

CLKB0# K8 A9 +1.8VS CLKB0# K8 A9 +1.8VS

CLKB0 CK VDDQ1 CLKB0 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
VDDQ3 C3 VDDQ3 C3
K2 C7 CKEB0 K2 C7
20 CKEB0 CKE VDDQ4 CKE VDDQ4
VDDQ5 C9 VDDQ5 C9
VDDQ6 E9 VDDQ6 E9
VDDQ7 G1 VDDQ7 G1
L8 G3 CSB0# L8 G3
20 CSB0# CS VDDQ8 CS VDDQ8
VDDQ9 G7 VDDQ9 G7
K3 G9 WEB#0 K3 G9
20 WEB#0 WE VDDQ10 WE VDDQ10
K7 A1 RASB#0 K7 A1
20 RASB#0 RAS VDD1 RAS VDD1
VDD2 E1 VDD2 E1
L7 J9 CASB#0 L7 J9
20 CASB#0 CAS VDD3 CAS VDD3
VDD4 M9 VDD4 M9
DQMB#2 F3 R1 DQMB#1 F3 R1
DQMB#0 LDM VDD5 DQMB#3 LDM VDD5
B3 UDM B3 UDM
J1 0.1U_0402_16V4Z +1.8VS J1 0.1U_0402_16V4Z +1.8VS
VDDL VDDL
VSSDL J7 1 1 VSSDL J7 1 1
B ODTB0 B
20 ODTB0 K9 ODT K9 ODT
CV244 CV245 CV242 CV243

QSB2 2 2 1U_0402_6.3V4Z QSB1 2 2 1U_0402_6.3V4Z

F7 LDQS F7 LDQS
+1.8VS QSB#2 E8 A7 +1.8VS QSB#1 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
1

1
VSSQ4 D2 VSSQ4 D2
RV61 QSB0 B7 D8 RV60 QSB3 B7 D8
4.99K_0402_1% QSB#0 UDQS VSSQ5 4.99K_0402_1% QSB#3 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
VSSQ7 F2 VSSQ7 F2
F8 F8
2

2
+VRAM_REF5 VSSQ8 CLKB0# +VRAM_REF6 VSSQ8
J2 VREF VSSQ9 H2 20 CLKB0# J2 VREF VSSQ9 H2
VSSQ10 H8 VSSQ10 H8
1

1
A2 NC#A2 1 A2 NC#A2
RV63 1 E2 A3 CLKB0 RV62 E2 A3
NC#E2 VSS1 20 CLKB0 NC#E2 VSS1
4.99K_0402_1% BB2 L1 E3 4.99K_0402_1% BB2 L1 E3
CV247 NC#L1 VSS2 NC#L1 VSS2
R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
0.1U_0402_16V4Z 2 CV246
R7 N1 R7 N1
2

2
2 NC#R7 VSS4 RV64 RV65 0.1U_0402_16V4Z NC#R7 VSS4
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9
56_0402_5% 56_0402_5%

HYB18T256161BF-25 HYB18T256161BF-25

Add BA2 for 64M*16 VRAM

Add BA2 for 64M*16 VRAM
CV248
470P_0402_50V8J
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/11 Deciphered Date 2009/04/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 23 of 58
5 4 3 2 1
 5 4 3 2 1

BB[2..0]
BB[2..0] 20,23 Close to UV9 Close to UV10
MAB[12..0]
MAB[12..0] 20,23 +1.8VS +1.8VS

MDB[63..32] 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

MDB[63..32] 20

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DQMB#[7..0]
DQMB#[7..0] 20,23
CV249 CV250 CV251 CV252 CV253 CV254 CV255 CV256 CV257 CV258 CV259 CV260 CV261 CV262 CV263 CV264

QSB[7..0] 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D QSB[7..0] 20,23 D
10U_0603_6.3V6M 10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
QSB#[7..0]
QSB#[7..0] 20,23

UV9
BB0 L2 B9 MDB46 UV10
BB1 BA0 DQ15 MDB45 BB0 MDB39
L3 BA1 DQ14 B1 L2 BA0 DQ15 B9
D9 MDB47 BB1 L3 B1 MDB35
MAB12 DQ13 MDB44 BA1 DQ14 MDB32
R2 A12 DQ12 D1 Group5 DQ13 D9
MAB11 P7 D3 MDB41 MAB12 R2 D1 MDB37 Group4
MAB10 A11 DQ11 MDB43 MAB11 A12 DQ12 MDB33
M2 A10/AP DQ10 D7 P7 A11 DQ11 D3
MAB9 P3 C2 MDB40 MAB10 M2 D7 MDB36
MAB8 A9 DQ9 MDB42 MAB9 A10/AP DQ10 MDB34
P8 A8 DQ8 C8 P3 A9 DQ9 C2
MAB7 P2 F9 MDB62 MAB8 P8 C8 MDB38
C MAB6 A7 DQ7 MDB58 MAB7 A8 DQ8 MDB51 C
N7 A6 DQ6 F1 P2 A7 DQ7 F9
MAB5 N3 H9 MDB61 MAB6 N7 F1 MDB54
MAB4 A5 DQ5 MDB57 MAB5 A6 DQ6 MDB48
N8 A4 DQ4 H1 Group7 N3 A5 DQ5 H9
MAB3 N2 H3 MDB63 MAB4 N8 H1 MDB55 Group6
MAB2 A3 DQ3 MDB56 MAB3 A4 DQ4 MDB52
M7 A2 DQ2 H7 N2 A3 DQ3 H3
MAB1 M3 G2 MDB59 MAB2 M7 H7 MDB50
MAB0 A1 DQ1 MDB60 MAB1 A2 DQ2 MDB53
M8 A0 DQ0 G8 M3 A1 DQ1 G2
MAB0 M8 G8 MDB49
A0 DQ0
CLKB1# K8 A9 +1.8VS
CLKB1 CK VDDQ1 CLKB1#
J8 CK VDDQ2 C1 K8 CK VDDQ1 A9 +1.8VS
C3 CLKB1 J8 C1
VDDQ3 CK VDDQ2
20 CKEB1 K2 CKE VDDQ4 C7 VDDQ3 C3
C9 CKEB1 K2 C7
VDDQ5 CKE VDDQ4
VDDQ6 E9 VDDQ5 C9
VDDQ7 G1 VDDQ6 E9
20 CSB1# L8 CS VDDQ8 G3 VDDQ7 G1
G7 CSB1# L8 G3
VDDQ9 CS VDDQ8
20 WEB#1 K3 WE VDDQ10 G9 VDDQ9 G7
WEB#1 K3 G9
WE VDDQ10
20 RASB#1 K7 RAS VDD1 A1
E1 RASB#1 K7 A1
VDD2 RAS VDD1
20 CASB#1 L7 CAS VDD3 J9 VDD2 E1
M9 CASB#1 L7 J9
DQMB#7 VDD4 CAS VDD3
F3 LDM VDD5 R1 VDD4 M9
DQMB#5 B3 DQMB#6 F3 R1
UDM 0.1U_0402_16V4Z DQMB#4 LDM VDD5
VDDL J1 +1.8VS B3 UDM
J7 1 1 J1 0.1U_0402_16V4Z +1.8VS
VSSDL VDDL
20 ODTB1 K9 ODT VSSDL J7 1 1
B CV265 CV266 ODTB1 B
K9 ODT CV267 CV268
+1.8VS QSB7 2 2 1U_0402_6.3V4Z
F7 LDQS
QSB#7 QSB6 2 2 1U_0402_6.3V4Z
E8 LDQS VSSQ1 A7 F7 LDQS
B2 QSB#6 E8 A7
VSSQ2 LDQS VSSQ1
1

B8 +1.8VS B2
RV66 VSSQ3 VSSQ2
VSSQ4 D2 VSSQ3 B8

1
4.99K_0402_1% QSB5 B7 D8 D2
QSB#5 UDQS VSSQ5 RV67 QSB4 VSSQ4
A8 UDQS VSSQ6 E7 B7 UDQS VSSQ5 D8
F2 4.99K_0402_1% QSB#4 A8 E7
2

VSSQ7 CLKB1# UDQS VSSQ6

VSSQ8 F8 20 CLKB1# VSSQ7 F2
+VRAM_REF7 J2 H2 F8

2
VREF VSSQ9 +VRAM_REF8 VSSQ8
VSSQ10 H8 J2 VREF VSSQ9 H2
1

1 A2 CLKB1 H8
NC#A2 20 CLKB1 VSSQ10

1
RV68 E2 A3 1 A2
4.99K_0402_1% BB2 NC#E2 VSS1 RV69 NC#A2
L1 NC#L1 VSS2 E3 E2 NC#E2 VSS1 A3
R3 J3 4.99K_0402_1% BB2 L1 E3
2 NC#R3 VSS3 RV70 RV71 NC#L1 VSS2
R7 N1 R3 J3
2

CV269 NC#R7 VSS4 56_0402_5% 56_0402_5% 2 NC#R3 VSS3

R8 P9 R7 N1

2
NC#R8 VSS5 CV270 NC#R7 VSS4
R8 NC#R8 VSS5 P9
0.1U_0402_16V4Z 0.1U_0402_16V4Z
HYB18T256161BF-25
@ HYB18T256161BF-25
Add BA2 for 64M*16 VRAM @
Add BA2 for 64M*16 VRAM CV271
470P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/11 Deciphered Date 2009/04/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 24 of 58
5 4 3 2 1
 5 4 3 2 1

STRAPS PIN GPU Project VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 3,2,1,0
10K_0402_5% @
JBK00 1.0a 512M(x4) Samsung 64Mx16 1.8V SA00002MD00 0000 2 1 +1.8VS 10K_0402_5% @
RV72 2 1 +1.8VS
JBK00 1.0 256M(X4) Samsung 32Mx16 1.8V SA00002AJ10 0001 RV73
VRAM_ID0 16
VRAM_ID2 16
512M(x4) Hynix 64Mx16 1.8V 0010 1 2
M82M-XT RV74 10K_0402_5% 1 2
JBK00 1.0 256M(X4) Hynix 32Mx16 1.8V SA00002DL00 0011 @ RV75 10K_0402_5%
@
D DVPDATA JBK00 1.0 256M(X4) Qimonda 32Mx16 1.8V SA00002A600 0100 D
VRAM_ID[3:0] (23,22,21,20)
JBK00 1.0a 512M(x4) Qimonda 64Mx16 1.8V SA00002MF00 0101
JBK00 1.1 512M(x8) Samsung 32Mx16 1.8V SA00002AJ10 0110 10K_0402_5% 10K_0402_5%
2 1 +1.8VS 2 1 +1.8VS
JBK00 1.1 512M(x8) Hynix 32Mx16 1.8V SA00002DL00 0111 RV76 @ RV77 @
VRAM_ID1 16 VRAM_ID3 16
JBK00 1.1 512M(x8) Qimonda 32Mx16 1.8V SA00002A600 1000
M86M 1 2 1 2
1G(x8) Samsung 64Mx16 1.8V SA00002MD00 1001 RV78 10K_0402_5% RV79 10K_0402_5%
@ @
1G(x8) Hynix 64Mx16 1.8V 1010
1G(x8) Qimonda 64Mx16 1.8V SA00002MF00 1011

+3VS_DELAY

STRAPS PIN DESCRIPTION OF RECOMMENDED SETTING RECOMMENDED @

10K_0402_5%2 1 RV92
M8X @
GPIO_0 16
TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 0 10K_0402_5%2 1 RV93 GPIO_1 16
@
C TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLES 0 10K_0402_5%2 1 RV94 C
GPIO_5 16
BIF_DEBUG_ACCESS GPIO4 DEBUG SIGNALS MUXED OUT 0
@
BIF_GEN2_EN_A GPIO5 PCI-E 5.0GT/s or 2.5 GT/s select 0 10K_0402_5%2 1 RV95 SCS#_GPIO22 16
DEBUG_ I2C_ENABLE GPIO6 Internal use only 0 10K_0402_5%2 1 RV96 M82@ SOUT_GPIO8 16
@
BIF_AUDIO_EN VIP3 ENABLE HD AUDIO 10K_0402_5%2 1 RV97 GPIO9 = 0 (BIOS_ROM_EN = 0)
M86-M ONLY SIN_GPIO9 16

BIF_AUDIO_EN GPIO8 ENABLE HD AUDIO 10K_0402_5%2 1 RV98 GPIO[13:11] MEMORY SIZE

M82-M ONLY @
GPIO_11 16
10K_0402_5%2 1 RV99 128MB
GPIO 512@
GPIO_12 16 0 0 0
ROMIDCFG[3:0] SERIAL ROM TYPE OR MEMORY 0001 10K_0402_5%2 1 RV100 256MB
[9,13,12,11] GPIO_13 16 0 0 1
APERTURE SIZE SELECT @
10K_0402_5%1 0 1 0 64MB
2 RV101 PSYNC 16
BIF_VGA_DIS PSYNC VGA ENABLED===0 is enable 0 1 0 0 512MB
10K_0402_5%1 2 RV102 CRT_HSYNC 16,27
BIF_HDMI_EN HSYNC HDMI ENABLE 1
HSYNC for HDMI video

B B

External VGA Thermal Sensor +3VS_DELAY

+3VS

1
@ RV103 RV104@
2
CV272 4.7K_0402_5% 4.7K_0402_5%

0.1U_0402_16V4Z

2
1
UV12
1 VDD SCLK 8 SMB_EC_CK2 6,45

16 D+ 2 D+ SDATA 7 SMB_EC_DA2 6,45

CV273
1 2 3 D- ALERT# 6 THM_ALERT# 16
2200P_0402_50V7K 4 5
16 D- THERM# GND

A A
ADM1032ARMZ REEL_MSOP8

1.1 PV Modify SA010320120 to SA010320110

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/11 Deciphered Date 2009/04/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 25 of 58
5 4 3 2 1
 A B C D E

+1.2V_HT +VDDCLK_IO +3VS_CLK

R167
+3VS 1 2
R168 0_0805_5% 1 1 1 1 1 1 1 1
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C445 C446 C447 C448 C449 C450 C451
0_0805_5% 1 1 1 1 1 1 C444
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
C452 C453 C454 C455 C456 C457 2 2 2 2 2 2 2 2
22U_0805_6.3V6M
2 2 2 2 2 2
+3VS_CLK
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1
1 C458 C459 C460 C461 1

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2

CLK_XTAL_OUT

CLK_XTAL_IN

SI2:follow AMD request modify resistor value

Y2
R170 1 2 33_0402_5%
R171/R183 (value may change)
CLK_48M_USB 32
2 1
NB_OSC_14.318M_R 1 2 OSC_14M_NB
14.31818MHZ_20P_6X1430004201 R379 158_0402_1% NB_OSC_14.318M 11

+3VS_CLK
1 1 1 2 R380 RS780 1.1V 158R/90.0R
C464 C465 90.9_0402_1%
R240 1 2 @ 33_0402_5% CLK_14M_SB 30
22P_0402_50V8J 22P_0402_50V8J R220 1 2 @ 33_0402_5% MV:unmount for MP
2 2 CLK_14M_SIO 44
CLK_NBHT 11

+3VS_CLK
+3VS_CLK
CLK_NBHT# 11 NB
1 2 +3VS_CLK MV:Add for ICS CLK

CLK_XTAL_OUT
Routing the trace at least 10mil R174 8.2K_0402_5%
CLK_CPU_BCLK 6

CLK_XTAL_IN

SEL_SATA
1 2

2
27M_SEL
2 C629 @ 1U_0402_6.3V4Z 2
1 2 R186
R946 0_0402_5% @ 261_0402_1% CPU
1 2
R945 0_0402_5%

1
CLK_CPU_BCLK# 6

73

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
U10

GND

XTAL_IN

REF_1/SEL_SATA

CPU_K8_0
VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT

REF_2/SEL_27

HTT_0/66M_0
HTT_0#/66M_1

PD#

CPU_K8_0#
VSS_REF
REF_0/SEL_HTT66

VDD_REF
VDD_HTT

VSS_HTT
CLKREQ_NCARD# 1 2 +3VS_CLK
R324 8.2K_0402_5%
CLKREQ_MCARD2# 1 2
R325 8.2K_0402_5%
1 54 +3VS_CLK CLKREQ_MCARD1# 1 2
8,9,32,39 SMB_CK_CLK0 SCL VDD_CPU R326 8.2K_0402_5%
2 SDA VDD_CPU_I/O 53 +VDDCLK_IO
8,9,32,39 SMB_CK_DAT0 CLKREQ_LAN
+3VS_CLK 3 VDD_DOT VSS_CPU 52 1 2
R226 1 2 33_0402_5% 4 51 CLKREQ_NCARD# R390 8.2K_0402_5%
16 27M_CLK R228 33_0402_5% SRC_7#/27M CLKREQ_1# CLKREQ_MCARD2# CLKREQ_NCARD# 37
1 2 5 SRC_7/27M_SS CLKREQ_2# 50
16 27M_SSC CLKREQ_MCARD2# 37
6 VSS_DOT VDD_A 49 +3VS_CLK
7 SRC_5# VSS_A 48
8 SRC_5 VSS_SATA 47
PA_RS7X0A1 11 CLK_SBLINK_BCLK# 9 SRC_4# SRC_6/SATA 46 CLK_SBSRC_BCLK 30 PA_RS7X0A1
SB LINK 11 CLK_SBLINK_BCLK 10 SRC_4 SRC_6#/SATA# 45 CLK_SBSRC_BCLK# 30 SB SRC
11 VSS_SRC VDD_SATA 44 +3VS_CLK
+VDDCLK_IO 12 43 CLKREQ_MCARD1#
VDD_SRC_IO CLKREQ_3# CLKREQ_MCARD1# 37
37 CLK_PCIE_MCARD1# 13 SRC_3# CLKREQ_4# 42
MiniCard_1 37 CLK_PCIE_MCARD1 14 SRC_3 SB_SRC_SLOW# 41 1 2 +3VS_CLK
15 40 R372 10K_0402_5%
37 CLK_PCIE_MCARD2# SRC_2# SB_SRC_0
MiniCard_2 37 CLK_PCIE_MCARD2 16 SRC_2 SB_SRC_0# 39
+3VS_CLK 17 VDD_SRC VDD_SB_SRC 38 +3VS_CLK
+VDDCLK_IO 18 VDD_SRC_IO VDD_SB_SRC_IO 37 +VDDCLK_IO

VDD_ATIG_IO

VSS_SB_SRC
3 3

ATIGCLK_2#

ATIGCLK_1#

ATIGCLK_0#
CLKREQ_0#

SB_SRC_1#
ATIGCLK_2

ATIGCLK_1

ATIGCLK_0

SB_SRC_1
VDD_ATIG
VSS_ATIG
VSS_SRC
SRC_1#

SRC_0#
SRC_1

SRC_0

+3VS_CLK
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
2

SLG8SP626VTR_QFN72_10x10
R179
@ 8.2K_0402_5% SI2: Use new version CLK gen
1

SEL_SATA +3VS_CLK
+3VS_CLK
+VDDCLK_IO
2

R181 NB CLOCK INPUT TABLE

NBGFX_CLK 11
8.2K_0402_5% R180 NB GFX
NBGFX_CLK# 11
8.2K_0402_5% NB CLOCKS RX780 RS780
CLK_PCIE_VGA 15
1

VGA chip(Dis) HT_REFCLKP

CLK_PCIE_VGA# 15
1

27M_SEL 100M DIFF 100M DIFF

HT_REFCLKN 100M DIFF 100M DIFF
CLK_PCIE_MCARD0 38
Card reader REFCLK_P
CLK_PCIE_MCARD0# 38
1 configure as SATA output CLKREQ_LAN 14M SE (1.8V) 14M SE (1.1V)
CLKREQ_LAN 36
SEL_SATA 1 * configure as 27M and 27M_SS output REFCLK_N NC vref
CLK_PCIE_LAN 36
0 * configure as normal SRC(SRC_6) output 27M_SEL GLAN
CLK_PCIE_LAN# 36
* default 0 configure as SRC_7 output GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
* default New Card
CLK_PCIE_NCARD 37 NC or 100M DIFF OUTPUT
GPP_REFCLK 100M DIFF
4 CLK_PCIE_NCARD# 37 4
GPPSB_REFCLK 100M DIFF 100M DIFF

Use voltage divider resistor R379 & R380 to pull low

1 configure as single-ended 66MHz output

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
NB_OSC_14.318M
0* configure as differential 100MHz output
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
* default AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 26 of 58
A B C D E
 A B C D E

CRT CONNECTOR
1 1
+5VS +R_CRT_VCC +CRT_VCC
D36 F2
2 1 1 2

1
D35 D37 D34 1
RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z
+3VS 2
DAN217_SC59 DAN217_SC59DAN217_SC59

3
@ @ @

MV: modify bead to NBQ100505T-800Y-N JP6

6
L47 11
RED 1 2 RED_L 1
16 RED
NBQ100505T-800Y-N_0402 7
L48 D_DDCDATA 12
GREEN 1 2 GREEN_L 2
16 GREEN
NBQ100505T-800Y-N_0402 8
L49 HSYNC 13
BLUE 1 2 BLUE_L 3
16 BLUE
NBQ100505T-800Y-N_0402 +CRT_VCC 9

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
VSYNC 14

75_0402_1%

75_0402_1%

75_0402_1%

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
1 1 1 4

1
R214 R211 R217 1 1 1 10
C471 C859 C469 D_DDCCLK 15
C858 5
2 2 2 C476 C472
2 2 2
16 GND

2
RED_L 47 17 GND
2 2
GREEN_L 47 SUYIN_070546FR015S265ZR
CONN@
BLUE_L 47
SI:change CRT Conn.

1.1 PV MODIFY

SI2:change pull high from 6.8K to 2K ohm

+3VS_DELAY

+CRT_VCC
+CRT_VCC
1

1 2
2

R237 R238 +3VS C473

5
1
4.7K_0402_5% 4.7K_0402_5% R100 R218 0.1U_0402_16V4Z
@ @ 2K_0402_5% 2K_0402_5%

P
OE#
5

2 4 D_HSYNC 1 2 HSYNC
16,25 CRT_HSYNC
2

A Y L84 10_0402_5%
1

G
4 3 D_DDCDATA U14
16 VGA_DDC_DAT D_DDCDATA 47

3
3 Q10B SN74AHCT1G125GW_SOT353-5 VSYNC 3
1 2
2N7002DW-7-F_SOT363-6 L83 10_0402_5%

10P_0402_50V8J

10P_0402_50V8J
+CRT_VCC
1 1
+3VS
1 2 C474 C470
C477 @ @
2

5
1
0.1U_0402_16V4Z 2 2
M82-S DDC3 & DDC4 is 5V tolerance

P
OE#
1 6 D_DDCCLK 2 4 D_VSYNC
16 VGA_DDC_CLK D_DDCCLK 47 16 CRT_VSYNC A Y

G
1 1 U13
Q10A SN74AHCT1G125GW_SOT353-5

3
2N7002DW-7-F_SOT363-6 C857 C856
@ @
RS780 DAC_SCL & SDA is 5V tolerance 470P_0402_50V8J 2 2 470P_0402_50V8J D_HSYNC 47

D_VSYNC 47

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 27 of 58
A B C D E
 A B C D E

+LCDVDD

+5VALW

1
R225

2
470_0805_5%
R224
1M_0402_5% +3VS

3 2
1 1
80mil

3
S
Q144B R222 G
2N7002DW-7-F_SOT363-6 5 1 2 2 Q43
100K_0402_5% SI2301BDS-T1-E3_SOT23-3

6
D
2

1
80mil
2 C863 +LCDVDD
17 VGA_ENVDD Q144A 1000P_0402_50V7K

2
1
2N7002DW-7-F_SOT363-6

1
R276 1
2.2K_0402_5%
C487 C491
4.7U_0805_10V4Z 0.1U_0402_16V4Z

1
2

2 2

+LCDVDD INVPWR_B+

B+ L44 INVPWR_B+
2 1
C479 C480 FBMA-L11-201209-221LMA30T_0805
<BOM Structure>
+3VS

680P_0402_50V7K

680P_0402_50V7K
1

1
LVDS CONN LVDS_ACLK- 1 2
@ C868 680P_0402_50V7K

2
C481 2 JP7 LVDS_ACLK+ 1 2
1 2 @ C869 680P_0402_50V7K
D22 1 2 LVDS_A2- 17

680P_0402_50V7K
3 3 4 4 LVDS_A2+ 17
+5VALW 4 2 USB20_P5 5 6 DMIC_DAT 1 2
VIN IO1 5 6 LVDS_A1- 17
1
7 8 @C923
@ C923 220P_0402_50V7K
7 8 LVDS_A1+ 17
USB20_N5 3 1 9 10 DMIC_CLK 1 2
IO2 GND 9 10 LVDS_A0- 17
11 12 @C924
@ C924 220P_0402_50V7K
LVDS_A0+ 17
2

@ PRTR5V0U2X_SOT143-4 USB20_P5 11 12 LVDS_ACLK-

32 USB20_P5 13 13 14 14 LVDS_ACLK- 17
32 USB20_N5 USB20_N5 15 16 LVDS_ACLK+ SI2: Add 220P for EMI
15 16 LVDS_ACLK+ 17
17 17 18 18
19 19 20 20
21 21 22 22
LVDS_BCLK+ 23 24 DMIC_DAT
17 LVDS_BCLK+ 23 24 DMIC_DAT 40
2 1 LVDS_BCLK+ LVDS_BCLK- 25 26 DMIC_CLK
17 LVDS_BCLK- 25 26 DMIC_CLK 40
680P_0402_50V7K C870 @ 27 28 1 2 +5VS SI: Change R491 to 0805 size
LVDS_BCLK- 27 28 INVT_PWM 100_0805_5% R491
2 1 17 LVDS_B0+ 29 29 30 30 INV_PWM 45
3 680P_0402_50V7K C871 @ BKOFF# 3
17 LVDS_B0- 31 31 32 32 BKOFF# 45
33 34 DAC_BRIG
17 LVDS_B1+ 33 34 DAC_BRIG 45
17 LVDS_B1- 35 35 36 36 +USB_CAM
37 38 LCD_DDC_CLK
17 LVDS_B2+ 37 38 LCD_DDC_CLK 16
39 40 LCD_DDC_DAT
17 LVDS_B2- 39 40 LCD_DDC_DAT 16
SI: Add +5VS jumper 41 GND GND 42

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
1 1 1

680P_0402_50V7K

680P_0402_50V7K
ACES_88242-4001

C482

C483

C628
CONN@

C866

C867
+5VALW +5VS 2 2 2

2
+3VS
@ @
1

BKOFF# 1 2
PJP4 SI:Change to Richtek parts +USB_CAM @ 4.7K_0402_5% R483
PAD-OPEN 2x2m PJP7 PV: mount for EMI
PAD-OPEN 2x2m @ 215K_0402_1% LCD_DDC_CLK 1 2
4.7K_0402_5% @ R274
U54
1
2

1 5 LCD_DDC_DAT 1 @ 2
VIN VOUT R891 4.7K_0402_5% R275
2
2

2 GND
C720 R16 2
2

10U_0805_10V4Z 0_0402_5% 3 4
1 EN BP C719
1

RT9193-39GB_SOT23-5 1 10U_0805_10V4Z
1

R892 1
31 CAM_SHDN# 2 1
R17 @ 0_0402_5% C511 100K_0402_1%
0.1U_0402_16V4Z @
2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 28 of 58
A B C D E
 A B C D E

1.1 PV MODIFY

SI2:change pull high from 6.8K to 2K ohm

+3VS_DELAY +HDMI_5V_OUT

+HDMI_5V_OUT

2
HDMI_HPD +3VS
C851 2 R176 R209 R210 R236
1 0.1U_0402_16V4Z 2 1 @ 4.7K_0402_5% @ 4.7K_0402_5% 2K_0402_5% 2K_0402_5% 1
+3VS

2
R615 R628 2 C850
5
1

5
2.2K_0402_5% 100K_0402_5% 0.1U_0402_16V4Z

1
1 P
OE# HDMI_SDATA
2 A Y 4 HPD 16 16 HDMIDAT_VGA 4 3
1

1
G

U39
SN74AHCT1G125GW_SOT353-5 Q139B
3

2N7002DW-7-F_SOT363-6

+3VS

2
1 6 HDMI_SCLK
16 HDMICLK_VGA

Q139A
2N7002DW-7-F_SOT363-6

C:Chg. PN to SB770020010.

2 2

MP:Update D10 to meet HDMI.

SI:Add R6161~R624 for EMI requset
D10
HDMI_CLK- 1 2 HDMI_R_CK- +5VS 2 1 +HDMI_5V_OUT
R616 0_0402_5%
RB491D_SOT23
L85
1 1 2 2 1
C468

4 3 0.1U_0402_16V4Z
4 3 2
@ WCM-2012-900T_0805
HDMI_CLK+ 1 2 HDMI_R_CK+
R617 0_0402_5%

HDMI_TX0- 1 2 HDMI_R_D0-
R618 0_0402_5%
16 HDMI_CLK+_VGA
16 HDMI_CLK-_VGA
C507 1
C508 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_CLK+
HDMI_CLK- L86 HDMI Connector
1 1 2 2

C655 1 2 0.1U_0402_16V7K HDMI_TX0+ HDMI_R_CK+ 1 2 +HDMI_5V_OUT JP8

16 HDMI_TX0+_VGA
C675 1 2 0.1U_0402_16V7K HDMI_TX0- 4 3 R307 499_0402_1% 18
3 16 HDMI_TX0-_VGA 4 3 +5V 3
HDMI_R_CK- 1 2 HDMI_SDATA 16 13
@ WCM-2012-900T_0805 R315 499_0402_1% HDMI_SCLK SDA CEC
15 SCL Reserved 14
C804 1 2 0.1U_0402_16V7K HDMI_TX1+ HDMI_TX0+ 1 2 HDMI_R_D0+ HDMI_R_D1- 1 2 HDMI_HPD 19
16 HDMI_TX1+_VGA HP_DET
C827 1 2 0.1U_0402_16V7K HDMI_TX1- R619 0_0402_5% R297 499_0402_1% 2
16 HDMI_TX1-_VGA GND
HDMI_R_D1+ 1 2 HDMI_R_CK- 12 5
R173 499_0402_1% HDMI_R_CK+ CK- GND
10 CK+ GND 8
C852 1 2 0.1U_0402_16V7K HDMI_TX2+ HDMI_R_D0- 1 2 HDMI_R_D0- 9 11
16 HDMI_TX2+_VGA D0- GND
C853 1 2 0.1U_0402_16V7K HDMI_TX2- HDMI_TX1- 1 2 HDMI_R_D1- R304 499_0402_1% HDMI_R_D0+ 7 20
16 HDMI_TX2-_VGA D0+ GND
R620 0_0402_5% HDMI_R_D0+ 1 2 HDMI_R_D1- 6 21
R172 499_0402_1% HDMI_R_D1+ D1- GND
4 D1+ GND 22
L87 HDMI_R_D2+ 1 2 HDMI_R_D2- 3 23
R141 499_0402_1% HDMI_R_D2+ D2- GND
1 1 2 2 1 D2+ DDC/CEC_GND 17
HDMI_R_D2- 1 2
R139 499_0402_1%
4 3 SUYIN_100042MR019S153ZL
4 3
@ WCM-2012-900T_0805 SI:Update
CONN@HDMI footprint

1
HDMI_TX1+ HDMI_R_D1+ D
1 2
R621 0_0402_5% +5VS 2 Q136
G 2N7002_SOT23-3

1
S

3
R490
HDMI_TX2- 1 2 HDMI_R_D2- 100K_0402_5%
R623 0_0402_5%

2
L88
1 1 2 2

4 4 3 3

@ WCM-2012-900T_0805
4 HDMI_TX2+ HDMI_R_D2+ 4
1 2
R624 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 29 of 58
A B C D E
 A B C D E

Check AMD need pull low or not

1 2 NB_RST#_R
R300 @ 8.2K_0402_5%
U15A

NB_RST#_R N2
SB700 P4
A_RST# PCICLK0
Part 1 of 5 PCICLK1 P3

PCI CLKS
C492 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
1 10 SB_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 34 1
C493 1 2 0.1U_0402_16V7K SB_RX0N_C V22 P2
10 SB_RX0N PCIE_TX0N PCICLK3 PCI_CLK3 34
C494 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4
10 SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 34
C495 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
10 SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 34
C496 1 2 0.1U_0402_16V7K SB_RX2P_C U25
10 SB_RX2P PCIE_TX2P
C497 1 2 0.1U_0402_16V7K SB_RX2N_C U24
10 SB_RX2N PCIE_TX2N
C498 1 2 0.1U_0402_16V7K SB_RX3P_C T23
10 SB_RX3P PCIE_TX3P
C499 1 2 0.1U_0402_16V7K SB_RX3N_C T22 N1
10 SB_RX3N PCIE_TX3N PCIRST#

PCI EXPRESS INTERFACE

10 SB_TX0P U22 PCIE_RX0P
10 SB_TX0N U21 PCIE_RX0N AD0 U2
10 SB_TX1P U19 PCIE_RX1P AD1 P7
10 SB_TX1N V19 PCIE_RX1N AD2 V4
10 SB_TX2P R20 PCIE_RX2P AD3 T1
10 SB_TX2N R21 PCIE_RX2N AD4 V3
10 SB_TX3P R18 PCIE_RX3P AD5 U1
10 SB_TX3N R17 PCIE_RX3N AD6 V1
AD7 V2
R305 2 1 562_0402_1% T25 T2
R306 PCIE_CALRP AD8
+PCIE_VDDR 2 1 2.05K_0402_1% T24 PCIE_CALRN AD9 W1
L53 T9
+SB_PCIEVDD AD10
+1.2V_HT 1 2 P24 PCIE_PVDD AD11 R6
BLM18PG121SN1D_0603 1 1 R7
AD12
P25 PCIE_PVSS AD13 R5
C504 C505 U8
+3VALW 10U_0805_10V4Z 1U_0402_6.3V4Z AD14
C506 AD15 U5
2 2
AD16 Y7
2 1 AD17 W8
AD18 V9
5

@ 0.1U_0402_16V4Z U16 Close to SB Y8

AD19
2 AA8
P

B PLT_RST# AD20
Y 4 PLT_RST# 11,14,15,36,37,38,44,45 AD21 Y4
NB_RST#_R 1 Y3
A AD22
G

2 @ NC7SZ08P5X_NL_SC70-5 PCI_AD23 2
AD23 Y2 PCI_AD23 34
AA2 PCI_AD24
PCI_AD24 34
3

AD24 PCI_AD25
AD25 AB4 PCI_AD25 34
N25 AA1 PCI_AD26
26 CLK_SBSRC_BCLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 34
N24 AB3 PCI_AD27
26 CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27 PCI_AD27 34
2 1 AB2 PCI_AD28
AD28 PCI_AD28 34
R312 33_0402_5% K23 AC1
NB_DISP_CLKP AD29
K22 NB_DISP_CLKN AD30 AC2
AD31 AD1
M24 W2

PCI INTERFACE
NB_HT_CLKP CBE0#
M25 NB_HT_CLKN CBE1# U7
CBE2# AA7
P17 CPU_HT_CLKP CBE3# Y1
M18 CPU_HT_CLKN FRAME# AA6
DEVSEL# W5
M23 SLT_GFX_CLKP IRDY# AA5
M22 SLT_GFX_CLKN TRDY# Y5
PAR U6
J19 GPP_CLK0P STOP# W6
J18 GPP_CLK0N PERR# W4
SERR# V7 PCI_SERR# 45
L20 GPP_CLK1P REQ0# AC3
L19 GPP_CLK1N REQ1# AD4
@ R314 20M_0402_5%
@R314 AB7
REQ2#
1 2 M19 GPP_CLK2P REQ3#/GPIO70 AE6
M20 AB6 PAD T15
GPP_CLK2N REQ4#/GPIO71
C643 GNT0# AD2

CLOCK GENERATOR
N22 GPP_CLK3P GNT1# AE4
1 2 SB_32KHI P22 AD5
GPP_CLK3N GNT2#
GNT3#/GPIO72 AC6
18P_0402_50V8J Y3 L18 AE5 PAD T16
25M_48M_66M_OSC GNT4#/GPIO73
1

4 3 AD6 PAD T17 CLK_PCI_EC 1 2 C501 1 2@ 100P_0402_25V8K

3 R389 OUT NC CLKRUN# R303 @ 100_0402_5% 3
LOCK# V5
20M_0603_5% 1 2 J21 CLK_PCI_SIO 1 2 C503 1 2@ 100P_0402_25V8K
IN NC 26 CLK_14M_SB 25M_X1
AD3 R369 @ 100_0402_5%
INTE#/GPIO33
2

32.768KHZ_12.5P_1TJS125BJ4A421P AC4
C652
2

R241 INTF#/GPIO34
INTG#/GPIO35 AE2
1 2 SB_32KHO 0_0402_5% J20 AE3 PCI_PIRQH# R967 2 1 0_0402_5%
25M_X2 INTH#/GPIO36 ACCEL_INT 39
18P_0402_50V8J
08/29 new add
1

G22 R308 1 2 22_0402_5% CLK_PCI_EC

LPCCLK0 CLK_PCI_EC 34,45
Close to SB E22 R309 1 2 22_0402_5% CLK_PCI_SIO
LPCCLK1 CLK_PCI_SIO 34,44
SB_32KHI A3 H24 R310 1 2@ 22_0402_5%
X1 LAD0 LPC_AD0 44,45 CLK_PCI_SIO2 44
LAD1 H23 LPC_AD1 44,45
LAD2 J25 LPC_AD2 44,45
J24
RTC XTAL

LAD3 LPC_AD3 44,45

LPC

SB_32KHO B3 H25
X2 LFRAME# LPC_FRAME# 44,45
LDRQ0# H22
LDRQ1#/GNT5#/GPIO68 AB8 LPC_DRQ1# 44
BMREQ#/REQ5#/GPIO65 AD7
+3VS 2 1 H_PROCHOT# V15
SERIRQ SIRQ 44,45
R319 10K_0402_5%
CPU_LDT_REQ# F23
6,11 CPU_LDT_REQ# ALLOW_LDTSTP
H_PROCHOT#
6 H_PROCHOT#
H_PWRGD
F24
F22
PROCHOT# RTCCLK C3
C2
RTC_CLK 34 STRAP PIN
6,56 H_PWRGD LDT_PG INTRUDER_ALERT# +3VL
CPU

6,11 LDT_STOP# G25 LDT_STP# VBAT B2 +SB_VBAT

G24 +SB_VBAT +RTCVCC_R +RTCVCC
6 LDT_RST# LDT_RST# +RTCBATT
RTC

R316 R317 D42

120_0402_5% 120_0402_5% 2
218S7EALA11FG_BGA528_SB700 1 2 1 2 1 R876 JBATT1
SBR1@ 1 1 3 1 2 W=20mils 1
W=20mils 1
W=20mils 2 2

2
C509 C510 DAN202U_SC70 1K_0402_5% 3
4 J1 GND 4
4

2
2 2 @ JUMP_43X39 GND
1U_0402_6.3V4Z ACES_85205-02001

1
CONN@
0.1U_0402_16V4Z

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 30 of 58
A B C D E
 A B C D E

U15B
1 1

C512 1 2 0.01U_0402_25V7K SATA_STX_DRX_P0 AD9

SB700 AA24
35 SATA_TXP0 SATA_TX0P IDE_IORDY
C513 1 2 0.01U_0402_25V7K SATA_STX_DRX_N0 AE9 Part 2 of 5 AA25
35 SATA_TXN0 SATA_TX0N IDE_IRQ
IDE_A0 Y22
35 SATA_RXN0_C AB10 SATA_RX0N IDE_A1 AB23
35 SATA_RXP0_C AC10 SATA_RX0P IDE_A2 Y23
IDE_DACK# AB24
C514 1 2 0.01U_0402_25V7K SATA_STX_DRX_P1 AE10 AD25
35 SATA_TXP1 SATA_TX1P IDE_DRQ
C515 1 2 0.01U_0402_25V7K SATA_STX_DRX_N1 AD10 AC25
35 SATA_TXN1 SATA_TX1N IDE_IOR#
IDE_IOW# AC24
35 SATA_RXN1_C AD11 SATA_RX1N IDE_CS1# Y25
35 SATA_RXP1_C AE11 SATA_RX1P IDE_CS3# Y24

C520 1 2 0.01U_0402_25V7K SATA_STX_DRX_P5 AB12 AD24

43 SATA_TXP5 SATA_TX2P IDE_D0/GPIO15
C521 1 2 0.01U_0402_25V7K SATA_STX_DRX_N5 AC12 AD23
43 SATA_TXN5 SATA_TX2N IDE_D1/GPIO16

ATA 66/100/133
IDE_D2/GPIO17 AE22
43 SATA_RXN5_C AE12 SATA_RX2N IDE_D3/GPIO18 AC22
43 SATA_RXP5_C AD12 SATA_RX2P IDE_D4/GPIO19 AD21
IDE_D5/GPIO20 AE20
C518 1 2 0.01U_0402_25V7K SATA_STX_DRX_P4 AD13 AB20
35 SATA_TXP4 SATA_TX3P IDE_D6/GPIO21
C519 1 2 0.01U_0402_25V7K SATA_STX_DRX_N4 AE13 AD19
35 SATA_TXN4 SATA_TX3N IDE_D7/GPIO22
AE19

SERIAL ATA
IDE_D8/GPIO23
35 SATA_RXN4_C AB14 SATA_RX3N IDE_D9/GPIO24 AC20
35 SATA_RXP4_C AC14 SATA_RX3P IDE_D10/GPIO25 AD20
IDE_D11/GPIO26 AE21
T24 PAD AE14 AB22
T25 PAD SATA_TX4P IDE_D12/GPIO27
AD14 SATA_TX4N IDE_D13/GPIO28 AD22
IDE_D14/GPIO29 AE23
T26 PAD AD15 AC23
T27 PAD SATA_RX4N IDE_D15/GPIO30
AE15 SATA_RX4P
2 T18 PAD 2
AB16 SATA_TX5P
T19 PAD AC16 SATA_TX5N
SPI_DI/GPIO12 G6
T20 PAD AE16 D2
T23 PAD SATA_RX5N SPI_DO/GPIO11
AD16 SATA_RX5P SPI_CLK/GPIO47 D1
F4

SPI ROM
SATA_CAL SPI_HOLD#/GPIO31
2 1 V12 SATA_CAL SPI_CS1#/GPIO32 F3
R342 1K_0402_1%
SATA_X1 Y12 U15
SATA_X1 LAN_RST#/GPIO13
ROM_RST#/GPIO14 J1
SATA_X2 AA12 SATA_X2
+3VS R343 1 2 10K_0402_5%
FANOUT0/GPIO3 M8
46 SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5 CR_WAKE# 38
+1.2V_HT M7
L54 FANOUT2/GPIO49
2 1 +PLLVDD_SATA AA11 P5 LAN_ISOLATE# 36
BLM18PG121SN1D_0603 PLLVDD_SATA FANIN0/GPIO50
FANIN1/GPIO51 P8 GSENSOR_LED# 46

SATA PWR
2 2 W12 XTLVDD_SATA FANIN2/GPIO52 R8 SB_INT_FLASH_SEL 44
C522 C523 C6
1U_0402_6.3V4Z TEMP_COMM
1U_0402_6.3V4Z TEMPIN0/GPIO61 B6 XMIT_OFF# 37
1 1
TEMPIN1/GPIO62 A6 BT_COMBO_EN# 37
TEMPIN2/GPIO63 A5 <BOM Structure>
B5

HW MONITOR
TEMPIN3/TALERT#/GPIO64 EC_THERM# 45 CH751H-40PT_SOD323-2
+3VS A4 2 1
VIN0/GPIO53 AC_IN 45,49
L55 B4
VIN1/GPIO54 BT_OFF 43 D41
2 1 +XTLVDD_SATA C4
VIN2/GPIO55 CAM_SHDN# 28
BLM18PG121SN1D_0603 2 1 D4 1 2 +3VALW
VIN3/GPIO56 R562 150K_0402_5%
VIN4/GPIO57 D5
C524 C625 D6 PV:Add D41 and R562
1U_0402_6.3V4Z @ 0.1U_0402_16V4Z VIN5/GPIO58
VIN6/GPIO59 A7
3 1 2 <BOM Structure> 3
VIN7/GPIO60 B7

PV:Reserve for EMI +3VALW

L56
F6 +SB_AVDD 2 1
AVDD BLM18PG121SN1D_0603
1 1
10P_0402_50V8J 2 1 C516 SATA_X1 G7
AVSS C526
1

2.2U_0603_6.3V4Z
Y4 R341 2 2
218S7EALA11FG_BGA528_SB700
25MHZ_20P C525
10M_0402_5% SBR1@ 0.1U_0402_16V4Z
2

10P_0402_50V8J 2 1 C517 SATA_X2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 31 of 58
A B C D E
 A B C D E

+3VALW

2
R561
10K_0402_5%

1
PCIE_WAKE#
36,37 LAN_PCIE_WAKE# U15D
1 2 C617 1 2@ 100P_0402_25V8K
36,37 MINI_PCIE_WAKE# R311 @ 100_0402_5%
SB700 Part 4 of 5
1 1
E1 PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB 26
demo circuit LID use RI# H7 SLP_S2/GPM9#
F5 G8 USB_RCOMP 1 2
45 SLP_S3# SLP_S3# USB_RCOMP
G1 11.8K_0402_1% R323
45 SLP_S5# SLP_S5#

USB MISC
ACPI / WAKE UP EVENTS
45 PWRBTN_OUT# H2 PWR_BTN#
6,45,56 SB_PWRGD H1 PWR_GOOD
+3VS 1 2 SUS_STAT# SUS_STAT# K3
11 SUS_STAT# SUS_STAT#
R388 4.7K_0402_5% SB_TEST2 H5 E6
SB_TEST1 TEST2 USB_FSD13P
H4 TEST1 USB_FSD13N E7
SB700 has internal PD SB_TEST0 H3 TEST0

USB 1.1
Y15 F7 USB10_P12 Touch Screen
45 GATEA20 GA20IN/GEVENT0# USB_FSD12P USB10_P12 43
+3VALW 1 2 SB_TEST2 W15 E8 USB10_N12
45 KB_RST# KBRST#/GEVENT1# USB_FSD12N USB10_N12 43
R320 @ 2.2K_0402_5% K4
45 EC_SCI# LPC_PME#/GEVENT3#
1 2 SB_TEST1 K24 H11 USB20_P11
45 EC_SMI# LPC_SMI#/EXTEVNT1# USB_HSD11P USB20_P11 37
R321 @ 2.2K_0402_5% F1 J10 USB20_N11 USB-11 New Card
S3_STATE/GEVENT5# USB_HSD11N USB20_N11 37
1 2 SB_TEST0 J2
R322 @ 2.2K_0402_5% PCIE_WAKE# SYS_RESET#/GPM7# USB20_P10
H6 WAKE#/GEVENT8# USB_HSD10P E11 USB20_P10 37
F2 F11 USB20_N10 USB-10 MiniCard(TV tuner)
BLINK/GPM6# USB_HSD10N USB20_N10 37
H_THERMTRIP# J6
6,45 H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
11 NB_PWRGD W14 NB_PWRGD USB_HSD9P A11
USB_HSD9N B11 USB-9 Card Reader(delete)
2 1 EC_RSMRST# PV:delete R381 & R386 D3 RSMRST#
R327 100K_0402_5% C10 USB20_P8
USB_HSD8P USB20_P8 37
D10 USB20_N8 USB-8 WLAN
USB_HSD8N USB20_N8 37
SI2: change from 2.2K to 100K ohm AE18 G11 USB20_P7
SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 43
EC_RSMRST# AD18 H12 USB20_N7 USB-7 Fingerprint
45 EC_RSMRST# CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 43
AA19 SMARTVOLT1/SATA_IS2#/GPIO4
W17 E12 USB20_P6
CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB20_P6 43
V17 E14 USB20_N6 USB-6 Bluetooth
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USB20_N6 43
W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
2 USB20_P5 2
40 SB_SPKR W21 C12

USB 2.0
SPKR/GPIO2 USB_HSD5P USB20_P5 28
8,9,26,39 SMB_CK_CLK0 SMB_CK_CLK0 AA18 D12 USB20_N5 USB-5 USB Camera
SCL0/GPOC0# USB_HSD5N USB20_N5 28
8,9,26,39 SMB_CK_DAT0 SMB_CK_DAT0 W18
+3VS SMB_CK_CLK1 SDA0/GPOC1# USB20_P4
37 SMB_CK_CLK1 K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 43
SMB_CK_DAT1 K2 A12 USB20_N4 USB-4 Left side
37 SMB_CK_DAT1 SDA1/GPOC3# USB_HSD4N USB20_N4 43
AA20 DDC1_SCL/GPIO9

GPIO
R328 1 2 2.2K_0402_5% SMB_CK_CLK0 Y18 G12 USB20_P3
DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 47
C1 G14 USB20_N3 USB-3 Dock
LLB#/GPIO66 USB_HSD3N USB20_N3 47
R329 1 2 2.2K_0402_5% SMB_CK_DAT0 +3VS 1 2 Y19
R400 @ 4.7K_0402_5% SMARTVOLT2/SHUTDOWN#/GPIO5 USB20_P2
G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USB20_P2 43
+3VALW USB20_N2
USB_HSD2N H15 USB20_N2 43 USB-2 Left Side
MV: reserve pull high for GPIO5
A13 USB20_P1
USB_HSD1P USB20_P1 43
B13 USB20_N1 USB-1 Right side
USB_HSD1N USB20_N1 43
R331 1 2 2.2K_0402_5% SMB_CK_CLK1
B14 USB20_P0
45 EC_LID_OUT# USB_HSD0P USB20_P0 43
R332 1 2 2.2K_0402_5% SMB_CK_DAT1 B9 A14 USB20_N0 USB-0 Right side
37 EXP_CPPE# USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 43
38 CR_CPPE# B8 USB_OC5#/IR_TX0/GPM5#
A8 A18

USB OC
36 LAN_DSM# USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
E5 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21
F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21
R333 33_0402_5% 1 2 E4 F19
40 HDA_BITCLK_CODEC USB_OC0#/GPM0# SDA2/IMC_GPIO12
R334 33_0402_5% 1 2 HDA_BITCLK E20
46 HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13
R335 33_0402_5% 1 2 M1 E21
46 HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14
R336 33_0402_5% 1 2 HDA_SDOUT M2 E19
40 HDA_SDOUT_CODEC AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0 J7 D19 STRAP PIN
40 HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 34
HDA_SDIN1
46 HDA_SDIN1 J8
L8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 GPIO17 34 STRAP PIN

HD AUDIO
AZ_SDIN2/GPIO44
M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
R337 33_0402_5% 1 2 HDA_SYNC L6 G21
46 HDA_SYNC_MDC AZ_SYNC IMC_GPIO19
R338 33_0402_5% 1 2 M4 D25
3 40 HDA_SYNC_CODEC AZ_RST# IMC_GPIO20 3
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
R339 33_0402_5% HDARST#

INTEGRATED uC
40 HDA_RST#_CODEC 1 2 IMC_GPIO22 C25
R340 33_0402_5% 1 2 C24
46 HDA_RST#_MDC IMC_GPIO23
PAD T41 IMC_GPIO24 B25
IMC_GPIO25 C23
STRAP PIN 34,45 HDARST#
B24
IMC_GPIO26
IMC_GPIO27 B23
IMC_GPIO28 A23
IMC_GPIO29 C22
IMC_GPIO30 A22
IMC_GPIO31 B22
IMC_GPIO32 B21
IMC_GPIO33 A21
H19 IMC_GPIO0 IMC_GPIO34 D20
H20 IMC_GPIO1 IMC_GPIO35 C20
INTEGRATED uC

H21 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 A20

F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20
IMC_GPIO38 B19
D22 IMC_GPIO4 IMC_GPIO39 A19
E24 IMC_GPIO5 IMC_GPIO40 D18
E25 IMC_GPIO6 IMC_GPIO41 C18
D23 IMC_GPIO7

218S7EALA11FG_BGA528_SB700

SBR1@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 32 of 58
A B C D E
 A B C D E

U15C U15E
1 2 +1.2VALW
R592 @ 0_0805_5%
SB700 L15 +1.2V_HT_R
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1
M12
1
R593
2
0_0805_5%
+1.2V_HT SB700 A2
VDDQ_2 VDD_2 VSS_1
2 1 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
C528 22U_0805_6.3V6M U9 N13 10U_0805_6.3V6M C529 B1

CORE S0
1 C531 1U_0402_6.3V4Z VDDQ_4 VDD_4 1U_0402_6.3V4Z C532 VSS_3 1
1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7
C530 1 2 1U_0402_6.3V4Z U17 P14 1U_0402_6.3V4Z 2 1 C534 T10 F20
VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5

PCI/GPIO I/O
C533 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C538 U10 G19
C536 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C537 AVSS_SATA_2 VSS_6
1 2 W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
C535 1 2 1U_0402_6.3V4Z Y6 T16 0.1U_0402_16V4Z 2 1 C527 U12 K9
C539 0.1U_0402_16V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C540 AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
C541 1 2 0.1U_0402_16V4Z AB5 V14 K16
C542 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
Y11 AVSS_SATA_9 VSS_13 L10
No IDE device unmount CAP Y14 AVSS_SATA_10 VSS_14 L11
L60 Y17 L12
+1.2V_CKVDD AVSS_SATA_11 VSS_15
+3VS Y20 VDD33_18_1 CKVDD_1.2V_1 L21 2 1 +1.2V_HT AA9 AVSS_SATA_12 VSS_16 L14
AA21 L22 0_0603_5% AB9 L16
VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17
2 1 AA22 L24 AB11 M6

IDE/FLSH I/O

CLKGEN I/O
C543 @ 22U_0805_6.3V6M VDD33_18_3 CKVDD_1.2V_3 C546 @ 1U_0402_6.3V4Z AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 1 2 AB13 AVSS_SATA_15 VSS_19 M10
C544 1 2 @ 1U_0402_6.3V4Z C545 1 2 @ 1U_0402_6.3V4Z AB15 M11
C547 AVSS_SATA_16 VSS_20
1 2 @ 1U_0402_6.3V4Z C548 2 1 @ 0.1U_0402_16V4Z AB17 AVSS_SATA_17 VSS_21 M13
C549 1 2 @ 1U_0402_6.3V4Z C551 2 1 @ 0.1U_0402_16V4Z AC8 M15
C550 @ 10U_0805_10V4Z AVSS_SATA_18 VSS_22
1 2 AD8 AVSS_SATA_19 VSS_23 N4
AE8 AVSS_SATA_20 VSS_24 N12
VSS_25 N14
+PCIE_VDDR P6
L61 POWER MV:internal CLKGEN no use,cap unmount VSS_26
VSS_27 P9
+1.2V_HT 2 1 VSS_28 P10
0_0805_5% A15 P11
AVSS_USB_1 VSS_29
P18 PCIE_VDDR_1 B15 AVSS_USB_2 VSS_30 P13
2 1 P19 +3VALW C14 P15
C552 4.7U_0805_10V6K PCIE_VDDR_2 AVSS_USB_3 VSS_31
P20 PCIE_VDDR_3 D8 AVSS_USB_4 VSS_32 R1
C553 1 2@ 1U_0402_6.3V4Z P21 A17 +S5_3V 1 2 D9 R2

A-LINK I/O
C555 PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33
1 2 1U_0402_6.3V4Z R22 PCIE_VDDR_5 S5_3.3V_2 A24 R564 0_0805_5% D11 AVSS_USB_6 VSS_34 R4
C554 1 2 1U_0402_6.3V4Z R24 B17 1 2 D13 R9
PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35

GROUND
2 C558 2
1 2 1U_0402_6.3V4Z R25 PCIE_VDDR_7 S5_3.3V_4 J4 22U_0805_6.3V6M C556 D14 AVSS_USB_8 VSS_36 R10

3.3V_S5 I/O
C557 1 2 0.1U_0402_16V4Z J5 1U_0402_6.3V4Z 2 1 C559 D15 R12
C560 S5_3.3V_5 AVSS_USB_9 VSS_37
1 2 0.1U_0402_16V4Z S5_3.3V_6 L1 1U_0402_6.3V4Z 2 1 C561 E15 AVSS_USB_10 VSS_38 R14
L2 1U_0402_6.3V4Z 2 1 C562 F12 T11
+1.2V_SATA S5_3.3V_7 0.1U_0402_16V4Z 2 C563 AVSS_USB_11 VSS_39
1 F14 AVSS_USB_12 VSS_40 T12
L63 0.1U_0402_16V4Z 2 1 C564 G9 T14
0.1U_0402_16V4Z 2 C565 AVSS_USB_13 VSS_41
+1.2V_HT 2 1 AA14 AVDD_SATA_1 1 H9 AVSS_USB_14 VSS_42 U4
0_0805_5% AB18 +1.2VALW H17 U14
AVDD_SATA_4 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 J9 AVSS_USB_16 VSS_44 V6
2 1 AA17 G2 +S5_1.2V L64 0_0603_5% J11 Y21

CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

SATA I/O
C566 22U_0805_6.3V6M AC18 G4 J12 AB1
C567 1 AVDD_SATA_5 S5_1.2V_2 +1.2VALW AVSS_USB_18 VSS_46
2 1U_0402_6.3V4Z AD17 AVDD_SATA_6
1U_0402_6.3V4Z 2 1 C569 J14 AVSS_USB_19 VSS_47 AB19
C568 1 2 1U_0402_6.3V4Z AE17 1U_0402_6.3V4Z 2 1 C570 J15 AB25
C571 1 AVDD_SATA_7 +1.2_USB AVSS_USB_20 VSS_48
2 0.1U_0402_16V4Z L65 0_0603_5% K10 AVSS_USB_21 VSS_49 AE1
C572 1 2 0.1U_0402_16V4Z A10 K12 AE24
USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
USB_PHY_1.2V_2 B10 1 2 K14 AVSS_USB_23
10U_0805_10V4Z C573 K15
1U_0402_6.3V4Z 2 C574 AVSS_USB_24
1 PCIE_CK_VSS_9 P23
1U_0402_6.3V4Z 2 1 C575 R16
PCIE_CK_VSS_10
PCIE_CK_VSS_11 R19
+AVDD_USB T17
L66 PCIE_CK_VSS_12
PCIE_CK_VSS_13 U18
+3VALW 2 1 A16 AE7 +V5_VREF 1K_0402_5% 2 1 R346 +5VS H18 U20
0_0805_5% AVDDTX_0 V5_VREF D14 PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 AVDDTX_1 2 2 J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18
C16 J16 +AVDDCK_3.3V 1 2 +3VS J22 V20
C576 10U_0805_10V4Z AVDDTX_2 AVDDCK_3.3V C578 C579 PCIE_CK_VSS_3 PCIE_CK_VSS_16
1 2 D16 AVDDTX_3 K25 PCIE_CK_VSS_4 PCIE_CK_VSS_17 V21
C577 1 2 10U_0805_10V4Z D17 K17 +AVDDCK_1.2V 0.1U_0402_16V4Z 1U_0603_10V4Z CH751H-40PT_SOD323-2 M16 W19
PLL

C580 1U_0402_6.3V4Z AVDDTX_4 AVDDCK_1.2V 1 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

1 2 E17 AVDDTX_5 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
USB I/O

C581 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24

C583 0.1U_0402_16V4Z AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
1 2 F17 AVDDRX_1 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
C582 1 2 0.1U_0402_16V4Z F18 L67
C584 0.1U_0402_16V4Z AVDDRX_2
1 2 G15 AVDDRX_3 2 1 +3VALW F9 AVSSC AVSSCK L17
3 0_0603_5% 3
G17 AVDDRX_4 Part 5 of 5
G18 AVDDRX_5 2.2U_0603_6.3V4Z 2 1 C585 218S7EALA11FG_BGA528_SB700

0.1U_0402_16V4Z 2 1 C586
218S7EALA11FG_BGA528_SB700 SBR1@

SBR1@

L68
+AVDDCK_1.2V 2 1 +1.2V_HT
0_0603_5%

2.2U_0603_6.3V4Z 2 1 C587

0.1U_0402_16V4Z 2 1 C588

L69
+AVDDCK_3.3V 2 1 +3VS
0_0603_5%

2.2U_0603_6.3V4Z 2 1 C589

0.1U_0402_16V4Z 2 1 C590

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 33 of 58
A B C D E
 A B C D E

REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 LPC_CLK0 LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16

PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
H,H = Reserved
ENABLED STRAPS
1 DEFAULT 1
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R355

R356
R347

R348

R349

R350

R351

R352

R353

R354
2

2
@

@
@ @ @ @ @ @ @
30 PCI_CLK2
30 PCI_CLK3
30 PCI_CLK4
30 PCI_CLK5
30,45 CLK_PCI_EC SI2: mount 2.2K ohm
30,44 CLK_PCI_SIO
30 RTC_CLK
32,45 HDARST#
2 32 GPIO17 2
32 GPIO16

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R363

R365

R366
R357

R358

R359

R360

R361

R362

R364
2

2
@ @ @ @

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
RESET BCLK

30 PCI_AD28
30 PCI_AD27
30 PCI_AD26
30 PCI_AD25
30 PCI_AD24
30 PCI_AD23
1

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R373

R374

R375

R376

R377

R378
2

2
@ @ @ @ @ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 34 of 58
A B C D E
 A B C D E

HDD Connector
JP9
+5VS
GND 1
2 SATA_TXP0
A+ SATA_TXP0 31

10U_0805_10V4Z

0.1U_0402_16V4Z
3 SATA_TXN0
A- SATA_TXN0 31
1 1 1 1 4 0.01U_0402_16V7K
C593 GND

C595
1 SATA_RXN0 1
B- 5 2 1 C592 SATA_RXN0_C SATA_RXN0_C 31
C594 C591 6 SATA_RXP0 2 1 C596 SATA_RXP0_C
B+ SATA_RXP0_C 31
7 0.01U_0402_16V7K
2 2 2 2 GND
0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side.
V33 8 +3VS
V33 9
Pleace near HD CONN (JP23) V33 10
GND 11
GND 12
GND 13
V5 14
15 +5VS
V5
V5 16
GND 17
Reserved 18
GND 19
V12 20
V12 21
V12 22

SUYIN_127072FR022G210ZR_RV

CONN@

2
2nd HDD Connector-option 2

JP10
+5VS
GND 1
2 SATA_TXP1
A+ SATA_TXP1 31
10U_0805_10V4Z

0.1U_0402_16V4Z

3 SATA_TXN1
A- SATA_TXN1 31
1 1 1 1 4 0.01U_0402_16V7K
GND
C601

C604

5 SATA_RXN1 2 1 C605 SATA_RXN1_C

B- SATA_RXN1_C 31
C602 C603 6 SATA_RXP1 2 1 C606 SATA_RXP1_C
B+ SATA_RXP1_C 31
7 0.01U_0402_16V7K
2 2 2 2 GND
0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side.
V33 8 +3VS
V33 9
Pleace near HD CONN (JP23) V33 10
GND 11
GND 12
GND 13
V5 14
15 +5VS
V5
V5 16
GND 17
Reserved 18
GND 19
V12 20
V12 21
V12 22

SUYIN_127072FR022G210ZR_RV
CONN@
3 3

CD-ROM Connector
+5VS JP11

Placea caps. near ODD CONN. GND 1

SATA_TXP4
A+ 2 SATA_TXP4 31
3 SATA_TXN4
A- SATA_TXN4 31
4 0.01U_0402_16V7K
GND SATA_RXN4
B- 5 2 1 C612 SATA_RXN4_C SATA_RXN4_C 31
6 SATA_RXP4 2 1 C611 SATA_RXP4_C
B+ SATA_RXP4_C 31
0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z

7 0.01U_0402_16V7K
GND
1 1 1 1
Near CONN side.
C613

C614

C615

C616 8
10U_0805_10V4Z DP
V5 9
2 2 2 2
V5 10 +5VS
MD 11
15 GND GND 12
14 GND GND 13

4 SUYIN_127382FR013G509ZR 4

CONN@
SI: Update ODD footprint to fix pin reverse issue

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 35 of 58
A B C D E
 A B C D E

Place Close to Chip

U18 +3V_LAN
Close to Pin16,37,46,53
0.1U_0402_16V7K
C485 2 1 PCIE_PTX_IRX_P3 29 45
10 PCIE_PTX_C_IRX_P3 HSOP EEDO
47 LAN_DI 1 2 +3V_LAN
C488 PCIE_PTX_IRX_N3 EEDI/AUX R382 3.6K_0402_5%
10 PCIE_PTX_C_IRX_N3 2 1 30 HSON EESK 48
0.1U_0402_16V7K 44 2 2 2 2
EECS C620 C621 C622 C623
10 PCIE_ITX_C_PRX_P3 23 HSIP
24 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
10 PCIE_ITX_C_PRX_N3 HSIN 1 1 1 1
LED3 54
LED2 55
33 56 LAN_LINK#
26 CLKREQ_LAN CLKREQB LED1
57 LAN_ACTIVITY#

4
.
7
u
H
c
h
o
k
e
LED0
26

B3
e
a
dm
f
o
r
8
1
1
1
C
26 CLK_PCIE_LAN REFCLK_P

0
0
A
27 3 LAN_MDI0+ +LAN_VDD12 +LAN_EVDD12
1 26 CLK_PCIE_LAN# REFCLK_N MDIP0 1
4 LAN_MDI0- 4.7UH_1008HC-472EJFS-A_5%_1008
MDIN0 LAN_MDI1+ L71 L72
11,14,15,30,37,38,44,45 PLT_RST# 20 PERSTB MDIP1 6
7 LAN_MDI1- +CTRL_18 1 2
MDIN1 LAN_MDI2+ 0_0603_5%
MDIP2 9
+CTRL_18 1 10 LAN_MDI2- C627 2 2
SROUT12 MDIN2

0.1U_0402_16V4Z
12 LAN_MDI3+ 1 2 C632 C633
MDIP3 LAN_MDI3-
+LAN_VDD12 5 FB12 MDIN3 13
C626 0.1U_0402_16V4Z 0.1U_0402_16V4Z
22U_0805_6.3V6M 1 1
+3V_LAN 62 ENSR 2 1 +LAN_VDD12
DVDD12 21 +LAN_VDD12
R408 1 2 2.49K_0402_1% 64 32 Close to Pin1
RSET DVDD12
DVDD12 38
DVDD12 43
DVDD12 49
32,37 LAN_PCIE_WAKE# 19 LANWAKEB DVDD12 52 2 2 2 2 2 2
C636 C637 C638 C639 C640 C641
ISOLATE# 36 ISOLATEB 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
EVDD12 22 +LAN_EVDD12 1 1 1 1 1 1
EVDD12 28
LAN_X1 60 +3V_LAN
CKTAL1
+3VS LAN_X2 61 16
CKTAL2 VDD33 L75
VDD33 37
VDD33 46 +3V_LAN 0_0603_5%
1

VDD33 53
R384 65 2 2 2 2 2
@ 1K_0402_1% EXPOSE_PAD C635 0.1U_0402_16V4Z C644 C645 C646 C647 C648
R398 VDDSR 63 2 1
25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2

ISOLATE# EGND +AVDD33 1 1 1 1 1

31 LAN_ISOLATE# 2 1 AVDD33 2 1 2
31 EGND AVDD33 59
C634 10U_0805_10V4Z
1K_0402_1%
AVDD12 8 +LAN_VDD12
R401 15 11 +3V_LAN
15K_0402_5% NC AVDD12 L74
17 NC AVDD12 14
18 58 +AVDD33
NC AVDD12 0_0603_5%
34 NC 2 2
2 35 C650 C651 2
NC
39 NC IGPIO 50
40 51 DSM# 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
NC OGPIO LAN_DSM# 32 1 1
41 0_0402_5% R399
NC
42 NC
RTL8111C-GR_QFN64_9X9

Close to Pin2 & pin59

Y1
LAN_X1 2 1LAN_X2

25MHZ_20P
1 1
C182 C181

27P_0402_50V8J 27P_0402_50V8J
2 2
PJP6
1 2
+3VALW
PAD-OPEN 4x4m

40 mils
S

D
3 1 +3V_LAN
2

2
R713
G
2

@ 100K_0402_5% C707 Q61

SI2301BDS-T1-E3_SOT23-3
1
1

45 LANPWR 1 2
R715 10K_0402_5% 0.1U_0402_16V4Z

3 3

LAN Conn.
JP12
+3V_LAN 13 Yellow LED+
LAN_ACTIVITY# R391 2 1 300_0402_5% 14
U19 Yellow LED-
1 SHLD1 16
C600 0.01U_0603_100V4Z R392 75_0402_1% RJ45_MIDI3- 8
RJ45_GND C656 PR4-
1 TCT1 MCT1 24 2 1 1 2 DETECT PIN1 9
LAN_MDI3- 2 23 RJ45_MIDI3- RJ45_MIDI3- 47 @68P_0402_50V8K RJ45_MIDI3+ 7
LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+ 2 PR4+
3 TD1- MX1- 22 RJ45_MIDI3+ 47 PV:Add ESD diode for EMI request
C607 0.01U_0603_100V4Z R393 75_0402_1% RJ45_MIDI1- 6 PR2-
4 TCT2 MCT2 21 2 1 1 2
LAN_MDI2- 5 20 RJ45_MIDI2- RJ45_MIDI2- 47 RJ45_MIDI2- 5
LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+ LAN_ACTIVITY# PR3-
6 TD2- MX2- 19 RJ45_MIDI2+ 47
C610 0.01U_0603_100V4Z R394 75_0402_1% RJ45_MIDI2+ 4
LAN_LINK# PR3+
7 TCT3 MCT3 18 2 1 1 2
LAN_MDI1- 8 17 RJ45_MIDI1- RJ45_MIDI1- 47 RJ45_MIDI1+ 3
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ PR2+
9 TD3- MX3- 16 RJ45_MIDI1+ 47

2
C619 0.01U_0603_100V4Z R396 75_0402_1% RJ45_MIDI0- 2
D39 PR1-
10 TCT4 MCT4 15 2 1 1 2 DETCET PIN2 10
LAN_MDI0- 11 14 RJ45_MIDI0- RJ45_MIDI0- 47 PSOT24C_SOT23-3 2 RJ45_MIDI0+ 1
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+ PR1+
12 TD4- MX4- 13 RJ45_MIDI0+ 47 @ SHLD1 15
C657 11
@68P_0402_50V8K +3V_LAN Green LED+

1
LAN_LINK# 1 R395
1 1 2 1 300_0402_5% 12 Green LED-
NS892402
C659 C660 1 FOX_JM36113-P1122-7F
0.01U_0402_16V7K 0.01U_0402_16V7K CONN@ LANGND
4
2 2 C658 4
1 1
1000P_1808_3KV7K C661 C662
2
1 1
0.1U_0402_16V4Z 4.7U_0805_10V4Z
C663 C664 2 2
0.01U_0402_16V7K 0.01U_0402_16V7K
2 2

Place these components

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
colsed to LAN chip THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 36 of 58
A B C D E
 A B C D E

Mini Card---TV tuner

SI2: chagne power plan from +3VALW to +3VS_TV
+1.5VS_TV
+3VS_TV +3VS_TV
0.01U_0402_16V7K 4.7U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1
1 1 C667 C668 C669 C670
C665 C666
2 2 2 2
2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
1 1
@

New Card
CONN@
SI: Exchange TV & WLAN JP14
minicard location 1 1 2 2 +3VS_TV
3 3 4 4
5 5 6 6 +1.5VS_TV
+1.5VS 7 8
U21 26 CLKREQ_MCARD1# 7 8
C681 9 10
9 10
2 1 0.1U_0402_16V4Z 12 1.5Vin 1.5Vout 11 +1.5VS_PEC 26 CLK_PCIE_MCARD1# 11 11 12 12
14 1.5Vin 1.5Vout 13 26 CLK_PCIE_MCARD1 13 13 14 14
+3VS 15 16
C679 15 16
17 17 18 18 SI2: chagne power plan from +3VALW to +3VS_TV
2 1 0.1U_0402_16V4Z 2 3.3Vin 3.3Vout 3 +3VS_PEC 19 19 20 20
4 5 21 22 PLT_RST#
3.3Vin 3.3Vout 21 22
2 1 0.1U_0402_16V4Z 10 PCIE_PTX_C_IRX_N5 23 23 24 24 +3VS_TV
+3VALW C680 17 15 +3V_PEC 10 PCIE_PTX_C_IRX_P5 25 26
AUX_IN AUX_OUT 25 26
27 27 28 28 +1.5VS_TV
PLT_RST# 6 19 29 30 SMB_CK_CLK1
11,14,15,30,36,38,44,45 PLT_RST# SYSRST# OC# 29 30
31 32 SMB_CK_DAT1
10 PCIE_ITX_C_PRX_N5 31 32
20 8 PERST# 33 34
45,48,51 SYSON SHDN# PERST# 10 PCIE_ITX_C_PRX_P5 33 34
35 35 36 36 USB20_N10 32
40,45,48,49,52,55 SUSP# 1 STBY# NC 16 37 37 38 38 USB20_P10 32
+3VS_TV 39 39 40 40
+3VALW 2 1@ 100K_0402_5% 10 CPPE# GND 7 41 41 42 42
R412 43 44
EXP_CPPE# 43 44
32 EXP_CPPE# 9 CPUSB# 45 45 46 46
THERMAL_PAD 21 47 47 48 48 +1.5VS_TV
18 49 50
Power Switch internal pull high RCLKEN
51
49
51
50
52 52 +3VS_TV
2 2
R5538D001-TR-F_QFN20_4X4~D
53 GND1GND2 54
USE TI TPS2231MRGPR MOLEX 67910-0002 52P

+1.5VS R406 1 2 0_1206_5% +1.5VS_TV

+3VS R407 1 2 0_1206_5% +3VS_TV

Mini-Express Card---WLAN
+3VS_WLAN +1.5VS_WLAN +3VALW

0.01U_0402_16V7K 4.7U_0805_10V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z

Near to Express Card slot. 1 1 1 1 1 1 1
C785 C786 C787 C781 C782 C783
+3VS_PEC C784 0.1U_0402_16V4Z

JP16 4.7U_0805_10V4Z 2 2 2 2 2 2 2

1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
GND
32 USB20_N11 2 USB_D-
3 C677 C678 3
32 USB20_P11 3 USB_D+ 31 BT_COMBO_EN# 1 2 CH_CLK
EXP_CPPE# 4 R547 0_0402_5%
CPUSB#

2
2 2
5 RSV
6 0.1U_0402_16V4Z R553
RSV +1.5VS_WLAN +3VS_WLAN
32 SMB_CK_CLK1 7 SMB_CLK 4.7K_0402_5%
8 CONN@ +3VS
32 SMB_CK_DAT1 SMB_DATA +1.5VS_PEC
9 R556 ＠ 0_0402_5% JP26
+1.5VS_PEC

1
+1.5V MINI_PCIE_WAKE# L78
+1.5VS_PEC 10 +1.5V 1 2 1 1 2 2 1 2 0_1206_5%
MINI_PCIE_WAKE# 11 4.7U_0805_10V4Z 3 4
32,36 MINI_PCIE_WAKE# WAKE# 43 CH_DATA 3 4
12 1 1 CH_CLK 5 6
+3V_PEC +3.3VAUX 43 CH_CLK 5 6 +1.5VS
PERST# 13 26 CLKREQ_MCARD2# 7 8
PERST# C683 C682 7 8
+3VS_PEC 14 +3.3V 9 9 10 10
15 11 12 L79 1 2 0_1206_5%
+3.3V 2 2 26 CLK_PCIE_MCARD2# 11 12
26 CLKREQ_NCARD# 16 CLKREQ# 26 CLK_PCIE_MCARD2 13 13 14 14
EXP_CPPE# 17 15 16
CPPE# 0.1U_0402_16V4Z 15 16
26 CLK_PCIE_NCARD# 18 REFCLK- 17 17 18 18
26 CLK_PCIE_NCARD 19 REFCLK+ 19 19 20 20 XMIT_OFF# 31
20 21 22 PLT_RST#
GND 21 22 +3VAUX R634 1
10 PCIE_PTX_C_IRX_N0 21 PERn0 10 PCIE_PTX_C_IRX_N2 23 23 24 24 2 @ 0_0603_5% +3VALW
22 10 PCIE_PTX_C_IRX_P2 25 26 R635 1 2 0_0603_5% +3VS
10 PCIE_PTX_C_IRX_P0 PERp0 +3V_PEC 25 26
23 GND 27 27 28 28
10 PCIE_ITX_C_PRX_N0 24 29 30 SMB_CK_CLK1
PETn0 4.7U_0805_10V4Z 29 30 SMB_CK_DAT1
10 PCIE_ITX_C_PRX_P0 25 PETp0 10 PCIE_ITX_C_PRX_N2 31 31 32 32
26 GND 10 PCIE_ITX_C_PRX_P2 33 33 34 34
1 1 35 35 36 36 USB20_N8 32
27 GND1 SHIELD 29 37 37 38 38 USB20_P8 32
28 30 C684 C685 +3VS_WLAN 39 40
GND2 SHIELD 39 40
41 41 42 42
SANTA_131851-A_LT 2 2
43 43 44 44 WL_LED# 46
0.1U_0402_16V4Z 45 46
45 46
CONN@ 47 47 48 48
49 49 50 50
4 4
51 51 52 52

53 54
SI: Exchange TV & WLAN
GND1GND2
minicard location
MOLEX 67910-0002 52P

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 37 of 58
A B C D E
 A B C D E

SI:Per ME request change

JP21 to new one Card Reader Connector
JP21
+VCC_4IN1 3 XD-VCC SD-VCC 21 +VCC_4IN1
MS-VCC 28
XD_SD_MS_D0 32
XD_SD_MS_D1 XD-D0 SDCLK
10 XD-D1 7 IN 1 CONN SD_CLK 20
XD_SD_MS_D2 9 14 XD_SD_MS_D0
XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1 SDCLK
8 XD-D3 SD-DAT1 12 1 2 1 2
XD_SD_D4 7 30 XD_SD_MS_D2
XD_SD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3 R413 C902
6 XD-D5 SD-DAT3 29
1 XD_SD_D6 XD_SD_D4 @ 100_0402_5% @ 100P_0402_25V8K 1
5 XD-D6 SD-DAT4 27
XD_SD_D7 4 23 XD_SD_D5
+VCC_4IN1 XD-D7 SD-DAT5 XD_SD_D6
SD-DAT6 18
SDCMD_MSBS_XDWE# 34 16 XD_SD_D7
10K_0402_5% R45 XDWP#_SDWP# XD-WE SD-DAT7 SDCMD_MSBS_XDWE#
33 XD-WP SD-CMD 25
1 2 XDWP#_SDWP# XD_ALE 35 XD-ALE SD-CD-SW 1 XDCD0#_SDCD#
10K_0402_5% XD_CD# 40
XD_RB# XD_RB# XD-CD XDWP#_SDWP#
1 2 39 XD-R/B SD-WP-SW 2
XD_RE# 38 MSCLK 1 2 1 2
R106 XDCE# XDCE# XD-RE
2 1 2 1 37 XD-CE
XD_CLE 36 26 MSCLK R410 C900
C901 R411 XD-CLE MS-SCLK XD_SD_MS_D0 @ 100_0402_5% @ 100P_0402_25V8K
MS-DATA0 17
+3VS 100P_0402_25V8K @ 100_0402_5% @ 11 15 XD_SD_MS_D1
7IN1 GND MS-DATA1 XD_SD_MS_D2
31 7IN1 GND MS-DATA2 19
2 1 XD_CLE SI:Per Jmicro request change 24 XD_SD_MS_D3
10K_0402_5% R405 MS-DATA3 XDCD1#_MSCD#
R405 & R122 from 200K to 10K MS-INS 22
2 1 XD_ALE 13 SDCMD_MSBS_XDWE#
10K_0402_5% @ R122 MS-BS
41 7IN1 GND
2 1 42 7IN1 GND
10K_0402_5% R127 +1.8VS_OUT +1.8VS
2 1 XD_RE# TAITW_R015-B10-LM R387
200K_0402_5% R86 0.1U_0402_16V4Z 1000P_0402_50V7K 1 2
CONN@ 1 1 1 1
@ 0_0603_5%
C892 C688 C687 C893
+3VS SI2:Support D3E function
2 2 2 2 SI:Use build in Regulator
10U_0805_10V4Z 0.1U_0402_16V4Z Chip unmount R387
1

R126
Power Circuit
10K_0402_5% +3VS
2 U23 2
1 1
2 2

C691 C692
G

26 CLK_PCIE_MCARD0# 3 APCLKN APVDD 5

Q54 4 10
26 CLK_PCIE_MCARD0 APCLKP APV18 2 2
32 CR_CPPE# 1 3 CPPE#
9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D

10 PCIE_ITX_C_PRX_N1 APRXN
10 PCIE_ITX_C_PRX_P1 8 APRXP DV33 19
2N7002_SOT23-3 20
C693 1 0.1U_0402_16V7K PCIE_PTX_IRX_N1 DV33
10 PCIE_PTX_C_IRX_N1 2 11 APTXN DV33 44
0_0402_5% 10 PCIE_PTX_C_IRX_P1 C697 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P1 12 18 +1.8VS_OUT
XDCD0#_SDCD# APTXP DV18
31 CR_WAKE# 1 2 DV18 37 1 1
R397 2 1 7
8.2K_0402_5% R114 APREXT XD_SD_MS_D0 C686 C690
MDIO0 48
SI:Per Jmicro request change 47 XD_SD_MS_D1 0.1U_0402_16V4Z
XIN MDIO1 XD_SD_MS_D2 2 2
R114 from 10K to 8.2K 38 TXIN MDIO2 46
XOUT 39 45 XD_SD_MS_D3
+3VS TXOUT JMB380 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE# 0.1U_0402_16V4Z
42 SDCLK_MSCLK_XDCE#
MDIO5 XDWP#_SDWP#
1 2 30 TAV33 MDIO6 41
SI:Use build in Regulator C695 0.1U_0402_16V4Z 40 XD_CLE
MDIO7 XD_SD_D4 SDCLK_MSCLK_XDCE# SDCLK
MDIO8 29 2 1
Chip mount R383,C689,C694 +5VS 1 28 XD_SD_D5 22_0402_5% 2 1 R457 MSCLK
11,14,15,30,36,37,44,45 PLT_RST# XRSTN MDIO9 XD_SD_D6 22_0402_5% 2
2 XTEST MDIO10 27 1 R456 XDCE#
26 XD_SD_D7 22_0402_5% R455
MDIO11
1

+VCC_OUT +VCC_4IN1 25 XD_RE#

R370 CPPE# MDIO12 XD_RB#
13 SEEDAT MDIO13 23
R383 470_0402_5% 14 22 XD_ALE
SEECLK MDIO14
1 2
34 TPA+ D40
2 2

0_0603_5% XDCD1#_MSCD# TPA1P TPBIAS XDCD1#_MSCD#

1 1 15 CR1_CD1N TPBIAS_1 35 2
XDCD0#_SDCD# 16 36 TREXT 1 2 1 1 XD_CD#
C689 C694 D5 CR1_CD0N TREXT R124 12K_0402_1% XDCD0#_SDCD# 3
3 10U_0805_10V4Z 0.1U_0402_16V4Z C696 3
HT-F196BP5_WHITE APGND 6
2 2 0707 modify DAN202U_SC70 270P_0402_50V7K
+VCC_OUT 17 CR1_PCTLN 2
TCPS 24
R933 31 TPB-
1

+3VS 0_0603_5% CR_LED# TPB1N TPB+

1 2 21 32
CR1_LEDN TPB1P
TPA1N 33 TPA- Close to Chip
1

4.7K_0402_5% R121 D @ Q53

1 2XDCD0#_SDCD# 2 CR_LED#
GND 49
G SI:Change 1394 connector
2

4.7K_0402_5% R111 S 2N7002_SOT23-3 JMB380-QGAZ0A_QFN48_7X7

3

1 2 XDCD1#_MSCD# R113 1

1
@
4.7K_0402_5% SI2: Use B version chip C899 R140 R133 R199
56_0402_5% 56_0402_5%
1

220P_0402_50V7K 2

2
SI:Use new chip ,change to JP19
4.99K_0402_1% TPB- 1 TPB-
SI:Use build in Regulator High active control TPB+ 2 TPB+ GND 5
TPA- 3 6
C897 TPA- GND
Chip unmount U22 and relation parts TPA+ 4 TPA+
2 1 XIN
@ SUYIN_020115FR004S550ZL_4P-T

1
22P_0402_50V8J R200
1

+VCC_4IN1 TPBIAS 56_0402_5% R290

1

+VCC_OUT R134 56_0402_5%

40mil X2 1
24.576MHz_16P_3XG-24576-43E1

2
C177
C898
2

+3VS U22 0.33U_0603_10V7K

XOUT 2
2 1
3 IN OUT 1
4 22P_0402_50V8J 1M_0402_5% 4
4 EN OUT 5
1
1

C895 2 1
GND
@ 0.1U_0402_16V4Z @ G5250C2T1U_SOT23-5 C896
2 @
2 150K_0402_5%
2

@ 1U_0603_10V4Z R123
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

reserved power circuit THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 38 of 58
A B C D E
 5 4 3 2 1

D ACCELEROMETER D

SMB_CK_CLK0 8,9,26,32

14
U66

SCL / SPC
+3VS

+3VS 1 Vdd_IO SDA / SDI / SDO 13 SMB_CK_DAT0 8,9,26,32

2 GND SDO 12
Pin12(internal pull high ) pull up I2C address :0011101b

10U_0805_6.3V6M
pull low I2C address:0011100b
0.1U_0402_16V4Z

3 Reserved Reserved 11
C1030

C1031

1 1 4 GND GND 10

5 GND INT 2 9
2 2
6 Vdd INT 1 8 ACCEL_INT 30

CS
C C
LIS302DLTR_LGA14_3x5

7
+3VS 2 1
R964 10K_0402_5%

I2C address:0111000Xb
+3VS
U68

VDDIO 9 1 2
C830 @ 0.1U_0402_16V4Z
+3VS 5 CSB VDD 2 +3VS
SMB_CK_CLK0 6 4 ACCEL_INT
SCK INT

10U_0805_6.3V6M
0.1U_0402_16V4Z
C828

C829
SMB_CK_DAT0 8 7
SDI SDO
1 1
B 10 3 B
reserved GND
1 reserved GND 11
2 2

GND 12
@ @

@ BMA150_LGA12

SI: Reserve Bosch solution

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 39 of 58
5 4 3 2 1
 A B C D E

CODEC POWER
+3VDD_CODEC +VDDA_CODEC 0212_Change to +5VALW.
R885
+3VS 1 2
+5VALW +VDDA_CODEC

0.1U_0402_16V4Z

0.1U_0402_16V4Z
BLM18BD601SN1D_0603 W=40Mil U32

1U_0603_10V4Z

1U_0603_10V4Z
0.1U_0402_16V4Z
1 1 1
1 1 C728 1 2 1
(4.75V)
IN

2.2U_0805_16V4Z
0.1U_0402_16V4Z
2
OUT 5
1
300mA
2 2 2 GND

C734

C733

C904
2 2

C730

C731

C729
37,45,48,49,52,55 SUSP# 3 SHDN BYP 4
1 G9191-475T1U_SOT23-5 1 2 1
C732

0.1U_0402_16V4Z
2

U27

+3VDD_CODEC 9 DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 47 EAPD_CODEC 45

1 DVDD_CORE VOL_UP/DMIC_0/GPIO 1 2 DMIC_DAT 28

VOL_DN/DMIC_1/GPIO 2 4
+VDDA_CODEC 25 AVDD1*
GPIO 3 30
38 AVDD2**
VREFOUT-E / GPIO 4 31

+3VDD_CODEC 3 DVDD_IO GPIO 5 43 SUB_ENABLE 42

32 MONO_OUT GPIO 6 44

45 SPDIF_OUT
SPDIF OUT1 / GPIO 7 SPDIF_OUT 47
HDA_BITCLK_CODEC 6
32 HDA_BITCLK_CODEC BITCLK
SPDIF OUT0 48 SI2: change to SPDIF to pin 45
32 HDA_SDOUT_CODEC 5 SDO
R522 1 2 33_0402_5% 8
32 HDA_SDIN0 SDI_CODEC
VREFOUT-B 28 +VREFOUT_B 41
32 HDA_SYNC_CODEC 10 SYNC
VREFOUT-C 29
2 2
32 HDA_RST#_CODEC 11 RESET#
PV: add bead for EMI 5.1K_0402_1% 2 1 R548 +VDDA_CODEC
2 1 1 2 20K_0402_1% 2 1 R569 EXTMIC_DET# 41
28 DMIC_CLK
L58 FBMA-L10-160808-301LMT_0603 R230 22_0402_5% 13 SENSEA# 39.2K_0402_1% 2 1 R571 JACK_DET# 41,47
R537 SENSE_A @ 10K_0402_1% 2 R570
45 EC_BEEP 1 2 2 1 46 DMIC_CLK 1 INTMIC_DET# 41
47K_0402_5% C913 1U_0603_10V4Z 0.1U_0402_16V4Z 2 1 C951
R524 1 2 1 2 MONO_INR 33 41 HP_OUTR
32 SB_SPKR CAP2 PORTA_R HP_OUTR 41
47K_0402_5% C955 0.1U_0402_16V4Z HP Jack & Dock
12 39 HP_OUTL
PCBEEP PORTA_L HP_OUTL 41
R523 1 2 10K_0402_5%
1U_0603_10V4Z
C956 1 2 0.1U_0402_16V4Z 22 MIC_EXT_R C908 1 2
PORTB_R MIC_EXTR 41
R584 1
40 NC / OTP MIC_EXT_L
Jack MIC
+VDDA_CODEC 2 5.1K_0402_1% PORTB_L 21 C907 1 2 MIC_EXTL 41
47 SENSE_B# R916 1 2 39.2K_0402_1% SENSEB# 34 SENSE_B / NC 1U_0603_10V4Z
1
C979 37 24 MIC_IN_R
NC PORTC_R MIC_IN_R 41
0.1U_0402_16V4Z MIC_IN_L
Internal MIC
18 NC PORTC_L 23 MIC_IN_L 41
2
19 NC
36 LINE_OUT_R
PORTD_R LINE_OUT_R 41,42
HDA_BITCLK_CODEC 20 Internal SPKR.
NC LINE_OUT_L
PORTD_L 35 LINE_OUT_L 41,42
1

10U_0805_10V4Z C972 1U_0603_10V6K

R525 C744 1 2 +VC_REFA 27 15 DOCK_MICR 1 2 1 2
VREFFILT PORTE_R DOCK_MIC_R 47
@ 47_0402_5% C973 1U_0603_10V6K R943 10K_0402_5% DOCK MIC
26 14 DOCK_MICL 1 2 1 2
AVSS1* PORTE_L DOCK_MIC_L 47
R944 10K_0402_5%
2

1
1 42 AVSS2**
17 R910 R911
3 C745 PORTF_R 3
7 DVSS**
@ 33P_0402_50V8K 16 1.21K_0402_1% 1.21K_0402_1%
2 PORTF_L

2
92HD71B7X5NLGXA1X8_QFN48_7X7 1/10*Vin
SI2: Use new version Codec need close to Codec

C746
1 2
@ 1000P_0402_25V8J
SENSE A SENSE B C747
1 2
@ 1000P_0402_25V8J
Port Resistor Port Resistor C748
1 2
@ 1000P_0402_25V8J
A 39.2K E 39.2K HP_DET# MIC_DET PORT-A
C749
1 2
LINEOUT <Earphone OUT> MIC EQ
@ 1000P_0402_25V8J 0(LOW) 0(LOW) OFF ON ON Disable
B 20K F 20K
4
0(LOW) NC OFF ON OFF Disable 4
R195 1 2 0_1206_5%
NC 0(LOW) ON OFF ON Enable
C 10K G 10K R198 NC NC ON OFF OFF Enable
1 2 GNDA 41,42,47
@ 0_0805_5%
D 5.11K H 5.11K
GND GNDA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 40 of 58
A B C D E
 A B C D E

PV:change cap form 100uF to 150uF

JP17
SI2:change from 12.7K to 7.5K +5VAMP +5VS MIC_EXTR 1
U28 R594 HP_OUT_R MIC_EXTL 1

+
40 HP_OUTR 1 2 2 2
EC_MUTE# 14 19 1 2 C940 150U_D_6.3VM 3
42,45 EC_MUTE# RS/D RVDD 0_1206_5% HP_OUT_R 3
4 4
2 HP_OUT_L HP_OUT_L

+
9 LS/D LVDD 7 40 HP_OUTL 1 5 5
1 C941 150U_D_6.3VM 1
6 6
EXTMIC_DET# 7
40 EXTMIC_DET# 7

10U_0805_10V4Z

10U_0805_10V4Z
1 2 1 R701 2 16 1 SPKR+ HP_DET# 8
0.1U_0402_16V7K C770 7.5K_0402_1% RIN+ ROUT+ C766 C767 8
9 9
1 2 1 R702 2 17 3 SPKR- 10
40,42 LINE_OUT_R 0.1U_0402_16V7K C775 7.5K_0402_1% RIN- ROUT- HP OUT For M/B 45,47 CIR_IN
CIR_IN 11
10
11
+5VL 12 12
1 2 1 R703 2 12 4 SPKL+ 13
0.1U_0402_16V7K C776 7.5K_0402_1% LIN+ LOUT+ 13
14 14
1 2 1 R704 2 13 6 SPKL-
40,42 LINE_OUT_L 0.1U_0402_16V7K C817 7.5K_0402_1% LIN- LOUT- R909 0_0402_5% ACES_87213-1400G
Keep 10 mil width 40 +VREFOUT_B 2 1 1 2
SI2:change from 0.047u to 0.1u 15 RBYPASS CONN@

1
20 C742 1U_0603_10V4Z
NC R907 R908
1 11 LBYPASS
1 18 4.7K_0402_5% 4.7K_0402_5%
NC
C818 2 10

2
2 C765 GND NC
2
5 GND NC 8

1U_0603_10V4Z 21 MIC_EXTR
THERMAL_PAD 40 MIC_EXTR
1U_0603_10V4Z
SI2:change from 10u to 1u for MIC_EXTL
40 MIC_EXTL
PA PA sound issue TPA6020A2RGWR_QFN20_5x5

2 +3VALW 2

JACK_DET# 40,47

2
R46
10K_0402_5%
B+

3
1

1
5 R871
Q20B
330K_0402_5%

4
2N7002DW-7-F_SOT363-6

2
+3VALW 0.01U_0402_25V7K

1
Q21 D
1 PV:change cap form 100uF to 150uF

2
2
R47 2N7002_SOT23-3 G R936 0_0402_5%
10K_0402_5% S C854 2 1 SI2: Add cap & 44.2 ohm for dock

3
2

6
1

2
C945
R602 44.2_0603_1%
HP_DET# Q20A HP_OUTR 6DOCK_R

+
2 6 1 1 1 2 1 2 DOCK_LOUT_R 47
2N7002DW-7-F_SOT363-6 Q22A Q23A

1
2N7002DW-7-F_SOT363-6 @ 2N7002DW-7-F_SOT363-6 150U_D_6.3VM
R947 0_0402_5%
2 1
3 SI: change 2n7002 to dual package 3

5
C946
R607 44.2_0603_1%
HP_OUTL DOCK_L

+
3 4 4 3 1 2 1 2 DOCK_LOUT_L 47
+3VS
Q22B Q23B
Analog MIC 2N7002DW-7-F_SOT363-6 @ 2N7002DW-7-F_SOT363-6 150U_D_6.3VM
2

R906 @ 0_0402_5%
2 1 1 2 R555 SI: change 2n7002 to dual package
+VDDA_CODEC
@ 10K_0402_5% HP OUT For Docking
1

C743 @ 1U_0603_10V4Z PV:change cap form 100uF to 150uF

R904 R905
1

@ 4.7K_0402_5% @ 4.7K_0402_5%
2

JP20
@ 1U_0603_10V6K 1 1 SP02000D000 S W-CONN ACES 85204-04001 4P P1.25 SPEAKER
C970 1 2 MICIN_L 2 JP15
40 MIC_IN_L 2
1 2 MICIN_R 3 SPKL+ 1
40 MIC_IN_R 3 1
C971 @ 1U_0603_10V6K 4 SPKL- 2
4 SPKR+ 2
+3VS 2 1 3 3
45 ANA_MIC_DET R956 @ 10K_0402_5% 5 SPKR- 4
GND1 4
6 GND2
1

D Q27 5 GND1
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
2 ACES_88231-04001 6
@ 2N7002_SOT23-3 G CONN@ GND2
1 1 1 1
40 INTMIC_DET# S ACES_88231-04001
3

C760

C761

C762

C763
CONN@
1
1

D Q28 2 2 2 2
2 R957
@ 2N7002_SOT23-3 G @ 100K_0402_5%
4 S 4
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 41 of 58
A B C D E
 A B C D E

@ SI2: Change C980,C990 from 0.056u to 0.027u

R917 1 2 0_0603_5%

C980
1 2
+VDDA_CODEC 0.027u_0402_16V7K C981
+VREF 1 2
SI2: Change C982 from 0.039u to 5600p SI2: Change C984 from 0.039u to 0.027u
5600P_0402_25V7K
C982 1

4
1 2 C983 U41B R918
100P_0402_50V8J 5 R919 1 2

P
5600P_0402_25V7K R920 C984 +
OUT 7 1 2
1 R921 2 +VREF 10K_0402_1% 1
1 2 1 2 6 -

G
1 2 30.1K_0402_1% 10K_0402_1%
0.027u_0402_16V7K TLV2464_TSSOP14 +VDDA_CODEC

11
1
+VDDA_CODEC

100P_0402_50V8J
10K_0402_1%
R922 1
10K_0402_1% C985 +VREF
C986 R923 R924

4
1 2 1 2 1 2 U41D

2
40,41 LINE_OUT_R

4
1U_0603_10V4Z 20K_0402_1% U41A 60.4K_0402_1% 2
12

P
C987 C990 C988 + BASS_OUT
3 14

P
C989 R925 + OUT
OUT 1 1 2 1 2 1 2 13 -

G
40,41 LINE_OUT_L 1 2 1 2 2 -

G
1U_0603_10V4Z 20K_0402_1% 0.056uF_0603_16V +VDDA_CODEC 0.027u_0402_16V7K 1U_0603_10V4Z TLV2464_TSSOP14

11
+VREF

100P_0402_50V8J
TLV2464_TSSOP14

11
1 SI2: Change C987 from 0.47u to 0.056u
C991
1

4
C992 U41C
2 100P_0402_50V8J R926
10

P
R927 C993 +
OUT 8 1 2
2
+VREF 1 2 1 2 9 -

G
30.1K_0402_1% 10K_0402_1%
0.027u_0402_16V7K TLV2464_TSSOP14

11
1
R928
10K_0402_1%
R929
1 2

2
60.4K_0402_1%

SI2: Change C984 from 0.039u to 0.027u

+VDDA_CODEC +VREF
2 2
R930
1 2
4.7U_0805_10V4Z

10K_0603_5%
0.1U_0402_16V7K
1

1 1
R932
10K_0603_5% C995 C996
2 2
2

C1021

4.7U_0805_25V6-K
1 2 SI: Change D82 & D83 to LLDS package
D82 D83
B+ 2 1 2 1
2 2
RLS4148_LLDS2 RLS4148_LLDS2
C1023 C1024

+VDDA_CODEC 1 1

1U_0805_25V4Z 1U_0805_25V4Z
1

@
R934 R935
1K_0402_5% 0_0402_5%
+VCC_WOOF
3 U60 R931 1 3
2 0_1206_5%
2

24 +VCC_WOOF
VCC
BASS_OUT 1 2 1 23 C1003 1 2 1U_0603_10V4Z
C1002 0.47U_0603_16V6K INN VREF C1004
BYPASS 22 1 2 2.2U_0603_10V6K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1U_0805_25V4Z

1U_0805_25V4Z
1 2 2 INP 1 1
C1005 0.47U_0603_16V6K 1 1 C1017 C1016

R937 1 2 3
0_0402_5% GAIN0 C1008 C1009 2 2
@ R938 1 C1010 1 2 2
2 4 GAIN1 COSC 21 2 220P_0402_50V7K
0_0402_5% 20 R939 1 2 120K_0402_5%
ROSC
R940 1 2 10K_0402_5%
R633 1 2@ 0_0402_5% 5
Need check
41,45 EC_MUTE# R632 1 SHUTDOWN
40 SUB_ENABLE 2 0_0402_5% PVCC 16
7 VCLAMP PVCC 9 MV: Change L57 & L59 to 0ohm
1
14 L57 JP13
C1011 OUTP SUBWOOF+ SUBWOOF_L+
OUTP 15 1 2 1 1
1U_0805_25V4Z 0_0603_5% 2
2 SUBWOOF- SUBWOOF_L- 2
OUTN 10 1 2
R941 1 2 8 11 0_0603_5% 3
BSN OUTN GND

1000P_0402_50V7K

1000P_0402_50V7K
51_0402_5% L59 4 GND
2

MV:change to 25V R942 1 2 17 1 1

51_0402_5% BSP BAT54AW_SOT323-3~D C1012 C1013 ACES_88231-02001
@ @ CONN@
1 1
18
PGND 6
12 D44 2 2 SUB wooffer
C1014 C1015 AGND PGND
19 13
1

0.22U_0603_25V7K 0.22U_0603_25V7K AGND PGND

MV: Change C1012 & C1013 to unmount
2 2 SI: Change D44 to dual package
4 4
HPA00304PWR_TSSOP24
MV:change to 25V SI: Change C1012 & C1013 to 1000P to
reduce power consumption

Compal Electronics, Inc

Security Classification Compal Secret Data
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
SCHEMATICS,MB A4093
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 42 of 58
A B C D E
 A B C D E

Left side USB CONNECTOR 0 Left side ESATA/USB combination Connector

+5VALW +USB_VCCA
+USB_VCCA JP27 +USB_VCCA
U40 L46
1 8 W=100mils 4 3 1 WCM-2012-900T_0805 JP28
GND OUT 32 USB20_N4 4 3 USB20_N4_R VCC USB
2 IN OUT 7 2 D- 32 USB20_N2 1 1 2 2 1 B_VCC

1000P_0402_50V7K
150U_D_6.3VM

0.1U_0402_16V4Z
3 6 1 USB20_P4_R 3 USB20_N2_R 2
IN OUT D+ USB20_P2_R B_D-
1 4 EN# OC# 5 1 1 32 USB20_P4 1 1 2 2 4 GND 3 B_D+

C789
+

C790

C791
C788 9 4 3 4
THERMAL_PAD WCM-2012-900T_0805 32 USB20_P2 4 3 B_GND
5 GND
1 4.7U_0805_10V4Z TPS2061IDGN_MSOP8~N 6 L51 5 1
2 2 2 2 GND SATA_TXP5 GND
7 GND 31 SATA_TXP5 6 A+
8 SATA_TXN5 7 ESATA
D8 GND 31 SATA_TXN5 A-
8 GND SHIELD 12
+5VALW 4 2 USB20_P4_R SUYIN_020173MR004S50TZL_4P-T C792 2 1 0.01U_0402_16V7K SATA_RXN5 9 13
VIN IO1 31 SATA_RXN5_C B- SHIELD
USB_EN# C793 2 1 0.01U_0402_16V7K SATA_RXP5 10 14
31 SATA_RXP5_C B+ SHIELD
USB20_N4_R 3 1 CONN@ 11 15
IO2 GND GND SHIELD
@ PRTR5V0U2X_SOT143-4
SI: change new footprint TYCO_1759576-1

CONN@
SI: change new footprint
D11

+5VALW 4 2 SATA_TXP5
VIN IO1 D9
SATA_TXN5 3 1 +5VALW 4 2 USB20_P2_R
IO2 GND VIN IO1
@ PRTR5V0U2X_SOT143-4 USB20_N2_R3 1
IO2 GND
@ PRTR5V0U2X_SOT143-4

D12
4 2 SATA_RXN5 SI: new add for ESD
Touch screen +5VALW VIN IO1
SATA_RXP5 3 1
IO2 GND
JP18 @ PRTR5V0U2X_SOT143-4
USB Board Conn 1 1
+5VS

2 2 USB10_N12 32
3 3 USB10_P12 32
2 JP47 2
4 4
+5VALW 1 1 5 5
2 2 GND1 6
3 3 GND2 7
45 USB_EN# 4 4
5 ACES_88266-05001
32 USB20_N0 5
32 USB20_P0 6 6
7 7 CONN@
32 USB20_N1 8 8
32 USB20_P1 9 9
10 10

11 GND1
12 GND2
ACES_87213-1000G

CONN@

CONN@
ACES_87213-0800G
BT Connector
10 GND 8 8 +3VAUX_BT
7 7
6 USB20_P6
6 USB20_P6 32
5 USB20_N6
3 5 USB20_N6 32 3
4 4 BT_LED 46
3 @ R517 1
@R517 2 1K_0402_5%
3 @R518
@ R518 1 1K_0402_5% CH_DATA 37
2 2 2 CH_CLK 37
9 1
Finger printer GND 1
JP32
0612 no install
D16
1 2 SI2: change form +5VALW 4 2 USB20_P6
R622 @ 0_0603_5% VIN IO1
+3VALW Q31 +3VS +3VALW to +3VS USB20_N6 3 1
IO2 GND
S

+3VS_FB @ PRTR5V0U2X_SOT143-4
D

3 1 1 2
@ SI2301BDS_SOT23 1 R581 0_0603_5%
C832 +3VS +3VAUX_BT
0.1U_0402_16V4Z Q24 SI2301BDS_SOT23
G
2

USB_EN# MV: add PJP10

2 0.1U_0402_16V4Z

S
JP39 0.1U_0402_16V4Z

D
3 1
1 1
USB20_N7 2 2
32 USB20_N7 2

1
USB20_P7

G
32 USB20_P7 3 1 1 1 1

2
3 C798 C802 R519 C799 C800 C801
4 4
5 5 1U_0603_10V4Z 1 100K_0402_5%
D21 1 2 6 6 2 2 2 2
7

2
USB20_P7 GND
+5VALW 4 VIN IO1 2 PAD-OPEN 2x2m 8 GND 0.01U_0402_16V7K 4.7U_0805_10V4Z
USB20_N7 3 1 PJP10 ACES_85201-06051
IO2 GND CONN@ R520
@ PRTR5V0U2X_SOT143-4 1 2
31 BT_OFF
10K_0402_5%

4 4
PV: Change PN to SC300000K00 for ESD request
SI: change to 10K ohm to make
sure MOS can turn on

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 43 of 58
A B C D E
 A B C D E

+3VL
SI2: Change from +3VL to +3VALW and unmount this EEPROM
SPI Flash (8Mb*1) 1 20mils
+3VALW +3VALW C484 U29
8 VCC VSS 4
0.1U_0402_16V4Z SI2: Change from +3VALW to +3VL

1
2
1 3 W
C803
R521 7 +3VL
@ 0.1U_0402_16V4Z @ 100K_0402_5% HOLD
2 U31 SPI_CS# INT_SPI_CS#
45 SPI_CS# 1 2 1 C624

2
R221 0_0402_5% S
8 VCC A0 1
1 SPI_CLK_R 1
7 WP A1 2 45 SPI_CLK 1 2 6 C 2 1
6,45,46,54 SMB_EC_CK1 6 3 R227 33_0402_5%
SCL A2
6,45,46,54 SMB_EC_DA1 5 SDA GND 4 45 EC_SO_SPI_SI 2 1 EC_SO_SPI_SI_R 5 D Q 2 EC_SI_SPI_SO_R 2 1 EC_SI_SPI_SO 45
@ 0.1U_0402_16V4Z
R229 0_0402_5% R223 0_0402_5%
@ AT24C16AN-10SI-2.7_SO8 SST25LF080A_SO8-200mil
SPI_CLK_R SI2: chagne 0 ohm to 33ohm for EMI

5
2 SI2: Add 22p for EMI U24 R313 @ 100K_0402_5%
R385

1
2 INT_FLASH_EN# 1 2

G Vcc
R526 C794 INT_SPI_CS# B
1 2 4 Y
@ 100K_0402_5% 22P_0402_50V8J 1 SPI_CS#
1 @ 22_0402_5% A
JP50 @ NC7SZ32P5X_NL_SC70-5

3
SPI_CS# 1 2 +3VL
EC_SI_SPI_SO_R 1 2 INT_FLASH_EN#
3 3 4 4
5 6 SPI_CLK_R
31 SB_INT_FLASH_SEL 5 6
7 8 EC_SO_SPI_SI_R
7 8
@ E&T_2941-G08N-00E~D

C:Chg. PN to LTC00000200

2
LPC Debug Port 2

+3VS
JP41
1 1
2 2
3 3
4 4
5 5
6 6 CLK_14M_SIO 26
7 LPC_AD0
7 LPC_AD1
8 8
9 LPC_AD2
9 LPC_AD3
10 10
11 LPC_FRAME#
11 LPC_DRQ1#
12 12
13 PLT_RST#
13 R137 1
14 14 2 @ 0_0402_5%
15 15 CLK_PCI_SIO2 30
16 SIRQ
16
17 17
18 18
19 19
20 20

@ ACES_85201-2005

3 3

LPC Debug Port

H31
+3VALW

6 5 LPC_DRQ1# 30

7 4 PLT_RST#
30,45 SIRQ PLT_RST# 11,14,15,30,36,37,38,45

LPC_AD3 8 3 LPC_AD2
30,45 LPC_AD3 LPC_AD2 30,45

LPC_AD1 9 2 LPC_AD0
30,45 LPC_AD1 LPC_AD0 30,45

LPC_FRAME# 10 1 CLK_PCI_SIO
30,45 LPC_FRAME# CLK_PCI_SIO 30,34

2
@ DEBUG_PAD R232
22_0402_5%
@

1
2
C486
4 22P_0402_50V8J 4
1
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 44 of 58
A B C D E
 A B C D E

SI2: Change keyboard conn

+3VL_EC

0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K PV: change to BEAD for EMI request

1 1 1 1 1
KBD CONN
CONN@
C805 C806 C807 C808 C809 +3VL +3VL_EC +EC_AVCC JP33
For EMI
2 2 2 2 2 R527 KSO17 KSO17 @ C213
@C213 100P_0402_25V8K
1 1 1 2
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 2 KSO16 KSO9 @C609
@ C609 1 2 100P_0402_25V8K
FBMA-L11-201209-601LMT_0805 2 KSO15 KSO16 @C754
@ C754 100P_0402_25V8K
3 3 1 2
4 KSO10 KSI6 @C756
@ C756 1 2 100P_0402_25V8K
4 KSO11 KSO14 @C757
@ C757 100P_0402_25V8K
5 5 1 2

111
125
+3VL SI2: Change from +5VL to +3VL KSO14 KSO11 @C758
@ C758 100P_0402_25V8K

22
33
96

67
6 6 1 2

9
1 U33 KSO13 KSO10 @C759
@ C759 100P_0402_25V8K 1
7 7 1 2
SMB_EC_DA1 R528 1 2 4.7K_0402_5% BATT_OVP 2 1 8 KSO12 KSO15 @C764
@ C764 1 2 100P_0402_25V8K

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R529 8 KSO3 KSO6
1 2 4.7K_0402_5% 100P_0402_50V8J C327
9 9 @C768
@ C768 1 2 100P_0402_25V8K
+3VS 10 KSO6 KSO3 @C769
@ C769 1 2 100P_0402_25V8K
10 KSO8 KSO12 @C822
@ C822 100P_0402_25V8K
11 11 1 2
SMB_EC_DA2 R531 1 2 4.7K_0402_5% GATEA20 1 21 INV_PWM 12 KSO7 KSO13 @C823
@ C823 1 2 100P_0402_25V8K
32 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM 28 12
SMB_EC_CK2 R532 1 2 4.7K_0402_5% KB_RST# 2 23 FAN_PWM 13 KSO4 KSO2 @C824
@ C824 1 2 100P_0402_25V8K
32 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 FAN_PWM 4 13
SIRQ 3 26 14 KSO2 KSO4 @C825
@ C825 1 2 100P_0402_25V8K
30,44 SIRQ SERIRQ# FANPWM1/GPIO12 EC_BEEP 40 14
LPC_LFRAME# 4 27 ACOFF 15 KSI0 KSO7 @C826
@ C826 1 2 100P_0402_25V8K
30,44 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 49 15
C810 R530 30,44 LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K 16 KSO1 KSO8 @C875
@ C875 1 2 100P_0402_25V8K
LPC_AD2 LAD3 C812 ECAGND 16 KSO5 KSI3 @C876
@ C876 100P_0402_25V8K
1 2 1 2 30,44 LPC_AD2 7 LAD2 PWM Output 1 2 17 17 1 2
@ 33_0402_5% 30,44 LPC_AD1 LPC_AD1 8 63 BATT_TEMP 18 KSI3 KSO5 @C877
@ C877 1 2 100P_0402_25V8K
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 54 18
@ 15P_0402_50V8J LPC_AD0 BATT_OVP KSI2 KSO1 @C878
@ C878 100P_0402_25V8K
30,44 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 54 19 19
KSO0 KSI0 @C884
@ C884
1 2
100P_0402_25V8K
ADP_I/AD2/GPIO3A 65 ADP_I 49 20 20 1 2
CLK_PCI_EC 12 AD Input 66 21 KSI5 KSI4 @C885
@ C885 1 2 100P_0402_25V8K
30,34 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_ID 54 21
PLT_RST# 13 75 TP_BTN# 22 KSI4 KSI5 @C886
@ C886 1 2 100P_0402_25V8K
11,14,15,30,36,37,38,44 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 TP_BTN# 46 22
+3VL R533 1 2 ECRST# 37 76 23 KSO9 KSO0 @C887
@ C887 1 2 100P_0402_25V8K
ECRST# SELIO2#/AD5/GPIO43 ANA_MIC_DET 41 23
47K_0402_5% EC_SCI# 20 24 KSI6 KSI2 @C888
@ C888 1 2 100P_0402_25V8K
32 EC_SCI# SCI#/GPIO0E 24 KSI7 KSI1 @C889
@ C889 100P_0402_25V8K
32,34 HDARST# 38 CLKRUN#/GPIO1D 27 G1 25 25 1 2
68 28 26 KSI1 KSI7 @C890
@ C890 1 2 100P_0402_25V8K
DAC_BRIG/DA0/GPIO3C DAC_BRIG 28 G2 26
2 1 EN_DFAN1/DA1/GPIO3D 70 VCTRL 49
DA Output 71 IREF
IREF/DA2/GPIO3E IREF 49
C811 0.1U_0402_16V4Z KSI0 55 72 ACES_85201-26051
KSI0/GPIO30 DA3/GPIO3F AC_SET 49
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 41,42
KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 43
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C I2C_INT 46
KSI6 61 PS2 Interface 86
SUSP# SYSON +3VALW KSI7 62
KSI6/GPIO36 PSDAT2/GPIO4D
87 TP_CLK
MUTE_LED 47
TP_CLK 46
KB Back Light Conn
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA +5VS_LED
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 46
SI2: Change from 10K to 100K KSO1 40 JP48
KSO1/GPIO21
1

2 KSO2 2
41 KSO2/GPIO22 1 1
R536 R539 KSO3 AC_LED#
42 KSO3/GPIO23 SDICS#/GPXOA00 97 AC_LED# 54 PV:Add for AC_LED function 2 2
1

100K_0402_5% 100K_0402_5% KSO4 43 98 DOCK_VOL_UP# 47 3

R538 KSO5 KSO4/GPIO24 SDICLK/GPXOA01 3
100K_0402_5% KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 DOCK_VOL_DWN# 47 4 4
45 KSO6/GPIO26 Matrix 109 VGATE 56 5
2

KSO7 SDIDI/GPXID0 G1
46 KSO7/GPIO27 SPI Device Interface G2 6
+3VS
KSO8 47
2

KSO9 KSO8/GPIO28 ACES_85201-0405N R540

48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO 44
KSO10 49 120 TP_BTN# 1 2
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 44
LID_SW# KSO11 50 SPI Flash ROM 126 CONN@
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 44
KSO12 51 128 10K_0402_5% +5V_TP
KSO12/GPIO2C SPICS# SPI_CS# 44
KSO13 52 R534
KSO14 KSO13/GPIO2D CIR_IN TP_CLK
0205_Add Pull down 53 KSO14/GPIO2E 2 1 +5VL 1 2
R402 for SUSP#. KSO15 54 73 CIR_IN R554 10K_0402_5% 10K_0402_5%
KSO15/GPIO2F CIR_RX/GPIO40 CIR_IN 41,47
KSO16 81 74 R535
KSO17 KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG TP_DATA
82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG 49 1 2
90 10K_0402_5%
BATT_CHGI_LED#/GPIO52 STD_ADP 49
CAPS_LED#/GPIO53 91 CAPS_LED# 46
SMB_EC_CK1 77 GPIO 92 BAT_LED#
6,44,46,54 SMB_EC_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BAT_LED# 46
SMB_EC_DA1 78 93 ON/OFFBTN_LED#
6,44,46,54 SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# 46
SMB_EC_CK2 79 SM Bus 95 SYSON
6,25 SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 37,48,51
SMB_EC_DA2 80 121 VR_ON
6,25 SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 56
127 ACIN_D
AC_IN/GPIO59
2 1 PV: Change from +3VALW to +3VL
R541 10K_0402_5%
SLP_S3# 6 100 EC_RSMRST#
32 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 32
SLP_S5# 14 101 1 2 +3VL
32 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 32
+3VL EC_SMI# 15 102 R560 150K_0402_5%
32 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 48,50
LID_SW# 16 103 WL_BLUE_LED# D33
46 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 WL_BLUE_LED# 46
ESB_CLK R563 1 2 4.7K_0402_5% ESB_CLK 17 104 SB_PWRGD ACIN_D 2 1
46 ESB_CLK SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWRGD 6,32,56 AC_IN 31,49
ESB_DAT R576 1 2 4.7K_0402_5% ESB_DAT 18 GPO 105 BKOFF#
46 ESB_DAT PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 28 CH751H-40PT_SOD323-2
3
19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106
3
25 107 TP_LED#
6,32 H_THERMTRIP# EC_THERM#/GPIO11 GPXO10 TP_LED# 46
47 CONA# 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 2 1
29 C326 100P_0402_50V8J
48 VLDT_EN E51_TXD FANFB2/GPIO15
46,47 DOCK_SLP_BTN# 30 EC_TX/GPIO16
LANPWR 31 110
36 LANPWR EC_RX/GPIO17 PM_SLP_S4#/GPXID1 VFIX_EN 56
46,47 ON/OFF 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL 16
R543 34 114 EAPD_CODEC 40
46 DIM_LED PWR_LED#/GPIO19 GPXID3
+3VL 2 1 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# 31
116 SUSP#
GPXID5 SUSP# 37,40,48,49,52,55
4.7K_0402_5% C813 117 PWRBTN_OUT#
GPXID6 PWRBTN_OUT# 32
15P_0402_50V8J 118 2 1
GPXID7 PCI_SERR# 30
1 2 CRY2 122 R231 0_0402_5%
XCLK1
123 XCLK0 V18R 124 2 1 remove in MP
C814 4.7U_0805_10V4Z
Y7
1

AGND

SI: Mount C814 for KB926C

GND
GND
GND
GND
GND

3 4 @
NC OSC R545
2 1 20M_0402_5% KB926QFC0_LQFP128_14X14
EC DEBUG port
11
24
35
94
113

69

NC OSC
2

@ 32.768KHZ_12.5PF_9H03200413
JP34
1 1 2 CRY1 +3VL_EC
1 +5VL
2 LANPWR
2 E51_TXD C815
3
ECAGND

3
1

4 15P_0402_50V8J
4 L80
ACES_85205-0400 +EC_AVCC FBM-11-160808-601-T_0603

L81
2

1 2 1 2
C816 0.1U_0402_16V4Z FBM-11-160808-601-T_0603
4 4

PV: change to BEAD for EMI request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 45 of 58
A B C D E
 A B C D E

CAPS LOCK LED WHITE +5VS_LED

MDC 1.5 Conn. 45 CAPS_LED# 1

D30
2
R552
1 2
Change type 4/25
HT-F196BP5_WHITE 750_0402_5%

JP25 MV: Modify R552 change to 750ohm

1 GND1 RES0 2 +3VS
HDA_SDOUT_MDC 3 4 WHITE +5VALW_LED
32 HDA_SDOUT_MDC

32 HDA_SYNC_MDC HDA_SYNC_MDC
5
7
IAC_SDATA_OUT
GND2
RES1
3.3V 6
8
+3VS POWER LED(Left 1) D27 R549
IAC_SYNC GND3
32 HDA_SDIN1 1 R495 2 HDA_SDIN1_MDC 9 IAC_SDATA_IN GND4 10 ON/OFFBTN_LED# 1 2 1 2
32 HDA_RST#_MDC 33_0402_5% 11 12 HDA_BITCLK_MDC 32
1 IAC_RESET# IAC_BITCLK HT-F196BP5_WHITE 470_0402_5% 1
2 1 1 2
+3VS R496 C777

GND
GND
GND
GND
GND
GND
@ 10_0402_5% @ 10P_0402_25V8K

ACES_88018-124G
Battery Charge LED(Left 2)

13
14
15
16
17
18
1000P_0402_50V7K
C778

C779

0.1U_0402_16V4Z

WHITE +5VALW_LED
1 1 1
Connector for MDC Rev1.5 D28 R550
C780 1 2 1 2
45 BAT_LED#
@4.7U_0805_10V4Z CONN@
2 2 2 HT-F196BP5_WHITE 470_0402_5%
HDD LED(Left 3)
QSMF-C16E_AMBER-WHITE +5VS_LED
+5VS White

1 2 1 2

1
R551 820_0402_5%
R631

3
10K_0402_5% 3 4 1 2 +3VS
Q138B 31 GSENSOR_LED# R559 470_0402_5%

1
2N7002DW-7-F_SOT363-6

2
PJP8 5 Amber MV: Modify R551& R559 to 470 ohm
PAD-OPEN 2x2m LED1

4
6
+3VS
Q138A

2
2N7002DW-7-F_SOT363-6
1

31 SATA_LED# 2
10K_0402_5%
2 R577 +5VALW_LED +5VS_LED 2

DIM LED

1
Q32 Q58
SI2301BDS-T1-E3_SOT23-3 SI2301BDS-T1-E3_SOT23-3
2

WL_BLUE_LED# 45

S
D

D
+5VALW 3 1 +5VS 3 1

1 1

1
C836

G
2

2
R587 0.1U_0402_16V4Z C845
10K_0402_5% 0.1U_0402_16V4Z
1

D 2 2
2 Q55
43 BT_LED

2
G 2N7002_SOT23-3
S
3
1

PV: Add LDO for ENE cap board

R505
100K_0402_5%

1
APL5151-33BC-TRL_SOT23-5 D
2 Q51
45 DIM_LED
2

+5VL 1 2 3 4 1 2 G 2N7002_SOT23-3
R578 10K_0402_5% EN BP
S

3
D15 @ 2 C185 @ 0.33U_0603_10V7K
GND
37 WL_LED# 1 2 1
1 VIN VOUT 5 1 2 +3VL_LDO
CH751H-40PT_SOD323-2 C795 R248 0_0603_5%
PV: change from MOS to Diode 1U_0402_6.3V4Z U55 @ @
2
SI: Change to +3VL to support Qplay
@ bottom boot in BATT mode

+3VL 1 2
3
T/P Board (Inculde T/P_ON/OFF) R247 0_0603_5%
SWITCH BOARD. +5VS_LED
+3VL_LDO SI2: add 4.7u for
Cypress cap board 3

1 2

PV: Change PN to SCA00000G00 for ESD request MV: Add cap for ENE board EMI C502 4.7U_0805_10V4Z
PV: change from Q85 to R235
TP_DATA TP_BTN# JP36
SI: Add +5VALW_LED to support
TP_CLK TP_LED# 1 2 PV: Add for EMI PWR LED S3 flash function 1
R235 0_0603_5% +5VS_LED 1
2 2
3

+5VALW +5V_TP ON/OFFBTN_LED# 3

45 ON/OFFBTN_LED# 3
D31 D32 R603 1 2 0_0402_5% R610 1 2 FBMA-11-100505-301T_0402 CAP_CLK 4
45 ESB_CLK 4
PSOT24C_SOT23-3 PSOT24C_SOT23-3 @ SI2301BDS-T1-E3_SOT23-3 R604 1 2 0_0402_5% R611 1 2 FBMA-11-100505-301T_0402 CAP_DAT 5
45 ESB_DAT 5
+5V_TP @ I2C_INT 6
45 I2C_INT 6
S

R_PWR_LED
D

3 1 +5VALW_LED 1 2 7 7
R705 1.8K_0402_5% LID_SW# 8
45 LID_SW#
1

ON/OFF 8
45,47 ON/OFF 9 9
1 @ Q85 R605 1 0_0402_5% 10
G

6,44,45,54 SMB_EC_CK1 2
2

C819 R606 1 0_0402_5% 11 10

6,44,45,54 SMB_EC_DA1 2 11 GND 13
12 12 GND 14
0.1U_0402_16V4Z
2 47,48,53 SYSON#
JP37 MV:R705 change to 1.8Kohm
1 ACES_85201-1205N
1 CONN@
2 2 +5VS_LED
3 ON/OFF PV: change to 12pin
3 TP_CLK ON/OFFBTN_LED#
4 4 TP_CLK 45
5 TP_DATA TP_DATA 45
5

2
6 TP_BTN# TP_BTN# 45 33P_0402_50V8K 2 1 C947 CAP_CLK
6 TP_LED# D38 0.1U_0402_16V4Z @ C192 +3VL_LDO
7 7 TP_LED# 45 2 1
8 PSOT24C_SOT23-3 0.1U_0402_16V4Z 2 1 @ C191 +5VS_LED
8 @ 0.1U_0402_16V4Z @ C186 ON/OFFBTN_LED#
GND 9 1 1 2 1
@ 10 @ 0.1U_0402_16V4Z 2 1 @ C187 I2C_INT
4 GND C820 C821 0.1U_0402_16V4Z @ C188 R_PWR_LED 4
2 1

1
ACES_85201-08051 100P_0402_50V8J 100P_0402_50V8J 0.1U_0402_16V4Z 2 1 @ C189 LID_SW#
2 2 0.047U_0402_16V7K @ C190 ON/OFF
2 1
CONN@ SI2: Add diode for EMI

MV: Add cap for ENE board EMI

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 46 of 58
A B C D E
 A B C D E

Atlas/ Saturn Dock

+DOCKVIN JP38

43 +3VS
43
44 44 DOCK_VOL_UP# 2 1
R589 10K_0402_5%
40 39 DOCK_VOL_DWN# 2 1
27 GREEN_L 40 39
<BOM Structure> D43 38 37 R590 10K_0402_5%
27 RED_L 38 37
+5VS 1 2 2 D_DDCDATA 36 35
27 D_DDCDATA 36 35
R586 1K_0402_5% 1 DOCK_PWR_ON 34 33
27 BLUE_L 34 33
+3VALW 1 2 3 D_HSYNC 32 31
27 D_HSYNC 32 31
R585 1K_0402_5% D_DDCCLK 30 29 CIR_IN
1 27 D_DDCCLK 30 29 CIR_IN 41,45 1
DAN202U_SC70 USB20_N3 28 27 DOCK_PWR_ON
32 USB20_N3 28 27

6
Q145A D_VSYNC 26 25 MUTELED 1 2 MUTE_LED 45
27 D_VSYNC 26 25

2
2N7002DW-7-F_SOT363-6 24 23 DOCK_SLP_BTN# R591 1K_0402_5%
24 23 DOCK_SLP_BTN# 45,46
R588 USB20_P3 22 21
32 USB20_P3 22 21 JACK_DET# 40,41
2 10K_0402_5% RJ45_MIDI3+ 20 19 R_VOL_UP# R567 1 2 200_0402_5% DOCK_VOL_UP# DOCK_VOL_UP# 45
46,48,53 SYSON# 36 RJ45_MIDI3+ 20 19
RJ45_MIDI3- 18 17 R_VOL_DWN# R568 1 2 200_0402_5% DOCK_VOL_DWN# DOCK_VOL_DWN# 45
36 RJ45_MIDI3- 18 17
RJ45_MIDI2+ 16 15 SPDIFO_L
36 RJ45_MIDI2+
1

1
RJ45_MIDI2- 16 15 AUDIO_OGND
36 RJ45_MIDI2- 14 14 13 13
RJ45_MIDI1+ 12 11 DOCK_LOUT_R DOCK_LOUT_R 41
36 RJ45_MIDI1+ 12 11
RJ45_MIDI1- 10 9 DOCK_LOUT_L DOCK_LOUT_L 41
36 RJ45_MIDI1- 10 9
RJ45_MIDI0+ 8 7 DOCK_MIC_R_C
36 RJ45_MIDI0+ 8 7
RJ45_MIDI0- DOCK_MIC_L_C
DOCK_PWR_ON Spec 36 RJ45_MIDI0-
+V_BATTERY
6
4
6 5 5
3 AUDIO_IGND
4 3
0V = Notebook S4/S5, Dock off PJP5 2 2 1 1 DOCK_PRESENT

2.5V = Notebook S3, Dock on B+ 1 2

41 45
4V = Notebook S0, Dock on @
PAD-OPEN 2x2m 42
41
42
SHIELD
SHIELD 46

FOX_QL1122L-H212AR-7F
CONN@

need change to reverse type connector

+1.5VS
+3VL

2
2

R574
R565 @ 33_0402_5%
2 2
10K_0402_5%

1 1
SI2:chang R572 to 22 ohm & R566 to
1

C
2K to fix dock usb issue CONA# 45
Q7 2 1 2 1 2 SPDIF_OUT 40
3

220P_0402_50V7K
@ MMBT3904_NL_SOT23-3 B 0.1U_0402_16V7K R647 150_0402_5%

1
Q145B E C894

3
R572 2N7002DW-7-F_SOT363-6 R575 1 R573

C944
DOCK_PRESENT 1 2 22_0402_5% 5 SPDIFO_L 1 2 110_0402_5%

DOCK_LOUT_R
4

2
0_0402_5%
1

DOCK_LOUT_L 2
R566 1 1

220P_0402_50V7K

220P_0402_50V7K
2K_0402_1%

C942

C943
2

2 2

0720 Add dock_present_gnd

R_VOL_UP# R_VOL_DWN#

1 1
C843 C844

3 MIC_Dock Need 600 Ohm 500 mA 2

1000P_0402_50V7K
2
1000P_0402_50V7K
3

L94
FBM-11-160808-601-T_0603
40 DOCK_MIC_R 1 2 DOCK_MIC_R_C

40 DOCK_MIC_L 1 2 DOCK_MIC_L_C
L93
FBM-11-160808-601-T_0603 1 1
C922
C921
220P_0402_50V7K 2 2 220P_0402_50V7K

+3VS

10K_0402_5%
2

SENSE_B# 40
R915
2

R914 D
1

10K_0402_5% 2 Q100
G 2N7002_SOT23-3
1

C S
1

2
R912 MMBT3904_NL_SOT23-3 B
1

10K_0402_5% C E Q18
3

DOCK_MIC_L_C 1 2 2 Q16
4 B MMBT3904_NL_SOT23-3 4
2

2 E
3

R913
47K_0402_5% C978
1
1

1U_0603_10V6K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 47 of 58
A B C D E
 A B C D E

H1 H2 H3 H4
+5VALW TO +5VS H_4P5X3P0N H_7P0X5P0N H_3P4N 3P0N
+3VALW TO +3VS
+5VALW +5VS @ @ @ @
4.7U_0805_10V4Z +3VALW +3VS

1
1 1
1 Q35 C833 C835 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 1
1 1
8 1 Q14 C839 C838 4.7U_0805_10V4Z H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
D S
7 D S 2 8 D S 1
2 2 @ @ @ @ @ @ @ @ @ @
6 D S 3 7 D S 2
2 2
5 4 6 3

1
D G 1U_0402_6.3V4Z D S
5 D G 4
SI4800BDY_SO8 1U_0402_6.3V4Z
4.7U_0805_10V4Z

1 SI4800BDY_SO8 RUNON 2 R152 1 B+

0.01U_0402_25V7K
4.7U_0805_10V4Z
1 1 750K_0402_1% H15 H16 H18 H19 H20 H26
C864 RUNON H_3P0 H_3P0 H_3P0 H_3P0 H_3P7 H_3P7

1
C840 D
2 C834 Q17 SUSP @ @ @ @ @ @
2
2 2 2N7002_SOT23-3
G

1
S

3
H21 H22 H23 H24
4P0 4P0 4P0 4P0

@ @ @ @

1
+1.8V TO +1.8VS
H27 H25 H33
+1.2VALW TO +1.2V_HT H_4P0 H_3P0 H_4P0
+1.8V +1.8VS
+1.2VALW +1.2V_HT @ @ @ CF1 CF2 CF3 CF4
1 1 1 1

1
Q4 1 2 Q11 1 1
IRF8113PBF_SO8 C848 IRF8113PBF_SO8 C846 C862 4.7U_0805_10V4Z
2 C841 2
8 1 8 1
7 2 10U_0805_10V4Z 7 2
2 1 2 2
6 3 6 3
5 5
1U_0402_6.3V4Z 1U_0402_6.3V4Z
4.7U_0805_10V4Z

1
4

4
4.7U_0805_10V4Z 1
C842 2 R233 1 B+

0.01U_0402_25V7K
C847 1 330K_0402_5%

1
2 1.8VS_ENABLE R138 2 +5VL +5VL
1 B+

1
2 D
0.01U_0402_25V7K

1 750K_0402_1% R808
1

10M_0402_5% C837 2 Q12 VLDT_EN#

1

1
R809 D Q13 2 G 2N7002_SOT23-3
10M_0402_5% C849 2 SUSP S R595 R596
2

3
2 2N7002_SOT23-3
G
S 100K_0402_5% 100K_0402_5%
2

2
SI2: Add this resistor to meet MOS voltage SYSON# SUSP
46,47,53 SYSON# SUSP 53
SI2: Add this resistor to meet MOS voltage

6
Q142B Q142A
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6
37,45,51 SYSON 5 2 SUSP# 37,40,45,49,52,55

1
Discharge circuit
+5VS +1.8VS +1.2V_HT +1.8V +1.2VALW
3 3
2

2
R239 R279 R280 R284 R368
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5%
@
1

1
1

D D D D D
SUSP 2 Q46 SUSP 2 Q48 VLDT_EN# 2 Q37 SYSON# 2 Q41 EC_ON# 2 Q42
G 2N7002_SOT23-3 G 2N7002_SOT23-3 G 2N7002_SOT23-3 G 2N7002_SOT23-3 G 2N7002_SOT23-3
S S S S S @
3

+5VL +5VL

1
R597 R598
100K_0402_5% 100K_0402_5%

2
+3VS +0.9V
+1.5VS +1.1VS VLDT_EN# EC_ON#
2

3
R288 R292
470_0805_5% 470_0805_5% R293 R294 Q143A Q143B
470_0805_5% 470_0805_5% 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6
VLDT_EN 2 5
45 VLDT_EN EC_ON 45,50
1

4
1

D D
1

4 SUSP Q47 SYSON# Q49 D D 4

2 2
G 2N7002_SOT23-3 G 2N7002_SOT23-3 SUSP 2 Q50 SUSP 2 Q52
S S G 2N7002_SOT23-3 G 2N7002_SOT23-3
3

S S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 48 of 58
A B C D E
 A B C D

+3VALW +3VL

PQ3

1
TP0610K-T1-E3_SOT23-3

3
PR9
100K_0402_5%

2
2 AC_LED#46 BATT
1 1

499K_0402_1% 340K_0402_1%
ADP_ID 41

PR1 1
+5VALW
PC12
2 1

0.01U_0402_50V7K

0.01U_0402_16V7K
PD4

1
PR8 PC13

2
2K_0402_5% PR2 820P_0402_25V7

1
10K_0402_5%

PC1
+DOCKVIN

PR4 1
1

2
ACES_88334-057N RLZ3.6B_LL34

2
5
ADP_SIGNAL 1
PR3
2 VIN
5 10K_0402_5%
4

2
4

8
3 PL1 PL2 PR5
3 SMB3025500YA_2P SMB3025500YA_2P 10K_0402_5%
2 3

P
2 ADPIN +
1 1 1 2 2 1 0 1 2 1 BATT_OVP 41
2 -

G
PJP1

105K_0402_1%
PR6 1
1000P_0402_50V7K

0.01U_0402_25V7K

4
1
820P_0402_25V7
PU1A
2

1000P_0402_50V7K

PC6
PD1 LM358ADT_SO8
1

1
PC5

2
PC2

PC4
PC3

2
820P_0402_25V7
2

2
@ PJSOT24C_SOT23-3
1

2 2

VMB
PL3 BATT
PJP2 SMB3025500YA_2P
1 1 1 2
2 2
3 EC_SMD PD2
3 EC_SMC @ SM05_SOT23
4 4
5 3
PH1 under CPU botten side :
5
1

1
6 6
7 2
1 CPU thermal protection at 90 +-3 degree C
7 PC9
8 PC8
2

2
8 1000P_0402_50V7K 0.01U_0402_25V7K
GND 9
10 PR7
GND
3

+5VS 604K_0402_1%
@ SUYIN_200275MR008GXOLZR
3
CPU 1 2
3
1
1

PD3
1

1
PR14 @ SM24.TC_SOT23-3
PR13 100_0402_5% PH1
100_0402_5% 10K_TH11-3H103FT_0603_1%
2
2

SMB_EC_DA1 SMB_EC_DA1 6,40,41 PU1B ENTRIP1 47

2
PR10 LM358ADT_SO8

8
200K_0402_1%

1
SMB_EC_CK1 D
1 2 5

P
SMB_EC_CK1 6,40,41 +
7 2 PQ1
0 G @SSM3K7002FU_SC70-3
+5VALW 1 2 6 -

G
BAT_ID 46 PR11 S

3
1 150K_0402_1%

4
1

1
+3VL PC10 PR12
PR16 2.4K_0402_1%
6.49K_0402_1% 0.22U_0603_10V7K PR15 PC11
2

1 2 150K_0402_1% 1000P_0402_50V7K
2

2
EN0 6,47

2
1

1
PR17 D
1K_0402_5% 2 PQ2
G SSM3K7002FU_SC70-3
2

BATT_TEMP 41 S

3
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 49 of 58
A B C D
 A B C D

P4 B+

BATT
VIN P2
PQ102
SI4835BDY-T1-E3 1P SO8
PQ103 1 8
PQ101 AO4407_SO8 PR102 PL101
1
2 7 1
SI4835BDY-T1-E3 1P SO8 0.012_2512_1% HCB2012KF-121T50_0805 3 6
8 1 1 8 1 2 1 2 CHG_B+ 5
7 2 2 7 PR103
6 3 3 6 47K_0402_5%

4
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5 5 1 2 1 2 VIN
PR101

1
47P_0402_50V8J

47K_0402_5% PR104 ACDET PC102

1
PC103

PC104

PC105
0.1U_0603_25V7K
1 2 0_0402_5% 1U_0603_6.3V6M
41 AC_SET 1 2 ACSET

2
1

3
DTA144EUA_SC70-3 PR105
PC101

1
PQ104 10K_0402_5%

0.1U_0603_16V7K

PC108
1

1
2

2
1
PC109

200K_0402_5%
2 PC107 PR140 ACOFF#

2
PC106

PR106
@ 0.01U_0402_16V7K @ 0.1U_0603_25V7K

2
1

1
100K_0402_5% CHG_B+

2
CHGEN#

2
PR107 PR108
47K_0402_1% 10_1206_5%
1

1
1 2 2 1 2 2 ACOFF 41

ACP
LPREF

ACSET

ACDET

LPMD

ACN

CHGEN
TP 29

5
6
7
8
PQ105 PR110 PC110
DTC115EUA_SC70-3 0_0402_5% 1U_0805_25V6K
3

3
1

D PR109 PQ106
33,36,41,44,49 SUSP# 1 2 8 IADSLP PVCC 28 1 2
2 PQ107 150K_0402_5% PC111 DTC115EUA_SC70-3
G 0.1U_0402_10V7K PQ108

2
S SSM3K7002FU_SC70-3 9 27 BST_CHG 1 2 4 AO4466_SO8
3

AGND BTST
PC112 BQ24740VREF PU101

PACIN_1
1 2 10 VREF
BQ24740RHDR_QFN28_5X5
HIDRV 26 DH_CHG
PL102 PR112
BATT

3
2
1
1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
PR111 11 25 LX_CHG 1 2 1 2
VDAC PH
1

3K_0402_1% D

1
PACIN 1 2 2 PQ109 PD102

5
6
7
8
G SSM3K7002FU_SC70-3 PR113 VADJ 12 24 REGN 2 1
143K_0402_1% VADJ REGN
S
3

ACOFF# PR114 RLS4148_LL34-2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1 2 2

@ 0_0402_5% 13 23 DL_CHG
2
EXTPWR LODRV

1
PD101 41 VCTRL 1 2 PQ110

PC113

PC114

PC115

PC116
RLS4148_LL34-2 4 AO4468_SO8
1

14 22

2
ISYNSET PGND
1

DPMDET
1
PC117 PR115

IADAPT
1 2

SRSET

CELLS

1
1U_0603_10V6K 100K_0402_1% PC119

SRN

SRP
2

3
2
1
BAT
PR116
2

39K_0402_5% 1U_0603_10V6K PC118

2
0.1U_0402_10V7K

15

16

17

18

19

20

21
PR117
100K_0402_5%

IADAPT
1 2 BQ24740VREF
PR118
Charge Detector

1
10K_0402_5%
1 2
41 ADP_I 47K_0402_5%
PR119

100P_0402_50V8J
0.22U_0603_10V7K
1

1
D

2
PC120

PC121
PQ111 2 BAT_ID 45
SSM3K7002FU_SC70-3 G

BATT
2

2
S

3
VIN

0.1U_0603_25V7K

0.1U_0603_25V7K
PR120
2 1 IREF 41
2

PC122
PC124
133K_0402_1%

1
PD104 PC123
1

RLS4148_LL34-2 0.1U_0402_10V7K PR122

2
PR121 1M_0402_5%
200K_0402_1% 1 2
1

PR123 @
2

1M_0402_5%
3
1 2 3
VIN_1

PR124
+3VL VIN 1K_0402_5%
VIN
1 2
1

+3VL AC_IN 28,41,47

1
PR125
47_1206_5% PR126
1
10K_0402_5%

133K_0402_1% PR127
VIN PR130 10K_0402_1%
2

8
+3VL
10K_0402_1%

PR128

2.15K_0402_1% PU102B

2
1 2 5

P
+
1

PR129

7 PACIN
2

O
1

PACIN
100K_0402_5%

PR131 6 -

G
133K_0402_1% PC125 CHGEN#
2

1
PR132

0.1U_0603_25V7K PC126 LM393DG_SO8

PR133
2

1
0.047U_0402_16V7K 10K_0603_0.1%
2

PR134
2

2
1

D PD103
3 10K_0402_5%
P

2
+ PQ112 RLZ4.3B_LL34
O 1 2
1

2 G SSM3K7002FU_SC70-3

2
-
G

PU102A S
PR135
3

LM393DG_SO8 FSTCHG#
4

10K_0603_0.1% PR136
60.4K_0402_1%
2

D VIN_1
1 2
1.24VREF 41 FSTCHG 2 PQ113
G SSM3K7002FU_SC70-3
S
3

STD_ADP 41
PU103

4 REF CATHODE 3 1.24VREF

1 2 ACDET

1
PC127 2
PR137 NC
22P_0402_50V8J
1

100K_0402_1%

4
20K_0402_1% 5 1
4

2
ANODE NC
PR138

LMV431ACM5X_SOT23-5
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 50 of 58
A B C D
 A B C D E

2VREF_51125

0.22U_0603_10V7K

1
1 1

PC302

2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 19.6K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PR305 PR306

1
105K_0402_1% 130K_0402_1%
1

1
PC301

PC303

PC304

PC305

PC313
10U_0805_6.3V6M
1 2 1 2

2
2

5
6
7
8
PC306
PU301

8
7
6
5

VREF
ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
25 PQ302
2
P PAD AO4466_SO8 2

2
PQ301
AO4466_SO8 7 24 4
VO2 VO1
4

UG1_5V
PR308 PC308

UG1_3V
8 VREG3 PGOOD 23
PR307 0_0402_5% 0.1U_0402_10V7K
OCP=4.59(min) PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310

3
2
1
0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
1
2
3

MOSTemperature Factor=1.3 (100C) PL302 1 2 PC307 UG_3V 10 21 UG_5V 1 2 PL303

4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 10U_LF919AS-100M-P3_4.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
8
7
6
5

5
6
7
8
LG_3V 12 19 LG_5V +5VALWP
DRVL2 DRVL1
+3VL

SKIPSEL

150U_D_6.3VM
VREG5
1

VCLK
GND
1

EN0

VIN

100K_0402_5%
+
PC309
150U_D_6.3VM

PQ303

1
+

PC310
AO4468_SO8 4 4

13

14

15

16

17

18
2

PR316
TPS51125RGER_QFN24_4X4
2
6,45 EN0
VL
1
2
3

3
2
1
PQ304

@
@620K_0402_5%
FDS6690AS_NL_SO8

1
1 2 1 2 3/5V_OK 49

1
PR311

PC311
10U_0805_10V6K
PR312 PR318 0_0402_5%

1
@ 0_0402_5%

2
3 PR317 3
45 ENTRIP1 6,45 ENTRIP2
0_0402_5%
OCP=7.644(min)

1
B++ MOSTemperature Factor=1.3 (100C)

0.1U_0603_25V7K
2
PC312
2VREF_51125
1

D D
PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

VL +5VL
PJP304
PJP302
1 2 VL 2 1
+5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
PR313 PAD-OPEN 2x2m
PQ308 100K_0402_5%
PAD-OPEN 4x4m
1

SSM3K7002FU_SC70-3 D D PQ307
PACIN_1 1 2 2 2
PJP303 +3VLP +3VL
41,44 G G EC_ON 41,44 1 2 +3VALW (3A,120mils ,Via NO.= 6) PJP301
PR315 SSM3K7002FU_SC70-3 +3VALWP
S S 2 1
3

3
1

PC314
0.047U_0603_16V7K

604K_0402_1%
PAD-OPEN 4x4m
1

PAD-OPEN 2x2m
2

100K_0402_5%
4 PR314 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 51 of 58
A B C D E
 A B C D

1 1

PL401
PR401
0_0402_5% HCB1608KF-121T30_0603
1 2 1.8V_B+ 1 2 B+
33,41,42,44 SYSON
1

3300P_0402_50V7-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

2200P_0402_50V7K
PC401

1
@ 1000P_0402_50V7K
2

1
PC408

PC406

PC403

PC412

PC404
PC405
680P_0402_50V7K
PC407

2
+5VALW

2
5
6
7
8
BST_1.8V
1+5VALW

1 2 1 2
PQ401
PR404 AO4466_SO8
0_0402_5% 0.1U_0402_10V7K

PR403 DH_1.8V

15

14
4

1
316_0402_1% PU401
PR405

EN_PSV

TP

VBST
2 255K_0402_1% 2
2

1 2 2 13 DH_1.8V_1 1 2 PL402

3
2
1
TON DRVH PR407 0_0402_5% 2.2UH_PCMC063T-2R2MN_8A_20%
PR406
+1.8VP 2 1 3 12 LX_1.8V 1 2 +1.8VP
VOUT LL
0_0402_5%
4 V5FILT TRIP 11 1 2

5
6
7
8

1
OCP=9.8913(min)
5 10 +5VALW PR408 10.5K_0402_1% PQ402 PR410

D
D
D
D
VFB V5DRV FDS6670AS_NL_SO8 @ 4.7_1206_5% 1
MOSTemperature Factor=1.3 (100C)
1

330U_4V_M
PC411 6 9 DL_1.8V PC415
PGOOD DRVL

PGND
+

PC409
1U_0603_10V6K 4.7U_0805_10V6K

GND

2
4
2

2
+1.8VP G PC410
@ 680P_0603_50V7K 2
PR411 7

1
S
S
S
1 2
14.3K_0603_0.1% TPS51117RGYR_QFN14_3.5x3.5

3
2
1
1 2
PC413
@ 10P_0402_50V8J
1

PR409
10K_0603_0.1%
2

3 3

PJP401

+1.8VP 1 2 +1.8V (7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 52 of 58
A B C D
 5 4 3 2 1

D D
PR501 PR502 PR503 PR504
11.5K_0402_1% 18.7K_0402_1% 24.9K_0402_1% 11.5K_0402_1%

+1.2VALWP 1 2 1 2 2 1 2 1 +1.1VSP
B+++

B+++

2
PR505 B+++ B+
0_0402_5% PL502

2200P_0402_50V7K
HCB2012KF-121T50_0805
4.7U_0805_25V6-K

2 1

1
1

1
PC501

PC502
2

4.7U_0805_25V6-K
2200P_0402_50V7K
4.7U_0805_25V6-K
1.1VS_POK 18

8
7
6
5

5
6
7
8
PU501

1
PC503 PQ502

VO2

VFB2

TONSEL

VFB1

VO1
GND

PC516
25 0.022U_0603_25V7K AO4466_SO8
P PAD

PC504

PC505
PQ501

2
AO4466_SO8 4 7 24 4
C
PGOOD2 PGOOD1 C
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
+1.2VALWP 0.1U_0402_10V7K 0_0402_5% 0_0402_5%
2 1 2 1 BST_1.2V 9 22 BST_1.1V 2 1 1 2
1
2
3

3
2
1
VBST2 VBST1
PL503 UG1_1.2V 2 1 UG_1.2V 10 21 UG_1.1V 2 1 UG1_1.1V PL501 +1.1VSP
3.3UH_SIQB74B-3R3PF_5.9A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 2.2UH_PCMC063T-2R2MN_8A_20%
2 1 LX_1.2V 11 20 LX_1.1V 0_0402_5% 1 2
LL2 LL1
LG_1.2V 12 19 LG_1.1V
DR VL2 DR VL1
8
7
6
5

PC509

5
6
7
8
PGND2

PGND1
1

V5FILT
2

TRIP2

TRIP1
4.7U_0805_6.3V6K

V5IN
1

PC508 + PR515

2
220U_D2_4VM 1K_0402_5% +
4 TPS51124RGER_QFN24_4x4 PC510 PC511
2

13

14

15

16

17

18
2 PQ503 4.7U_0805_6.3V6K 220U_6.3VM_R15
4
1

1
2
AO4468_SO8 PQ504

1
1
2
3

PR511 AO4468_SO8

3
2
1
10.7K_0402_1% PR510
OCP=4.487(min) 1 2 13K_0402_1%
OCP=9.6(min)

2
MOSTemperature Factor=1.3 (100C)
MOSTemperature Factor=1.3 (100C)

B PR512 B
1 2 +5VALW
0_0402_5%
1 2 PR514 PR513
47 3/5V_OK 3.3_0402_5% 21K_0402_1%
1 2
SUSP# 33,36,41,44,46
1

1
PC514 PC515
1U_0603_10V6K 4.7U_0805_10V6K

1
PC513
2

2
1

PC512 0.1U_0402_10V7K
@ 0.1U_0402_10V7K

2
2

PJP501
+1.1VSP 1 2 +1.1VS (6A,240mils ,Via NO.=12)
PAD-OPEN 4x4m

PJP502
+1.2VALWP 1 2 +1.2VALW (4A,160mils ,Via NO.=8)
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 53 of 58
5 4 3 2 1
 5 4 3 2 1

D D

+1.8V
+1.8V

PU601
1 6 PU603
VIN VCNTL +5VALW

10U_0805_10V6K
1 VIN VCNTL 6 +5VALW

10U_0805_10V6K
2 GND NC 5

PC602
2 GND NC 5

PC609
PC601 3 7
VREF NC

1
10U_0805_10V6K PC613 3 7

2
VREF NC

1
PR601 PC603
4 8 10U_0805_10V6K

2
1K_0402_1% VOUT NC 1U_0603_10V6K PR606 PC612
4 8

2
1K_0402_1% VOUT NC 1U_0603_10V6K
9

2
@ TP
9

2
G2992F1U_SO8 @ TP
PR602 G2992F1U_SO8
1 2 VREF1.5V
43,44 SYSON#
+0.9VP

1
0_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K
+1.5VSP

1
PQ601
SSM3K7002FU_SC70-3 PR603 PQ602

1
D

PC604
1K_0402_1% SSM3K7002FU_SC70-3 PR607

1
PC605 D
18,44 SUSP 1 2 2 5.1K_0402_1%

2
G 10U_0805_10V6K 1 2 2 PC614
PR604 18,44 SUSP

PC611
@ 0_0402_5% S PR608 G 10U_0805_10V6K

2
1
0_0402_5% S

3
1
C PC606 C

2
@ 0.1U_0402_10V7K PC610

2
@ 0.1U_0402_10V7K

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3 +2.5VSP

B PJP601 +3VS B
2 IN OUT 3
(2A,80mils ,Via NO.= 4)

4.7U_0805_6.3V6K
+0.9VP 1 2 +0.9V 1U_0603_6.3V6M
1

1
GND
PAD-OPEN 3x3m
PC607

PC608
PR605
PJP602 1 @150_1206_5%
2

2
+2.5VSP 1 2 +2.5VS (500mA,40mils ,Via NO.= 1)

2
PAD-OPEN 3x3m

PJP603

+1.5VSP 1 2 +1.5VS (1A,40mils ,Via NO.= 2)

PAD-OPEN 3x3m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 54 of 58
5 4 3 2 1
 5 4 3 2 1

PL201

4.7UH_SIQB74B-4R7PF_4A_20%

+CPU_CORE_NB 2 1

PQ201 PQ202
1
6 VDD_NB_FB_H AO4468_SO8 AO4466_SO8

10U_0805_10V6K
1
+ PC202 1 8 1 8 CPU_B+
220U_B2_2.5VM

PC201
2 7 2 7
<BOM Structure> 3 6 3 6

1
2 PC204
5 5
4.7U_0805_25V6-K
6 VDD_NB_FB_L

2
D D
ISL6265_PWROK

2
PC203
PR203 2200P_0402_50V7K
PR204 0_0402_5%
22K_0402_1%
1 2
SSM3K7002FU_SC70-3

UGATE NB 1
PHASE NB
LGATE NB
1 2
1

D PC205
VFIX_EN
PQ115

2 1000P_0402_50V7K
6,27,41 G
PR205

0_0402_5%
S
3

0_0402_5%
Connect to EC Pin 110. 2_0402_5%
+5VS 1 2

1
B+
CPU_B+

1
PC207 PL202

1200P_0402_50V7K
0.1U_0402_10V7K PC206 SMB3025500YA_2P

33P_0402_50V8K
2

1
0.1U_0603_16V7K

14K_0402_1%

2
1
PC209

PC208
2 1
+5VS

PR207

BOOT_NB1
1

1
PR208

2200P_0402_50V7K

1000P_0402_50V7K
2_0402_5% 1 1

1
820P_0402_50V7K
1 2

3300P_0402_50V7-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

68U_25V_M_R0.44

68U_25V_M_R0.44
CPU_B+

1
+ +

PR206

PR209

PC241

PC242

PC235

PC234

PC212

PC213

PC214

PC240

PC211

PC215
PC210
2.2U_0603_6.3V6K

44.2K_0402_1%

2
1

2
2 2

PR210
PC216 PR211

5
6
7
8
0.1U_0603_25V7K 1_0603_5% <BOM Structure>
2

D
D
D
D
VSEN_NB

RTN_NB
+5VS
2

2
1 2 PQ203
+3VS PR212

UGATE NB
PHASE NB
LGATE NB

G
S
S
S
0_0402_5% AO4474 1N SO8
1 2

BOOT_NB

4
3
2
1
PR213
C @ 0_0402_5% 2.2_0603_5% 0.22U_0603_10V7K UGATE0_1 C
1 2 PR214 PC217 0.36UH_PCMC104T-R36MN1R17_30A_20%
1
10K_0402_1%

48

47

46

45

44

43

42

41

40

39

38

37
1 2 1 2 2 1 +CPU_CORE_0
PR215 PU201

5
6
7
8

5
6
7
8

1
PR216

@ 10K_0402_5% PL203

4.7_1206_5%

16.5K_0402_1%
VIN

VCC

FB_NB

FSET_NB
COMP_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB

PR220

PR221
1 2

BOOT0
0_0603_5%
2

1 36 PR219
OFS/VFIXEN BOOT_NB PR217

680P_0603_50V8J
1 2

2
2 35 4 4 4.02K_0402_1%
41 VGATE PGOOD BOOT0

PC218
PR242 1 @ 100K_0402_5%
2 PQ204 1 2
6,27,41 H_PWRGD 1 2 ISL6265_PWROK 3 34 UGATE0 AO4714 1N SO8
6,27,41 SB_PWRGD PR234 100K_0402_5% PWROK UGATE0 PQ205 PC219 1 2

2
1 2 SVD 4 33 PHASE0 AO4714 1N SO8 0.1U_0603_25V7K

3
2
1

3
2
1
6 CPU_SVD PR218 0_0402_5% SVD PHASE0 ISP 0
1 2 SVC 5 32
6 CPU_SVC PR222 0_0402_5% SVC PGND0
6 31 LGATE0 CPU_B+
41 VR_ON PR223 PR224 ENABLE LGATE0

2200P_0402_50V7K

4.7U_0805_25V6-K
5
6
7
8

820P_0402_50V7K

3300P_0402_50V7-K
1 2 1 2 7 30

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
RBIAS PVCC PQ206

D
D
D
D

1
PC221

PC222

PC237

PC236

PC243

PC244
34.8K_0402_1%~N 82.5K_0402_1% 8 29 LGATE1 AO4474 1N SO8
OCSET LGATE1

PC220
PR225 PC223 9 28

2
VDIFF0 PGND1

G
S
S
S
1 2 1 2 ISL6265IRZ-T_QFN48_6X6
10 27 PHASE1

4
3
2
1
255_0402_1% 4700P_0402_25V7K FB0 PHASE1 PR226
PR227 11 26 UGATE1 1 2 UGATE1_1
COMP0 UGATE1 0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
12 25 BOOT1 1 2 1 2 2 1 +CPU_CORE_1
1K_0402_1% VW0 BOOT1 PR228 PL204
COMP1
VDIFF1
VSEN0

VSEN1

5
6
7
8

5
6
7
8

1
RTN0

RTN1

2.2_0603_5% PC224
ISN0

ISN1
ISP0

ISP1
VW1

1
FB1

0.22U_0603_10V7K PR229

16.5K_0402_1%
TP

4.7_1206_5%

PR231
PR230 PC225 PQ207 PQ208
1 2 1 2
13

+CPU_CORE_014

15

16

17

18

19

20

21

22

23

24

49

1 2
54.9K_0402_1% 1200P_0402_50V7K PR232 4 4 AO4714 1N SO8

2
1 2 1 2 PR233
PC227 PC226 4.02K_0402_1%
B 180P_0402_50V8J 6.81K_0402_1% +CPU_CORE_1 680P_0603_50V8J B
1 2
ISP 0

2
3
2
1

3
2
1
ISP 1 PC229
1 2 PC230 0.1U_0603_25V7K 1 2
PC228 1000P_0402_50V7K
1000P_0402_50V7K 2 1
AO4714 1N SO8
PC231
180P_0402_50V8J ISP 1
1 2 VSEN0
6 CPU_VDD0_FB_H PR235 0_0402_5% 2 1 2 1
1

PR236 PR238
PC238 6.81K_0402_1% 54.9K_0402_1%
@1000P_0402_50V7K 2 1 2 1
2

1 2 RTN0
6 CPU_VDD0_FB_L PR237 0_0402_5% PC232
1200P_0402_50V7K
1 2 RTN1 PR240
6 CPU_VDD1_FB_L PR239 0_0402_5% 1K_0402_1%
1

2 1
PC239
@1000P_0402_50V7K PR243
2

1 2 VSEN1 255_0402_1%
6 CPU_VDD1_FB_H PR241 0_0402_5% 2 1 2 1

4700P_0402_25V7K
PC233

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 55 of 58

5 4 3 2 1
 A B C D

+6269_VCC
1 PR719 1

0_0402_5%
2 1
PR702
0_0402_5%
<32,40,41,43,49> SUSP# 1 2
PC707

1
2.2U_0603_10V6K

1
PL701
HCB2012KF-121T50_0805

2
PC702 VGA_B+ 2 1 B+

2
@ 0.1U_0402_10V7K

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K

1
4

1
PC703

PC704

PC710
2 1 PC705
PC716 @680P_0402_50V7K

EN

VCC

VIN
FCCM

2
5
6
7
8
22P_0402_50V8J

2
PR720
PR721 2 1 2 1 5 COMP GND 17
+VGA_CORE 2 1 PC717 90.9K_0402_1%
0_0402_5% 6800P_0402_25V7K
PGOOD 16 4
PR712 1 2 6 PU701
10_0402_5% PR707 FB ISL6269ACRZ-T_QFN16_4X4 PQ701
+VGA_COREP 1 2 2.55K_0402_1% 2 1 15 LX_VGA AO4474_SO8
PHASE PR711
PR706

3
2
1
49.9K_0402_1% 7 0_0402_5%
FSET DH_VGA DH_VGA_1
UG 14 1 2
2 2 1 PL702 2

1
PC715 0.33UH_PCMC063T-R33MN_20A_20% +VGA_COREP
0.01U_0402_16V7K 8 13 BST_VGA 1 2 BST1_VGA1 2 1 2
PR704 VO BOOT

PGND

PVCC
4.32K_0402_1% PR708 PC706

ISEN
2.2_0402_5% 0.22U_0603_16V7K

LG
2

1
5
6
7
8

5
6
7
8
PR710

10

11

12
2

+5VALW PQ703 PQ702 @4.7_1206_5%

330U_2V_Y_D2_LESR9M
1 1 1 1
PR713 +VGA_COREP 6269_PVCC

330U_2V_Y_D2_LESR9M

330U_2V_Y_D2_LESR9M

330U_2V_Y_D2_LESR9M
+ + + +

PC708

PC713

PC714

PC718
FDS6676AS_SO8

FDS6676AS_SO8
9.09K_0402_1% PR709

2 2
1

2 1
0_0402_5% 4 4 PC709
1

PR716 2 2 2 2
100K_0402_5% @680P_0603_50V7K
PR717 PR705

1
1 2
2

1 2 8.25K_0402_1%

3
2
1

3
2
1
PQ705
10K_0402_1%
1

D SSM3K7002FU_SC70-3
2 1 2 +5VALW
VGA_PWRSEL 16
1

D G
PQ704 2 S PR715
3

1
SSM3K7002FU_SC70-3 G 0_0402_5% OCP=22.8(min)
1

S PR703
3

PC719 0_0402_5% MOSTemperature Factor=1.3 (100C)

0.022U_0402_16V7K
2

PR722
3 +6269_VCC 2 1 2 6269_PVCC 3
PJP701
2.2_0402_5% 1 2 +VGA_CORE (18A,720mils ,Via NO.= 36)
+VGA_COREP
1

High: VGA_CORE 0.95V PC701

PAD-OPEN 4x4m
2

PJP702
Low: VGA_CORE 1.1V 2.2U_0603_10V6K
1 2

PAD-OPEN 4x4m
PJP703
1 2

PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 56 of 58
A B C D
 5 4 3 2 1

Item Modify List

PAGE Fixed Issue and change item M.B. Ver.

1 Remove Q23 (2N7002) 41

HP OUT For Docking 1.1

2 ADD R936 R937 (0 ohm) 41 HP OUT For Docking 1.1

15,16,17
3 Remove U5 (M82-S) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
D 4 Remove U54 18,19,20,21 change M82S TO M86M 1.1
D

15,16,17
5 Remove Q8(SI2301BDS) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
6 Remove Q9(2N7002) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
7 Remove R149 (240 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
8 Remove L32,L33 (0 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
9 Remove R42,R625,R630 18,19,20,21 change M82S TO M86M 1.1
(0 ohm)
15,16,17
10 Remove R189 (100 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
11 Remove R131,R142 (1K ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
12 Remove R120,R130,R190,R197,R243,R244,R245,R246(10K ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
13 Remove R151 (10Kohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
14 Remove R145,R146,R147,R241,R242,R403 (4.7Kohm) 18,19,20,21
change M82S TO M86M 1.1

15,16,17
15 Remove R159,R160,R165,R166(56 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
C 16 Remove R143,R144,R148,R150 (100 ohm) 18,19,20,21 change M82S TO M86M 1.1 C

15,16,17
18,19,20,21
17 Remove R109 (1.27K ohm) change M82S TO M86M 1.1

15,16,17
18 Remove R112 (150 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
19 Remove R108 (2K ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
18 Remove R1136 (249 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
20 Remove R119,R132 (499 ohm) 18,19,20,21
change M82S TO M86M 1.1

15,16,17
21 Remove R155,R156,R157,R158,R161,R162,R163,R164 (4.99Kohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
22 Remove R135 (715 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
23 Remove R177 (75 ohm) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
24 Remove C254,C255,C256,C257,C258,C259,C260,C261,C262,C263,C264,C265,C266,C267,C268,C269,C270,C271,C272,C273,C274,C275,C276,C277,C278,C279,C280,C281,C282,C283,C284,C285 (0.1U) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
25 Remove C478 (220U) 18,19,20,21 change M82S TO M86M 1.1

15,16,17
26 Remove L23,L24,L25,L26,L27,L28,L29,L30,L31,L34,L35,L36,L37,L38,L39,L40,L41,R110,R115 18,19,20,21 change M82S TO M86M 1.1
(BLM18PG121SN1D)
Remove C294,C295,C298,C299,C302,C303,C305,C307,C310,C315,C318,C319,C322,C330,C331,C332,C336,C337,C341,C351,C356,C359,C364,C368,C373,C380,C386,C390,C392,C395,C405,C406,C413,C414,C428,C429,C436,C437,C599 15,16,17
B 27 (10 U) 18,19,20,21 change M82S TO M86M 1.1 B

Remove C287,C288,C290,C292,C297,C300,C306,C308,C311,C314,C317,C320,C323,C325,C328,C329,C339,C344,C358,C382,C391,C394,C397,C398,C400,C402,C403,C408,C409,C410,C411,C416,C417,C418,C419,C421,C423, 15,16,17

28 C425,C426,C431,C432,C433,C434,C439,C440,C441,C442,C598 18,19,20,21 change M82S TO M86M 1.1
(0.1 U)
29 Remove C286,C312,C338,C340,C342,C343,C345,C346,C352,C353,C354,C355,C360,C361,C362,C363,C369,C370,C371,C372,C374,C375,C376,C377,C387,C388,C393,C396,C289,C291,C293 15,16,17
C296,C301,C304,C309,C313,C316,C321,C324,C333,C334,C335,C347,C348,C349,C350,C357,C365,C366,C367,C378,C379,C381,C383,C384,C385,C389,C399,C401,C407,C415,C422,C424,C430,C438,C597(1U) 18,19,20,21 change M82S TO M86M 1.1

30 Remove U12 (ADM1032ARMZ) 15,16,17

18,19,20,21 change M82S TO M86M 1.1
15,16,17
31 Remove R330(4.7K ohm) 18,19,20,21 change M82S TO M86M 1.1
Remove C466
32 (0.1U) 38 Fix CR_LED 1.1

33 Remove C467 (2200P) 38 Fix CR_LED 1.1

34 Remove Q53(2N7002) 38 Fix XD_ALE

35 ADD R933(0 ohm)

36 ADD R127(10Kohm)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 57 of 58
5 4 3 2 1
 5 4 3 2 1

Item Modify List

PAGE Fixed Issue and change item M.B. Ver.

1 ADD ":U6,UV7,U7,UV8,U8,UV9,U9,UV10
"(MEMARY) P15~P25 change M82S TO M86M
1.1

2 ADDQ9 (2N7002) P15~P25 change M82S TO M86M 1.1

3 ADD QV3(SI2301BDS) P15~P25 change M82S TO M86M 1.1

4 ADD RV47(240 ohm) P15~P25 change M82S TO M86M 1.1

D D
5 ADD R42(0 ohm) P15~P25 change M82S TO M86M 1.1

6 ADD RV19,RV44 P15~P25 change M82S TO M86M 1.1

(1K ohm)

7 ADD RV96,RV100,RV72,RV73,RV74,RV75,RV76,RV77,RV78,RV79,RV92,RV93,RV94,RV95,RV97,RV99,RV101,RV107,RV108,RV7,RV9,RV10,RV11,RV12,RV13,RV14,RV16,RV17,RV18,RV33,RV98,RV102(10K ohm) P15~P25 change M82S TO M86M 1.1

8 ADD RV30,RV34(100K ohm) P15~P25 change M82S TO M86M 1.1

9 ADD RV103,RV104,RV45,RV46,R403(4.7K ohm) P15~P25 change M82S TO M86M 1.1

10 ADD RV36,RV37,RV38,RV39,RV40,RV41,RV42,RV43(100 ohm) P15~P25 change M82S TO M86M 1.1

11 ADD RV6 P15~P25 change M82S TO M86M 1.1

(1.27Kohm)

12 ADD RV25,RV26,RV27,RV8(150 ohm) P15~P25 change M82S TO M86M 1.1

13 ADD RV5(2K ohm) P15~P25 change M82S TO M86M 1.1

14 ADD RV23,RV15,RV22(499 ohm)

P15~P25 change M82S TO M86M 1.1

15 ADD RV60,RV61,RV62,RV63,RV66,RV67,RV68,RV69,RV54,RV55,RV56,RV57,RV48,RV49,RV50,RV51(4.99K ohm) P15~P25 change M82S TO M86M 1.1

16 ADD RV24(715 ohm) P15~P25 change M82S TO M86M 1.1

C C
ADD RV28(75 ohm) P15~P25
17 change M82S TO M86M 1.1

18 ADD YV1(CRYSTAL 27MHZ) P15~P25 change M82S TO M86M 1.1

19 ADD RV103,RV104,RV45,RV46,R403(4.7K ohm) P15~P25 change M82S TO M86M 1.1

20 ADD LV1,LV2,LV3,LV4,LV5,LV6,LV7,LV8,LV9,LV10,LV11,LV12,LV13,LV14,LV15,LV16,LV17,LV18,LV19,LV21,LV22,LV23,LV24,LV25 P15~P25 change M82S TO M86M 1.1

(MURATA BLM18PG121SN1D )

21 ADDCV226,CV227,CV234,CV235,CV249,CV250,CV257,CV258,CV203,CV204,CV211,CV212,CV180,CV181,CV188,CV189,CV42,CV45,CV48,CV52,CV53,CV56,CV59,CV64,CV67,CV68,CV71,CV76,CV84,CV85,CV90,CV92,CV95,CV97,CV99,CV101,CV108, P15~P25
CV117,CV119,CV131,CV132,CV136,CV140,CV145,CV149,CV157,CV165,CV166,CV169,CV173(10u) change M82S TO M86M 1.1

22 ADD CV80,CV244,CV229,CV230,CV231,CV232,CV237,CV238,CV239,CV240,CV242,CV246,CV247,CV252,CV253,CV254,CV255,CV260,CV261,CV262,CV263,CV265,CV267,CV269,CV270,CV206,CV207,CV208,CV209,CV214,CV215,CV216, change M82S TO M86M 1.1

CV217,CV219,CV221,CV223,CV224,CV196,CV183,CV184,CV185,CV186,CV191,CV192,CV193,CV194,CV198,CV200,CV201,CV44,CV46,CV49,CV50,CV55,CV58,CV60,CV62,CV66,CV69,CV72,CV75,CV79,CV83, P15~P25
CV87,CV88,CV106,CV114,CV120,CV125,CV159,CV168,CV171,CV172,CV175,CV176,CV177,CV178,CV179,CV272(0.1u)
change M82S TO M86M 1.1

23 ADD CV77,CV78(22P) P15~P25 change M82S TO M86M 1.1

24 ADD CV273 (2200P) P15~P25 change M82S TO M86M 1.1

25 ADDCV233,CV241,CV256,CV264,CV210,CV218,CV187,CV195(0.01U) P15~P25 change M82S TO M86M 1.1

26 ADD CV245,CV228,CV236,CV243,CV251,CV259,CV266,CV268,CV205,CV213,CV220,CV222,CV197,CV182,CV190,CV199,CV41,CV43,CV47,CV51,CV57,CV63,CV65,CV70,CV73,CV74,CV82,CV86,CV89,CV93,CV96,CV98,CV100,CV103,CV104, change M82S TO M86M 1.1

CV105,CV107,CV109,CV111,CV113,CV118,CV121,CV135,CV139,CV144,CV162,CV163,CV164,CV54,CV61,CV94,CV102,CV110,CV112,CV115,CV116,CV123,CV124,CV126,CV127,CV129,CV130,CV133,CV134,CV137,CV138,CV141,CV142, P15~P25
CV146,CV147,CV150,CV151,CV153,CV154,CV155,CV156,CV158,CV160,CV161,CV167,CV170,CV174(75 ohm)
ADD RV28(1U) change M82S TO M86M 1.1
B B
27 ADD CV9,CV10,CV11,CV12,CV13,CV14,CV15,CV16,CV17,CV18,CV19,CV20,CV21,CV22,CV23,CV24,CV25,CV26,CV27,CV28,CV29,CV30,CV31,CV32,CV33,CV34,CV35,CV36,CV37,CV38,CV39,CV40 P15~P25 change M82S TO M86M 1.1
( 0.1U)

28 ADD CV122,CV91,CV128(33OU) P15~P25 change M82S TO M86M 1.1

PV

1 Change RV30 100K to 100 ohm P16 About GBU 27MHz

2 Change PR702 4.7K to 0 ohm P55 About GBU 3V_delay time

3 del PC702 0.1 U P55 About GBU 3V_delay time

4 change NET DQMA#4 TO U8 F3 Pin P22 about GBU A chanel VRAM

5 change NET DQMA#5 TO U8 B3 Pin P22 about GBU A chanel VRAM

6 Change NET QSA4 QSA#4 TO U8 F7,E8 PIN P22 about GBU A chanel VRAM

7 Change NET QSA5 QSA#5TO U8 B7,A8 PIN P22 about GBU A chanel VRAM

8 change NET DQMA#7 TO U8 F3 Pin P22 about GBU A chanel VRAM

9 change NET DQMA#6 TO U8 B3 Pin P22 about GBU A chanel VRAM

10 Change NET QSA7 QSA#7TO U8 F7,E8 PIN P22 about GBU A chanel VRAM

11 Change NET QSA6 QSA#6 TO U8 B7,A8 PIN P22 about GBU A chanel VRAM

12 Change UV12 BOM SA010320120 to SA010320110 P25 about GBU Thermal Sensor

13 Modify R237,R238,R176,R209 PULL +3VS TO +3VS_DELAY P27 P29 Change power plan

A 14 ADD LV20,CV152,CV148,CV143 P18 ADD M86M +VDDR5 POWER A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4093
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401621 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 15, 2009 Sheet 58 of 58
5 4 3 2 1