GOVERNMENT ENGINEERING COLLEGE

RAIPUR, CHHATTISGARH

VLSI (LAB)
NAME: SOUMYA CHOUBEY

ROLL NO. : 301602816046

BRANCH: ELECTRONICS &

TELECOMMUNICATION (2016-2020)
 EXPERIMENT 6
Design 16:1 Mux using Generator Statement

Department of Electronis & Telecommunication Engineering

Government Engineering College

Raipur, Chhattisgarh
1.OBJECT: To Design 16:1 Multiplexer Using Generate Statement and Implementation
in FPGA.

2. TOOLS REQUIRED : Xilinx ISE 14.1 ,Windows 8.1

3. THEORY :

Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection
lines and single output line. One of these data inputs will be connected to the output
based on the values of selection lines.Since there are ‘n’ selection lines, there will be
2n possible combinations of zeros and ones. So, each combination will select only one
data input. Multiplexer is also called as Mux.

Fig.1 Block Diagram of 16:1

4. VHDL CODE
--Library declarations

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux_16 is
port
(
Data_In :in std_logic_vector(15 downto 0);
Select_In :in std_logic_vector(3 downto 0);
Data_Out :out std_logic
);
end Mux_16;

architecture Behavioral of Mux_16 is

--4:1 Mux Component Instantiation

component Mux_4 is
port
(
Data_In :in std_logic_vector(3 downto 0);
Select_In :in std_logic_vector(1 downto 0);
Data_Out :out std_logic
);
end component;

signal S_Data_Out:std_logic_vector(3 downto 0);

begin

--Stage 1 Mapping

G_MUX_4:for V_I in 0 to 3 generate

U_Mux_4_1:Mux_4
port map
(
Data_In => Data_In(V_I*4+3 downto V_I*4),
Select_In => Select_In(1 Downto 0),
Data_Out => S_Data_Out(V_I)
);
end generate;

--Stage 2 Mapping

U_Mux_4_2:Mux_4
port map
(
Data_In => S_Data_Out,
Select_In => Select_In(3 Downto 2),
Data_Out => Data_Out
);

end Behavioral;

code for 4:1 mux:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux_4 is
port
(
Data_In :in std_logic_vector(3 downto 0);
Select_In :in std_logic_vector(1 downto 0);
Data_Out :out std_logic
);
end Mux_4;

architecture Behavioral of Mux_4 is

begin

--------------------------------------------------------------------
--Data Out is implemented using basic principle of the Mux as Shown
-- Select line | Data_Out
-- 00 | Data_In(3)
 -- 01 | Data_In(2)
-- 10 | Data_In(1)
-- 11 | Data_In(0)
--------------------------------------------------------------------

Data_Out <= (not Select_In(1) and not Select_In(0) and Data_In(3) )

or (not Select_In(1) and Select_In(0) and Data_In(2))
or (Select_In(1) and not Select_In(0) and Data_In(1))
or (Select_In(1) and Select_In(0) and Data_In(0));

end Behavioral;

5. SCHEMATIC VIEW

Fig.2 Top Level Block

 Fig.2 16:1 Multiplexer

Fig 3 4:1 Internal Diagram

5. OUTPUT:

6. CONCLUSION:
Hence, we got designed the 16:1 multiplexer using generator statement which give the
designer the ability to create replicated structures, or select between multiple
representations of a model. Here we used four 4:1 mux to implement 16:1 mux and hence
due to replication of 4:1 mux model we used the Generator statement for the ease to design
16:1 and shorten the code for the program and make it efficient