Experiment No 5

Implementation of demultiplexer using Verilog code

Objective: -

To write and simulate the HDL code to realize the Combinational gates and to check the
functionality by simulating the design ISE Simulator.

Theory:-

The action or operation of a demultiplexer is opposite to that of the multiplexer. As inverse to the
MUX , demux is a one-to-many circuit. With the use of a demultiplexer , the binary data can be
bypassed to one of its many output data lines.
The process of getting information from one input and transmitting the same over one of many
outputs is called demultiplexing. A demultiplexer is a combinational logic circuit that receives
the information on a single input and transmits the same information over one of 2n possible
output lines.
Demultiplexers are also called as data distributors, since they transmit the same data which is
received at the input to different destinations.

Thus, a demultiplexer is a 1-to-N device whereas the multiplexer is an N-to-1 device. The figure
below shows the block diagram of a demultiplexer or simply a DEMUX.

It consists of 1 input line, n output lines and m select lines. In this, m selection lines are required
to produce 2m possible output lines (consider 2m = n). For example, a 1-to-4 demultiplexer
requires 2 (22) select lines to control the 4 output lines.

1-2 demux:

A 1-to-2 demultiplexer consists of one input line, two output lines and one select line. The signal
on the select line helps to switch the input to one of the two outputs. The figure below shows the
block diagram of a 1-to-2 demultiplexer with additional enable input.
Data flow modeling

The dataflow level shows the nature of the flow of data in continuous assignment statements
(assign keyword). It describes the combinational circuit by their functions rather than their gate
structures. For coding in the dataflow style, we only need to know about the logical expression of
the circuit.
Logical Expression:

The equations for 1:2 de-mux are:

Y0 = D.S’
Y1= D.S
where Y0 and Y1 are the final outputs, D and S are inputs.
Verilog code for 1:2 DE-MUX using data flow modeling

To start with this, first, you need to declare the module. There’s no need for data- type
declaration in this modeling.
Verilog code 0f 1-2 de-mux:
module demux1to2(Y0,Y1, D, S);
output Y0,Y1;
input D, S;

assign Y0= (~S&D);

assign Y1= (S&D) ;

endmodule

1-4 de-mux:
Verilog code 0f 1-4 de-mux:

module demux1to4(F,S0,S1,I,Y0,Y1,Y2,Y3);
output Yo,Y1,Y2,Y3;
input F,I,S0,S1;

assign Y0=(F&~S1&~S0&I);
assign Y1=( F&~S1&S0&I);
assign Y2=(F&S1&~S0&I);
assign Y3=(F&S1&S0&I);

endmodule

Lab task:

1. Implement 1-8 demux and 1-16 demux using Verilog data flow modeling on Xilinx.

2. Verify truth table with timing diagram using model sim software.

Conclusion: