Digital System Design: Combinational Circuits MUX and DEMUX

Digital System Design
KEC302
Unit-2
Combinational Circuits
Deepak Sigroha
Electronics Engineering Department
Rajkiya Engineering College Sonbhadra
deepak.sigroha@recsonbhadra.ac.in
+91-9478856526
 Outline
Looping
• Combinational Circuits
o Analysis & Design
• Arithmetic Circuits
o Adder, Subtractor, & Multiplier
• Non-arithmetic Circuits
o Magnitude Comparator, Code Convertors & Parity Generator/Checker
• Encoder & Decoder
• Multiplexer & De-Multiplexer
• ALU
• Barrel Shifter
Combinational Circuit
(Multiplexers & Demultiplexers)
Multiplexing
 Multiplexing means sharing. A common example of multiplexing or sharing occurs when
several peripheral devices share a single transmission line or bus to communicate with a
computer.
1. Time Multiplexing: Each device in succession is allocated a brief time to send or receive data. At any given
time, one and only one device is using the line.
2. Frequency Multiplexing: Several devices share a common line by transmitting at different frequencies.
 In a large mainframe computer, numerous users are time-multiplexed to the computer in such a
rapid succession that all appear to be using the computer simultaneously.
Unit 2 – Combinational Circuits 4

Multiplexer
 A multiplexer (MUX) selects 1 of input data sources and transmits the selected data to a single
output—called multiplexing.
• A digital multiplexer or data selector is a logic circuit that performs the same task.
Routing control of desired data

input to output by SELECT
inputs—referred to as
ADDRESS inputs.

Multiplexer
 The “Multiplexer” is a special, versatile and one of the most widely used standard circuits in
digital design.
 A digital multiplexer or data selector is a logic circuit that accepts several digital data inputs
and selects one of them at any given time to pass on to the output.
 The selection of a particular input line is controlled by a set of selection lines. Normally, there
are input lines and ‘n’ selection lines (sometime referred as ADDRESS input) whose bit
combinations determine which input is selected.

Multiplexer
 Consider an integer ‘m’, which is constrained by the following relation:
, where ‘m’ and ‘n’ are both integers.
 A m-to-1 ( Multiplexer has
 m Inputs: ///………./
 One Output: Y/Z
 n Control inputs: ......

 One (or more) Enable input (E)
 Such that Y/Z may be equal to one of the inputs, depending upon the control inputs.

Multiplexer
 A two-to-one-line multiplexer connects one of two 1-bit sources to a common destination.
 The circuit has two data input lines as and , one output line designated as , and one selection
line .
Select Input Output

′
Y =S I 0 +S I 1 0
1
(a) Block Diagram (b) Function Table

 Wedge shape suggests visually how a selected one of multiple data sources is directed into a
single destination.

Multiplexer
 The logic level applied to the S input determines which AND gate is enabled so that its data
input passes through the OR gate to output Y.
 When , the upper AND gate (1) is enabled and has a path to the output. When , the lower AND
gate (2) is enabled and has a path to the output.
1
′
Y =S I 0 +S I 1
2
(c) Logic Circuit
 The multiplexer acts like an electronic switch that selects one of two sources.
Multiplexer
 A two-input MUX could be used is in a digital system that uses two different MASTER CLOCK signals:
a high-speed clock (say, 10 MHz) in one mode and a slow-speed clock (say, 4.77 MHz) for the other.
 Using the circuit of, the 10-MHz clock would be tied to and the 4.77-MHz clock would be tied to .
 A signal from the system’s control logic section would drive the SELECT input to control which clock signal appears at
output for routing to the other parts of the circuit.

4-to-1 Multiplexer
 A MUX has four inputs as and and one output designated as and two select lines as and
inputs
I0 Select Inputs Output
I1 I0
4x1
Y
I2 MUX 1 output 0 0
0 1
I3
1 0
1 1
Enable (G)
S1 S0 Y =S ′1 S ′0 I 0 + S ′1 S0 I 1+ S 1 S′0 I 2 +S 1 S 0 I 3
0 0
n control inputs
MUX Actual Circuit
I3
I2
Y
I1
I0 Y =S ′1 S ′0 I 0 + S ′1 S0 I 1+ S 1 S′0 I 2 +S 1 S 0 I 3
S 1 S 0Enable (G)
Multiplexers
 The AND gates and inverters in the multiplexer resemble a decoder circuit, and indeed, they decode
the selection input lines.
 In general, a line multiplexer is constructed from an decoder by adding input lines to it, one input
to each AND gate. The outputs of the AND gates are applied to a single OR gate.
 The size of a multiplexer is specified by the number of its data input lines and the single output
line. The selection lines are implied from the data lines.
 As in decoders, multiplexers may have an enable input to control the operation of the unit.
 When the enable input is in the inactive state, the outputs are disabled, and when it is in the active state, the
circuit functions as a normal multiplexer.

Tristate Gates
 A multiplexer can be constructed with three-state gates—digital circuits that exhibit three
states.
 Two of the states are signals equivalent to logic 1 and logic 0 as in a conventional gate.
 The third state is a high-impedance state in which
1. The logic behaves like an open circuit, which means that the output appears to be disconnected.
2. The circuit has no logic significance.
3. The circuit connected to the output of the three-state gate is not affected by the inputs to the gate.
 Three-state gates may perform any conventional such as AND or NAND. However, the one
most commonly used is the buffer gate.

Tristate Gates
 The graphic symbol for a three-state buffer gate is shown in Figure. It is distinguished from a
normal buffer by an input control line entering the bottom of the symbol.
 The buffer has a normal input, an output, and a control input that determines the state of the
output.
 When the control input is equal to 1, the output is enabled and the gate behaves like a conventional buffer,
with the output equal to the normal input.
 When the control input is 0, the output is disabled and the gate goes to a high-impedance state, regardless of
the value in the normal input.

Tristate Gates
 The high-impedance state of a three-state gate provides a special feature not available in other
gates.
 A large number of three-state gate outputs can be connected with wires to form a common line
without endangering loading effects.
Three-state Gates

2:1 MUX Using Tri-state Gates
 The two outputs are connected together to form a single output line. (Note that this type of
connection cannot be made with gates that do not have three-state outputs.)
 When the select input is 0, the upper buffer is enabled by its control input and the lower buffer is
disabled. Output is then equal to input .
 When the select input is 1, the lower buffer is enabled and is equal to .
Construction of a two-to-one-line multiplexer with 2 three-state buffers and an inverter

2:1 MUX Using Tri-state Gates
 The two outputs are connected together to form a single output line.
 When the select input is 0, the lower buffer is enabled by its control input and the upper buffer is
disabled. Output is then equal to input B.
 When the select input is 1, the upper buffer is enabled and is equal to .
Construction of a two-to-one-line multiplexer with 2 three-state buffer.

4:1 Multiplexer using Decoder & Tri-state Gates
 The outputs of 4 three-state buffers are connected together
to form a single output line.
 The control inputs to the buffers determine which one of the
four normal inputs through will be connected to the output
line.
 The connected buffers must be controlled so that only 1
three-state buffer has access to the output while all other
buffers are maintained in a high impedance state. One way
to ensure that no more than one control input is active at
any given time is to use a decoder, as shown in the diagram.
 When the enable input of the decoder is 0, all of its four
outputs are 0 and the bus line is in a high-impedance state
because all four buffers are disabled.
 When the enable input is active, one of the three-state
buffers will be active, depending on the binary value in the
select inputs of the decoder.
Construction of a 4:1 multiplexer with 4 three-state
buffers and a decoder
4:1 MUX using Active-Low Decoder & Tri-state Buffers
Four-input multiplexer: (a) using sum of products logic; (b) using tristate buffers
Multiplexers
 Two, four, eight, and 16-input multiplexers are readily available in the TTL and CMOS logic
families. These basic ICs can be combined for multiplexing a larger number of inputs.
 Some packages contain more than one multiplexer, for example, the 74157 quad 2-to-1
multiplexer (four 2-to-1 multiplexers having the same data select inputs) and the 74153 dual 4-to-
1 multiplexer.
 Some designs have 3-state outputs and others have open collector outputs. Most have enable
inputs to facilitate cascading.

8:1 Multiplexer (74ALS151)

Implementation of Higher Order Multiplexer using Lower Order Multiplexers
Given Mux To be Implemented Required
2:1 16 : 1
4:1 16 : 1
4:1 64 : 1
8:1 64 : 1
8:1 256 : 1
NOTE: To Implement MUX, the total number of 2 : 1 MUXs is (

16:1 MUX from Two 8:1 MUX and OR Gate
 This circuit has a total of 16 data inputs, eight applied to each MUX. The
two multiplexer outputs are combined in the OR gate to produce a
single output . The circuit functions as a 16-input MUX.
 The four select inputs will select one of the 16 inputs to pass through
to
 Among the four select inputs, the least significant three select lines ()
are connected with three select inputs of both the MUX ICs,
determines which data inputs will appear at the output and pass
through OR gate to .
 The select input is connected to Enable input of MUX, determines
which multiplexer is enabled.
 When the top multiplexer is enabled, and the select inputs determine
which of its data inputs will appear at its output and pass through the
OR gate to X.
 When the bottom multiplexer is enabled, and the inputs select one of its
data inputs for passage to output X.
Logic diagram for cascading of two 8 × 1 mux to get
a 16-bit mux
16:1 MUX from Two 8:1 MUX and One 2:1 MUX
 This circuit has a total of 16 data inputs, eight applied to
each MUX. The two multiplexer outputs are combined in
the 2:1 MUX to produce a single output . The circuit
functions as a 16-input MUX.
F1
 The four select inputs will select one of the 16 inputs to
pass through to .
 The select input is connected to select input of the 2:1
MUX.
 For the values of = 000 to 111, inputs 0 to 7 of top MUX will
appear at the input terminal 0 of the 2:1 mux through the
output of the top 8:1 mux and inputs 0 to 7 of bottom MUX
will appear at the input terminal 1 of the 2:1 mux through
the output of the second 8:1 mux. F2
 For , output . For , output
Logic diagram for cascading of two 8 × 1 mux to get a 16-

bit mux
4:1 MUX using Three 2:1 MUX
I0 0
2:1 MUX
I1 1
0 f 0 0
2:1 MUX 0 1
(LSB)
1 1 0
1 1
I2 0
2:1 MUX (MSB)
I3 1
(LSB)
8:1 MUX from Seven 2:1 MUX
I0
2:1 MUX
I1
S0 2:1 MUX
I2
I3
2:1 MUX S1
S0
Y
2:1 MUX
I4
2:1 MUX
I5
S2
S0
2:1 MUX
I6
2:1 MUX
I7 S1
S0
16:1 MUX using 4:1 MUXs
 16 inputs are there, the first four inputs are applied to the first 4:1 mux, the second four inputs to the second 4:1 mux,
the third four inputs to the third 4:1 mux, and the fourth four inputs are applied to the fourth 4:1 mux.
 Four select inputs are required. Select inputs and are applied to and terminals of the four muxes. The outputs of
these muxes are connected as data inputs to the fifth 4:1 mux and select inputs and are applied to and of that mux.
 When ; will appear at, at , D8 at F3 and D12 at F4.
 When appears at , at , at and at .
 Similarly, when and appear at and respectively.
 When and appear at and respectively. Depending upon the values of AB either F1 or F2 or F3 or F4 will appear at the output.

32:1 MUX using 16:1 MUXs and 2:1 MUX
 A 32:1 mux has 32 data inputs. So it requires five data select lines.
 For the values of to , inputs to will appear at the input terminal of the mux through the output of the first
16:1 mux and inputs to will appear at the input terminal of the mux through the output of the second 16:1
mux.

Application of Multiplexers
 Logic function generation
 Data selection
 Data routing
 Operation sequencing
 Parallel-to-serial conversion
 Waveform generation

MUX as a Universal Logic Circuit
 Buffer
0 I0
Y
1 I1
S
Required 2:1 MUX is 1

 NOT Gate
1 I0
Y
0 I1
S

 AND Gate
0 I0
Y
B I1
S

 OR Gate
B I0
Y
1 I1
S

 NOR Gate
B′ I0
Y
0 I1
S
Required 2:1 MUX is 2, one to perform OR operation and one to perform NOT operation

 NAND Gate
1 I0
Y
B′ I1
S
Required 2:1 MUX is 2, one to perform AND operation and one to perform NOT operation

 Ex-OR Gate
B I0
Y
B′ I1
S

 Ex-NOR Gate
B′ I0
Y
B I1
S

 For Implementation of basic logic
gates, the required number of 2:1
Mux is 1.
 For Implementation of universal and
special purpose logic gates, the
required number of 2:1 Mux is 2.

Logic Function Generator using MUX
 A decoder can be used to implement Boolean functions by employing external OR gates.
 An examination of the logic diagram of a multiplexer reveals that it is essentially a decoder that includes
the OR gate within the unit.
 The minterms of a function are generated in a multiplexer by the circuit associated with the selection
inputs. The individual minterms can be selected by the data inputs.
 Advantage of using a multiplexer in place of logic gates is that, a single integrated circuit can perform a
function that might otherwise require numerous integrated circuits. Moreover, it is very easy to change the
logic function implemented, if and when redesign of a system becomes necessary.

Logic Function Generator/Boolean Function Implementation
 Method of implementing a Boolean function of variables with a multiplexer that has selection
inputs and data inputs as follows:
1. Construct a truth table for the function to be implemented or express the Boolean function in terms of sum-of-
minterms.
2. Connect logic 1 to each data input of the multiplexer corresponding to each combination of the input variables,
for which the truth table shows the function to be equal to 1 or one for each minterm. Logic 0 is connected to
the remaining data inputs.
3. The variables themselves are connected to the data select inputs of the multiplexer.

Logic function generator using Multiplexer
 Implement the following function using 8 to 1 MUX
S2 S1 S0
𝑧 S0
𝑦 S1
0 0 0 1 𝑥 S2
0 0 1 0
1 D0
0 1 0 1 0 D1 8x1
0 1 1 1 1 D2 MUX Output=F
1 D3
1 0 0 0 0 D4
1 0 1 1 1 D5
1 1 0 0 0 D6
0 D7
1 1 1 0

Logic Function Generator
 Implement the Boolean function using 8:1 MUX.
F (A ,B ,C)=∑(1,2,4,7)

Boolean Function Implementation using MUX
1. Any Boolean function with variable can be implemented with MUX by connecting and at
specific input.
2. Some Boolean function with variable can be implemented with MUX.
3. Any Boolean function with variable can be implemented with MUX and a NOT gate.
4. Any Boolean function with variable can be implemented with or …………or and Logic Gates.

Boolean Function Implementation using MUX (Method)
 Multiplexer with data select inputs can implement any function of variables.
 The first variables of the function as the select inputs and to use the least significant input
variable (one variable) and its complement to drive some of the data inputs.
 If the single variable is denoted by , each data output of the multiplexer will be or .
 Suppose, we wish to implement a variable logic function using a multiplexer with three data
select inputs.
 Let the input variables be and is the LSB.
 A truth table for the function is constructed. has the same value twice once with and again with .

Boolean Function Implementation using MUX (Method)
 The following rules are used to determine the connections that should be made to the data inputs
of the multiplexer.
1. If both times when the same combination of occurs, connect logic to the data input selected by that
combination.
2. If both times when the same combination of occurs, connect logic to the data input selected by that
combination.
3. If is different for the two occurrences of a combination of , and if in each case, connect to the data input
selected by that combination.
4. If is different for the two occurrences of a combination of , and if in each case, connect to the data input
selected by that combination.

Implement the following function
using 8 to 1 MUX
F= 0 0 0 0 1
0 0 0 1 1 C S0
B S1
0 0 1 0 1 A S2
0 0 1 1 1
0 1 0 0 1 1 D0
0 1 0 1 0 1′ D1 8x1 Output =F
0 1 1 0 0 D D2 MUX
0 1 1 1 0 0 D3
0 D4
1 0 0 0 0 1 D5
1 0 0 1 0
0 D6
1 0 1 0 1 1 D7
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
Boolean Function Implementation (2)
 Implement the Boolean function using 4:1 MUX.

 Use a multiplexer having three data select inputs to implement the logic for the function . Also realize the
same using a 16:1 MUX.

 Implement the Boolean function using 8:1 MUX. Use as Input.

Boolean Function Implementation by using MUX
 For Implementing any Boolean function of n-variable with a MUX, we require some general
procedure.
1) Express the function in its Standard SOP form.
2) In the ordered sequence of variable, connect variable to to the select input and the single variable to
the input line with complement or uncomplemented form including 0 and 1.
3) List the inputs of MUX (all the minterms) in two rows. The row list all those minterms where single
variable is complemented and row with uncomplemented form.
4) Circle all the minterms of function and inspect each column separately.
5) If two minterms in a column are not circled, apply to the corresponding MUX input.
6) If two minterms are circled, apply to the corresponding MUX input.
7) If one minterm is circled (either upper or lower row), then its front value is the corresponding MUX
input.

4-variable Function {F(A,B,C,D)} Implementation using 8:1 MUX
Let ‘ and ’ are Select lines and as Data Input
0 2 4 6 8 10 12 14
1 3 5 7 9 11 13 15
Let and are Select lines and as Data Input
0 1 4 5 8 9 12 13
2 3 6 7 10 11 14 15

0 1 2 3 8 9 10 11
4 5 6 7 12 13 14 15
Let and’ are Select lines and as Data Input
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15

Let and are Select lines and and as Data Input
0 4 8 12
1 5 9 13
2 6 10 14
3 7 11 15

Let , is Select lines and and as Let is Select lines and ‘and as
Data Input Data Input
0 8 0 4
1 9 1 5
2 10 2 6
3 11 3 7
4 12 8 12
5 13 9 13
6 14 10 14
7 15 11 15

 Implement using 8:1 MUX. Use as data input.
0 2 4 6 8 10 12 14
1 3 5 7 9 11 13 15
0

 Implement The Boolean Function using 8:1 MUX.
F ( A, B,C, D ) =∏ ( 3,7,12 )=∑(0,1,2, 4,5,6,8,9,10,11,13,14 ,15)
0 2 4 6 8 10 12 14
1 3 5 7 9 11 13 15
1 1 1 1 1

 Implement The Boolean Function using a 4:1 MUX.
F ( a , b , c )=ab+b c=ab ( c +c ) + ( a+a ) b c=∑ ( 1,5,6,7 )

′ ′ ′ ′
Let , and are Select lines and as Data

Input
0 2 4 6
1 3 5 7

 Implement Full adder using 4:1 MUX.

 Implement the Boolean function with a 4:1 multiplexer and external gates. Connect inputs and
to the selection line.
 Solution:
 The input requirements for the four data lines will be a function of variables and . These values are obtained by
expressing as a function of and for each of the four cases when and. These functions may have to be
implemented with external gates.

F(A,B,C,D)=∑(1,2,4,7,8,9,10,1 ,13,15)
0 4 8 12
1 5 9 13
2 6 10 14
3 7 11 15


F( A, B,C, D)=∑(0,1,5 ,7 ,8,13 ,14)

0 4 8 12
1 5 9 13
2 6 10 14
3 7 11 15

F( A, B,C, D)=∑(0,1,5 ,7 ,8,13 ,14)

 Implement the Boolean function using 2:1 MUX. Use as select Input.
Let , is Select lines and as Data Input
0 1
2 3
4 5
6 7
8 9
10 11
12 13
14 15

MUX Questions (1)
 The Logic realized by the Circuit shown in figure is
F= A ⊕C
A B
Solution

MUX Questions (2)
 The Boolean function 𝑓 implement in figure using 2:1 MUX is
Solution

MUX Questions (3)
 In the following figure 𝑋 is given by
Solution

MUX Questions (4)
 In the circuit shown, and are MSBs of the control input. The output is given by
Solution

MUX Questions (5)
 The logic function implemented by circuit below is (ground implies a logic 0)
𝟏 0
Solution

MUX Questions (7)
 The Boolean function realized by the logic circuit shown below is
Solution

MUX as Waveform Generator
 A 2-to-1 digital multiplexer having a switching delay of is connected as shown in figure. The output of the multiplexer
is tied to its own select input The input which gets selected when is tied to 1 and the input that gets selected when
is tied to 0. What will be the output ?
2:1 MUX
1
S =0
V0
S =1
0 S
 Solution: When output is 1, then will also be 1 and switch will go to 1 after and output become zero, again becomes
0 and switch will go to 0 after and output goes to 1 and this will continue and we will get the waveform at output as
 so, 1 1 1 1
 Then, 0 0 0 0 0
2 μsec Output waveform

Application of MUXs (Data Routing)
 Multiplexers can route data from one of
several sources to one destination.
 One typical application uses 74ALS157
multiplexers to select and display the contents
of either of two BCD counters using a single
set of decoder/ drivers and LED displays.
 When the COUNTER SELECT line is HIGH, the
outputs of counter 1 will be allowed to pass
through the multiplexers to the
decoder/drivers to be displayed on the LED
readouts. When COUNTER SELECT = 0, the
outputs of counter 2 will pass through the System for displaying two
multiplexers to the displays.
multidigit BCD counters one
 In this way, the decimal contents of one
at a time.
counter or the other will be displayed under
the control of the COUNTER SELECT input.

Data Routing
 A common situation where this might be used is in a digital watch.
 The digital watch circuitry contains many counters and registers that keep track of seconds, minutes, hours,
days, months, alarm settings, and so on. A multiplexing scheme such as this one allows different data to be
displayed on the limited number of decimal readouts.
 The purpose of the multiplexing technique, as it is used here, is to timeshare the decoder/drivers
and display circuits between the two counters rather than have a separate set of decoder/drivers
and displays for each counter.
 This results in a significant saving in the number of wiring connections, especially when more BCD stages are
added to each counter.

Parallel to Serial Conversion
 Many digital systems process binary data in parallel form (all bits simultaneously) because it is
faster.
 When data are to be transmitted over relatively long distances, however, the parallel arrangement
is undesirable because it requires a large number of transmission lines.
 For this reason, binary data or information in parallel form is often converted to serial form before being
transmitted to a remote destination.
 One method for performing this parallel-to-serial conversion uses a multiplexer.

Waveforms for

 The data are present in parallel form at the outputs of the register and are fed to the eight-input
multiplexer.
 A three-bit (MOD-8) counter is used to provide the select code bits so that they cycle through
from to as clock pulses are applied.
 In this way, the output of the multiplexer will be during the first clock period, during the second
clock period, and so on.
 The output is a waveform that is a serial representation of the parallel input data.
 This conversion process takes a total of eight clock cycles. Note that (the LSB) is transmitted
first and the (MSB) is transmitted last.

Demultiplexer
 A demultiplexer (DEMUX) takes a single input and distributes it over several outputs. A demultiplexer
(DEMUX) performs the reverse operation.
 The select input code determines to which output the DATA input will be transmitted.

Demultiplexer
 A demultiplexer(DEMUX) is a device that allows digital information from one source to be routed
onto a multiple lines for transmission over different destinations.
 In other words, A DEMUX is a combinational circuit that receives information on a single line and
transmits this on to possible output lines.
 The selection of a specific output line is controlled by the bit values of selection line.
 A demultiplexercan also known as a ‘distributor’, since it transmits the same data to different
destination.
 A “Decoder” with an enable input can function as a “DEMUX”.

Demultiplexer
 A demultiplexer(DEMUX) is a device that allows digital information from one source to be routed
onto a multiple lines for transmission over different destinations.
 Consider an integer , which is constrained by the following relation:
, where and are both integers.
 A 1-to-m (or Demultiplexer has
 One Input:
 Outputs: ................
 Control inputs: , ..........
 One (or more) Enable input(s)
Such that may be transfer to one of the outputs, depending upon the control inputs.

1-to-4 Demultiplexer
D S1 S ′1 S0 S ′0
O0
1x4 O1
D DEMUX
O0= D S ′1 S′0
O2
O3 O1=D S′1 S 0
S1 S0 O2=D S 1 S′0
Select code Outputs O 3= D S 1 S 0
0 0 0 0 0 D
0 1 0 0 D 0 The input data line goes to all of the AND gates. The two select lines
S0 and S1 enable only one gate at a time, and the data appearing on the
1 0 0 D 0 0
input line will pass through the selected gate to the associated output
1 1 D 0 0 0
line.
1-to-8 Demultiplexer
► The single data input line is connected to all eight
AND gates, but only one of these gates will be
enabled by the select input lines.
► For example, with , only the AND gate will be enabled,
and the data input will appear at output . Other select
codes cause input to reach the other outputs.

1-to-8 Demultiplexer using 3Decoder
 The demultiplexer circuit is very similar to the 3-line to 8-line decoder circuit, except that a fourth
input has been added to each gate. The inputs are here labelled and become the data select
inputs.
 The 3-to-8 decoder can be used as a 1-to-8 demultiplexer as follows:
 The enable input is used as the data input , and the binary code inputs are used as the select inputs.
 Depending on the select inputs, the data input will be routed to a particular output. For this reason, the
IC manufacturers often call this type of device a decoder/demultiplexer.

Applications of DEMUX
 Data Distributor
 Serial to Parallel Convertor
 One to many Circuit

Demultiplexer
Determine the outputs, given the inputs shown. 𝐴0
𝐴1
𝐴2
𝐺1
The output logic is opposite to the input because of LOW
𝐺2 𝐴
the active-LOW convention. (Red shows the selected
line). 𝐺2 𝐵 LOW
Y0
Y1
Data Y2
select
lines Y3
Data
outputs Y4
Enable Y5
inputs
Y6
Y7
74LS138
Implementation of Higher Order DEMUXs using Lower Order DEMUXs
Given DEMUX To be Implemented Required
1:2 1 : 16
1:4 1 : 16
1:4 1 : 64 1 + 4 + 16
1:8 1 : 64 1+8
1:8 1 : 256 1 + 4 + 32 = 37
NOTE: To Implement MUX, the total number of 1 : 2 DEMUX is (

1:8 DEMUX using Two 1:8 DEMUX and an Invertor

1:16 DEMUX using a 1:2 DEMUX and Two 1:8 DEMUX

Demultiplexer (Data Distributor)
 Consider the case of a security monitoring system in an industrial plant where the open/closed
status of many access doors is to be monitored.
 Each door controls the state of a switch, and it is necessary to display the state of each switch on
LEDs that are mounted on a remote monitoring panel at the security guard’s station.
 One way to do this would be to run a separate signal from each door switch to an LED on the
monitoring panel. This setup would require running many wires over a long distance.
 A better approach that would reduce the amount of wiring to the monitoring panel uses a
multiplexer/demultiplexer combination.

Demultiplexer (Data Distributor)
Security monitoring system using the 74ALS138.
 Note that there are only four
signal lines going from the
“door-sensing” circuitry to the
The system shown can handle eight remote monitoring panel: the
doors, but can be expanded to output and the three select
any number.
lines.
 This is a saving of four lines
The door switches are data inputs when compared with the
to the MUX.
alternative of having one line
per door. The MUX/DEMUX
They produce a HIGH when a door
combination is used to
transmit the status of each
is open and a LOW when it is closed.
door to its LED one at a time
(serially) instead of all at once
(parallel).

DEMUX
 The Minimized expression for is
𝑋
𝑍
Solution

References
1. M. Morris Mano, M. D. Ciletti, “Digital Design” 6th Ed., USA : Prentice-Hall.
2. A. Anand Kumar, “Fundamentals of Digital Circuits” 4th Ed., PHI.
3. T. L. Floyd, “Digital Fundamental”, 11th Ed., USA : Prentice-Hall.
4. R.J. Tocci, N. S. Widmer and G. L. Moss “Digital Systems: Principles and Applications”,
11th Ed., USA : Prentice-Hall.

Thank You

Digital System Design: Combinational Circuits MUX and DEMUX

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Digital System Design: Combinational Circuits MUX and DEMUX

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Digital System Design

Unit 2 – Combinational Circuits 4

Routing control of desired data

Unit 2 – Combinational Circuits 5

Unit 2 – Combinational Circuits 6

, where ‘m’ and ‘n’ are both integers.

 A m-to-1 ( Multiplexer has

 n Control inputs: ......

Unit 2 – Combinational Circuits 7

Select Input Output

(a) Block Diagram (b) Function Table

Unit 2 – Combinational Circuits 8

(c) Logic Circuit

Unit 2 – Combinational Circuits 10

I0 Select Inputs Output

Unit 2 – Combinational Circuits 13

Unit 2 – Combinational Circuits 14

Unit 2 – Combinational Circuits 15

Unit 2 – Combinational Circuits 16

Construction of a two-to-one-line multiplexer with 2 three-state buffers and an inverter

Construction of a two-to-one-line multiplexer with 2 three-state buffer.

Unit 2 – Combinational Circuits 21

Unit 2 – Combinational Circuits 22

Given Mux To be Implemented Required

NOTE: To Implement MUX, the total number of 2 : 1 MUXs is (

Unit 2 – Combinational Circuits 23

Logic diagram for cascading of two 8 × 1 mux to get a 16-

Unit 2 – Combinational Circuits 28

Unit 2 – Combinational Circuits 29

Unit 2 – Combinational Circuits 30

Required 2:1 MUX is 1

Unit 2 – Combinational Circuits 31

Required 2:1 MUX is 1

Unit 2 – Combinational Circuits 32

Required 2:1 MUX is 1

Unit 2 – Combinational Circuits 33

Required 2:1 MUX is 1

Unit 2 – Combinational Circuits 34

Unit 2 – Combinational Circuits 35

Unit 2 – Combinational Circuits 36

Required 2:1 MUX is 2

Unit 2 – Combinational Circuits 37

Required 2:1 MUX is 2

Unit 2 – Combinational Circuits 38

Unit 2 – Combinational Circuits 39

Unit 2 – Combinational Circuits 40

Unit 2 – Combinational Circuits 41

Unit 2 – Combinational Circuits 42

Unit 2 – Combinational Circuits 43

Unit 2 – Combinational Circuits 44

Unit 2 – Combinational Circuits 45

Unit 2 – Combinational Circuits 46

Unit 2 – Combinational Circuits 48

Unit 2 – Combinational Circuits 49

Unit 2 – Combinational Circuits 50

Unit 2 – Combinational Circuits 51

Let ‘ and ’ are Select lines and as Data Input

Let and are Select lines and as Data Input

Unit 2 – Combinational Circuits 52

Let and are Select lines and as Data Input

Let and’ are Select lines and as Data Input

Unit 2 – Combinational Circuits 53

Let and are Select lines and and as Data Input