You are on page 1of 8

ON Semiconductor

J308
JFET VHF/UHF Amplifiers J309
N–Channel — Depletion
J310
ON Semiconductor Preferred Devices

MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage VDS 25 Vdc
Gate–Source Voltage VGS 25 Vdc
1
Forward Gate Current IGF 10 mAdc 2
3
Total Device Dissipation @ TA = 25°C PD 350 mW
Derate above 25°C 2.8 mW/°C
CASE 29–11, STYLE 5
Junction Temperature Range TJ –65 to +125 °C TO–92 (TO–226AA)

Storage Temperature Range Tstg –65 to +150 °C

1 DRAIN

3
GATE

2 SOURCE
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
Gate–Source Breakdown Voltage V(BR)GSS –25 — — Vdc
(IG = –1.0 µAdc, VDS = 0)
Gate Reverse Current IGSS
(VGS = –15 Vdc, VDS = 0, TA = 25°C) — — –1.0 nAdc
(VGS = –15 Vdc, VDS = 0, TA = +125°C) — — –1.0 µAdc
Gate Source Cutoff Voltage VGS(off) Vdc
(VDS = 10 Vdc, ID = 1.0 nAdc) J308 –1.0 — –6.5
J309 –1.0 — –4.0
J310 –2.0 — –6.5
ON CHARACTERISTICS
Zero–Gate–Voltage Drain Current(1) IDSS mAdc
(VDS = 10 Vdc, VGS = 0) J308 12 — 60
J309 12 — 30
J310 24 — 60
Gate–Source Forward Voltage VGS(f) — — 1.0 Vdc
(VDS = 0, IG = 1.0 mAdc)

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:


March, 2001 – Rev. 1 J308/D
J308 J309 J310

Characteristic Symbol Min Typ Max Unit

SMALL–SIGNAL CHARACTERISTICS
Common–Source Input Conductance Re(yis) mmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) J308 — 0.7 —
J309 — 0.7 —
J310 — 0.5 —
Common–Source Output Conductance Re(yos) — 0.25 — mmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz)
Common–Gate Power Gain Gpg — 16 — dB
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz)

1. Pulse Test: Pulse Width  300 µs, Duty Cycle  3.0%.


SMALL–SIGNAL CHARACTERISTICS (continued)
Common–Source Forward Transconductance Re(yfs) — 12 — mmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz)
Common–Gate Input Conductance Re(yig) — 12 — mmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz)
Common–Source Forward Transconductance gfs µmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) J308 8000 — 20000
J309 10000 — 20000
J310 8000 — 18000
Common–Source Output Conductance gos — — 250 µmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz)
Common–Gate Forward Transconductance gfg µmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) J308 — 13000 —
J309 — 13000 —
J310 — 12000 —
Common–Gate Output Conductance gog µmhos
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) J308 — 150 —
J309 — 100 —
J310 — 150 —
Gate–Drain Capacitance Cgd — 1.8 2.5 pF
(VDS = 0, VGS = –10 Vdc, f = 1.0 MHz)
Gate–Source Capacitance Cgs — 4.3 5.0 pF
(VDS = 0, VGS = –10 Vdc, f = 1.0 MHz)

FUNCTIONAL CHARACTERISTICS
Noise Figure NF — 1.5 — dB
(VDS = 10 Vdc, ID = 10 mAdc, f = 450 MHz)
Equivalent Short–Circuit Input Noise Voltage en — 10 — nV Hz
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 Hz)

http://onsemi.com
2
J308 J309 J310

50 Ω U310 50 Ω
SOURCE LOAD
C3 L2P L2S
L1 C1 C2
C4
C5 C6
C7
1.0 k
RFC
+VDD
C1 = C2 = 0.8 – 10 pF, JFD #MVM010W.
C3 = C4 = 8.35 pF Erie #539–002D.
C5 = C6 = 5000 pF Erie (2443–000).
C7 = 1000 pF, Allen Bradley #FA5C.
RFC = 0.33 µH Miller #9230–30.
L1 = One Turn #16 Cu, 1/4″ I.D. (Air Core).
L2P = One Turn #16 Cu, 1/4″ I.D. (Air Core).
L2S = One Turn #16 Cu, 1/4″ I.D. (Air Core).

Figure 1. 450 MHz Common–Gate Amplifier Test Circuit

70

Yfs , FORWARD TRANSCONDUCTANCE (mmhos)


70 35
IDSS, SATURATION DRAIN CURRENT (mA)
60 60 30 VDS = 10 V TA = -55°C
VDS = 10 V TA = -55°C f = 1.0 MHz +25°C
I D , DRAIN CURRENT (mA)

50 50 25
IDSS +25°C
40 +25°C 40 20
+150°C
30 30 15 +25°C
+150°C
20 20 -55°C
+25°C 10
-55°C +150°C
10 +150°C 10 5.0

0 0
-5.0 -4.0 -3.0 -2.0 -1.0 0 5.0 4.0 3.0 2.0 1.0 0
ID - VGS, GATE-SOURCE VOLTAGE (VOLTS)
VGS, GATE-SOURCE VOLTAGE (VOLTS)
IDSS - VGS, GATE-SOURCE CUTOFF VOLTAGE (VOLTS)

Figure 2. Drain Current and Transfer Figure 3. Forward Transconductance


Characteristics versus Gate–Source Voltage versus Gate–Source Voltage

100 k
Yfs , FORWARD TRANSCONDUCTANCE (µmhos)

1.0 k 10 120
Yos, OUTPUT ADMITTANCE (µ mhos)

RDS
Yfs 96
R DS , ON RESISTANCE (OHMS)
Yfs
7.0
CAPACITANCE (pF)

10 k 100
72
Cgs
4.0 48
1.0 k VGS(off) = -2.3 V = 10
Yos VGS(off) = -5.7 V =
Cgd 24
1.0
100 1.0 0 0
0.01 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0
ID, DRAIN CURRENT (mA) VGS, GATE SOURCE VOLTAGE (VOLTS)

Figure 4. Common–Source Output Figure 5. On Resistance and Junction


Admittance and Forward Transconductance Capacitance versus Gate–Source Voltage
versus Drain Current

http://onsemi.com
3
J308 J309 J310

|S21|, |S11| |S12|, |S22|


30 3.0 0.85 0.45 0.060 1.00

S22
VDS = 10 V
24 2.4 0.79 0.39 0.048 0.98
ID = 10 mA
|Y11|, |Y21 |, |Y22 | (mmhos)

S21
TA = 25°C
Y11
VDS = 10 V

Y12 (mmhos)
18 1.8 0.73 0.33 0.036 0.96
ID = 10 mA
TA = 25°C
Y21
12 1.2 0.67 0.27 0.024 0.94
S11
Y22
6.0 0.6 0.61 0.21 0.012 0.92

Y12 S12
0 0.55 0.15 0.90
100 200 300 500 700 1000 100 200 300 500 700 1000
f, FREQUENCY (MHz) f, FREQUENCY (MHz)

Figure 6. Common–Gate Y Parameter Figure 7. Common–Gate S Parameter


Magnitude versus Frequency Magnitude versus Frequency

θ21, θ11 θ12, θ22 θ11, θ12 θ21, θ22


180° 50° -20° 87° -20° 120° 0
θ11
θ22 -20°
θ21
170° 40° -40° 86° -40° 100° θ22 -20°
θ21
-60°
160° 30° -80° 85° -60° 80° -40°
-100°
150° 20° -120° 84° -80° 60° θ21 -60°
θ12
θ11 -140° θ12
140° 10° VDS = 10 V -160° 83° -100° 40° VDS = 10 V -80°
θ11
ID = 10 mA ID = 10 mA
TA = 25°C -180°
TA = 25°C
130° 0° -200° 82° -120° 20° -100°
100 200 300 500 700 1000 100 200 300 500 700 1000
f, FREQUENCY (MHz) f, FREQUENCY (MHz)

Figure 8. Common–Gate Y Parameter Figure 9. S Parameter Phase–Angle


Phase–Angle versus Frequency versus Frequency

8.0 24 7.0
VDD = 20 V 26
7.0 21 6.0
f = 450 MHz
BW ≈ 10 MHz 22
6.0 18
G pg , POWER GAIN (dB)

G pg , POWER GAIN (dB)


NF, NOISE FIGURE (dB)

NF, NOISE FIGURE (dB)

CIRCUIT IN FIGURE 1 5.0


5.0 15 Gpg 18
Gpg 4.0 VDS = 10 V
4.0 12 ID = 10 mA 14
NF 3.0 TA = 25°C
3.0 9.0 CIRCUIT IN FIGURE 1 10
2.0 NF
2.0 6.0
6.0
1.0 3.0 1.0
2.0
0 0 0
4.0 6.0 8.0 10 12 14 16 18 20 22 24 50 100 200 300 500 700 1000
ID, DRAIN CURRENT (mA) f, FREQUENCY (MHz)

Figure 10. Noise Figure and Figure 11. Noise Figure and Power Gain
Power Gain versus Drain Current versus Frequency

http://onsemi.com
4
J308 J309 J310

C1 U310 C6
BW (3 dB) – 36.5 MHz
S D ID – 10 mAdc
G VDS – 20 Vdc
L1 C3 C4
INPUT L3 OUTPUT Device case grounded
RS = 50 Ω RL = 50 Ω IM test tones – f1 = 449.5 MHz, f2 = 450.5 MHz
C2 C5 C1 = 1–10 pF Johanson Air variable trimmer.
C2, C5 = 100 pF feed thru button capacitor.
L2 L4 C3, C4, C6 = 0.5–6 pF Johanson Air variable trim-
mer.
L1 = 1/8″ x 1/32″ x 1–5/8″ copper bar.
VS VD L2, L4 = Ferroxcube Vk200 choke.
SHIELD
L3 = 1/8″ x 1/32″ x 1–7/8″ copper bar.
Figure 12. 450 MHz IMD Evaluation Amplifier

Amplifier power gain and IMD products are a function of the load impedance. For the amplifier design shown above with
C4 and C6 adjusted to reflect a load to the drain resulting in a nominal power gain of 9 dB, the 3rd order intercept point (IP)
value is 29 dBm. Adjusting C4, C6 to provide larger load values will result in higher gain, smaller bandwidth and lower IP
values. For example, a nominal gain of 13 dB can be achieved with an intercept point of 19 dBm.

+40
U310 JFET 3RD ORDER INTERCEPT POINT
+20 VDS = 20 Vdc
OUTPUT POWER PER TONE (dBm)

ID = 10 mAdc
0 F1 = 449.5 MHz
F2 = 450.5 MHz
-20
FUNDAMENTAL OUTPUT
-40
Example of intercept point plot use:
-60 Assume two in–band signals of –20 dBm at the amplifi-
-80 er input. They will result in a 3rd order IMD signal at
3RD ORDER IMD OUTPUT the output of –90 dBm. Also, each signal level at the
-100
output will be –11 dBm, showing an amplifier gain of
-120 9.0 dB and an intermodulation ratio (IMR) capability
-120 -100 -80 -60 -40 -20 0 +20 of 79 dB. The gain and IMR values apply only for sig-
INPUT POWER PER TONE (dBm) nal levels below comparison.
Figure 13. Two Tone 3rd Order Intercept Point

http://onsemi.com
5
J308 J309 J310

PACKAGE DIMENSIONS

TO–92 (TO–226AA)
CASE 29–11
ISSUE AL

NOTES:
A B 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
R IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
P BEYOND DIMENSION K MINIMUM.
L
SEATING INCHES MILLIMETERS
PLANE K DIM MIN MAX MIN MAX
A 0.175 0.205 4.45 5.20
B 0.170 0.210 4.32 5.33
C 0.125 0.165 3.18 4.19
D 0.016 0.021 0.407 0.533
X X D G 0.045 0.055 1.15 1.39
G H 0.095 0.105 2.42 2.66
J 0.015 0.020 0.39 0.50
H J K 0.500 --- 12.70 ---
L 0.250 --- 6.35 ---
V C N 0.080 0.105 2.04 2.66
P --- 0.100 --- 2.54
SECTION X–X
1 R 0.115 --- 2.93 ---
N V 0.135 --- 3.43 ---
N
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE

http://onsemi.com
6
J308 J309 J310

Notes

http://onsemi.com
7
J308 J309 J310

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION


NORTH AMERICA Literature Fulfillment: CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
P.O. Box 5163, Denver, Colorado 80217 USA Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Toll–Free from Mexico: Dial 01–800–288–2872 for Access –
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada then Dial 866–297–9322
Email: ONlit@hibbertco.com
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
Phone: 1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
N. American Technical Support: 800–282–9855 Toll Free USA/Canada Toll Free from Hong Kong & Singapore:
001–800–4422–3781
EUROPE: LDC for ON Semiconductor – European Support Email: ONlit–asia@hibbertco.com
German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)
Email: ONlit–german@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center
French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET) 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Email: ONlit–french@hibbertco.com Phone: 81–3–5740–2700
English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT) Email: r14525@onsemi.com
Email: ONlit@hibbertco.com ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 For additional information, please contact your local
*Available from Germany, France, Italy, UK, Ireland Sales Representative.

http://onsemi.com J308/D
8

You might also like