Control Systems of Single-Phase Voltage Source Inverters for a UPS

Zbigniew Rymarski

Institute of Electronics, Silesian University of Technology, ul. Akademicka 16, Gliwice 44-100, Poland
(e-mail: zbigniew.rymarski@polsl.pl)

Abstract: This article presents considerations of the effectiveness of suppressing output voltage
distortions of low power single-phase voltage source inverters (VSI) dedicated for UPS systems working
with the nonlinear rectifier RC load defined in the EN 62040-3 standard. Various types of control systems
were tested – PID/CDM and deadbeat instantaneous controllers designed using the author's discrete
model (including the design of the output filter) of VSI and the fuzzy controller. It was shown that the
additional control loop with the repetitive controller or additional input variables (currents) of the
controller should be used for lowering the THD of the output voltage for the nonlinear load. The results
of the experimental verification are shown.
Keywords: voltage source inverter, coefficient diagram method, repetitive control, fuzzy control,
deadbeat control, nonlinear load.

decoupled into two buck converters in every 60° region. The
1. INTRODUCTION
Clarke transform is very convenient as long as the balanced
The output voltage quality is the basic advantage of voltage load is assumed. Most authors design the 3-phase balanced
source inverters (VSI) for UPS systems. The sinusoidal system and only check its behavior for an unbalanced load
PWM is typical for single- or three-phase UPS systems while (e.g. Kawamura et al. 1988). The resistive-inductive RL load
space vector modulation is the standard in three-phase is a typical industrial load however the EN 62040 standard
induction motor control systems. Single-phase inverters with contains the statement that a nonlinear rectifier RC load with
output power up to 3 ÷ 4 kVA are typical for a UPS for a power factor equal to 0.7 is the typical load for UPS
computer systems. So the demands on them should be systems for output power below 3 kVA. Most low output
precisely established. The EN 62040-3 standard limits the power UPSs are predicted to supply computer systems with
Total Harmonic Distortion (THD) of the output voltage for AC/DC switching mode supplies with the rectifier in their
the defined nonlinear load and presents the requirements for input. This load is defined in the EN 62040-3 standard and
the transient response depending on the class of the system. the THD of the output voltage should be reduced below 8%
The IEEE 519 standard specifies the demands concerning the (for the S class of the UPS). Two types of inverter control
maximum THD and the highest harmonic amplitude of the systems can be considered. The traditional control systems
supplied voltage in the steady state. Considering the output based on the discrete model of the inverter and the fuzzy
voltage harmonics of the PWM inverter it can be easily control system based on "control rules". The presented
proved that the harmonic with the highest amplitude before discrete PID controller has its origin in a continuous
filtering has the frequency fc (fc - frequency of the modulated controller; deadbeat controller is unique for discrete systems
waveform) or fc±fm (fm - fundamental frequency of the and has some parameters (the control speed) that are
modulating sinusoidal signal) where fc>50fm is usual in UPS unreachable in continuous systems (Astrom el al. 1997) but it
systems. The design of the output filter is based on the is more sensitive to load changes (Ben-Brahim et al. 2003).
requirement to sufficiently suppress them (Rymarski 2009, The aim of this paper is to show how the different types of
2010, 2011a) and to minimize the reactive power in the the control systems influence on the output voltage quality of
output filter components. The IEEE-519 standard does not single-phase, 3-level voltage source inverter for a standard
specify the limit of the highest order of the harmonics nonlinear load.
spectrum considered. So it can be used for the design of the
output filter. The EN 62040-3 standard presents demands for 2. VSI OUTPUT VOLTAGE FOR THE OPEN FEEDBACK
the low frequency harmonics (<40) at the supplied voltage. LOOP
The low-order harmonics can be reduced practically only by Let us assume a low power inverter with the apparent output
means of the feedback loop. That is why the EN 62040-3 power S=1150 VA (VOUTRMS=230 V, IORMS=5 A). According
standard is useful for the assignment of control loop to EN 62040-3 the peak-to-peak voltage ripple on the load
requirements. The 3-phase inverters control for a balanced capacitor should not be higher than 5%. For the presented
load can be easily designed using the Clarke transform where inverter the parameters of the nonlinear load (EN 62040-3)
a 3-phase control system is changed into two orthogonal
should be:
single-phase systems. An interesting approach is presented in
(Li et al. 2008) where the three-phase three-legged VSI is RS=0.04U2/S=1.84 Ω≈2 Ω,
VCO=1.22VOUTRMS=280.6 V
RO=VCO2/(0.66S)=103.737 Ω ≈100 Ω
CO=7.5/(fmRO)=1446 μF≈1500 μF
where VOUTRMS – rms value of the inverter output voltage.
Fig. 1. A single-phase inverter with a standard (EN 62040-3)
nonlinear load.
The distortions of the output voltage depend on the design of
the output filter. The output filter design was presented in
(Rymarski 2009, 2010, 2011a) and was based on the
approach of Dahono et al. 1995. The reduction of the highest
amplitude of harmonics (close to fc frequency) below 3%, and
THD below 5% (IEEE-519) was the assumption of the output
filter LFCF product value calculation. The particular LF and
CF values (for the known LFCF product value) were
calculated to minimize the reactive power in the output filter
components (Dahono et al. 1995). The considerations in this
paper are limited only to single-phase 3-level VSI with a
double edge PWM. The simplified calculation of the LF and
CF output filter parameters is:
1 VOUTRMS , 1 1
LF  CF  (1)
f c I ORMS f c VOUTRMS / I ORMS
where VOUTRMS and IORMS are the rms values of the inverter
output voltage and current. The calculated values in the
presented example are LF=1.8 mH (RLF=0.5 Ω), CF=0.85 µF,
RCF=0. The design of the output filter has a strong influence
on the discrete model of the inverter and as a result on the
design of the controller. Most authors that present control
techniques in inverters significantly lower the value of the
filter inductance and increase the value of the filter
capacitance (Ben-Brahim et al. 2003) because the value of
the output inverter impedance is proportional to LF/CF ratio.
The LF value determines how fast the output capacitor CO can
be charged when the rectifier forward bias begins. Fig. 2
shows the output voltage waveform of the inverter without
the feedback loop for a nonlinear load.
Fig. 2. Output voltage distortions for a standard nonlinear
load (without the feedback loop)
When the reverse bias of the rectifier begins, the oscillating
waveform that has the angular frequency ωRB=1/√(LFCF) and
the dumping factor ξRB=0.5ωRBRLFCF is subtracted from the
output sinusoidal voltage. When the forward bias of the
rectifier begins, the oscillating waveform that has the angular
frequency ωFB=1/√(LFCO) and the dumping factor
ξFB=0.5[ωFBLF/RO+ωFB(RLF+RS)CO] is subtracted from the
output sinusoidal voltage. The simplified analysis of the
possibility of output voltage distortion lowering is based on
the calculation of the desired voltage waveform on the input
of the filter to get the sinusoidal waveform on the output of
the inverter with a nonlinear load (Rymarski 2010). It is not
possible to force a sufficiently high step increase of the input
voltage of the output filter when the forward bias of the
rectifier begins in any control system for the output filter
inductance LF>LFmax, (Rymarski 2010).
LF max  ( RCO  RSO )( 2 / M  1) / m (2)
where ωm=2πfm, M is the modulation ratio in the operating
point of the inverter, RCO is an ESR of the load capacitor and
RSL is a sum of all the serial resistances of the nonlinear load.
In a case where RCO+RSO≈RS=2 Ω, M=0.8, fm=50 Hz the
inductance is LFmax≈5 mH. When the rectifier is forward
biased the current charging the load capacitor CO should be
forced and further this current should be reduced, or for a
high value of CO this current should change its sign. Owing to
the rectifier, the capacitor CO can be discharged only through
the load resistance RO and for a high value of CORO no
control system can discharge the load capacitor faster
(Rymarski 2010). Only systems that remember the previous
fundamental cycle (e.g. the repetitive controller) or that
additionally control the inductor and output currents (the
multi-input deadbeat controller) can effectively reduce this
type of the output voltage error. Fig. 2 presents the output
voltage of the VSI with an open feedback loop and a
nonlinear rectifier RC load (from Fig. 1).
3. VSI OUTPUT VOLTAGE DISTORTIONS IN
INSTANTENOUS CONTROLLED SYSTEMS
The traditional design of a control system is based on the
model of the plant. The discrete model of a plant (with the
linearization of the control function - Kawamura et al. 1988)
was presented in Rymarski (2009, 2010, 2011a). This model
includes the presented design of the output filter. The transfer
function of the single-phase 3-level VSI with a double edge
PWM (assuming the additional one switching period delay in
the modulator) is as follows:
VOUT ( z ) 
   
  LF 0.841  0.5RLF    LF 0.841  0.5RLF  z 1 )
 CF   
z 1    CF  I O ( z) 
1 2
1 z  z
1  z 1
 0.5 z 2 VCTRL ( z )
1  z 1  z 2
(3)
In this model the load is treated as an independent current
source IO. However every real load implements a new
feedback loop from the output voltage and has an influence
on location of the poles of the closed loop device depending
on the type and properties of the controller (e.g. time constant
of a closed loop system). The other problem concerns the
acceptable tolerance of LF and CF (1) values used in model
(Rymarski 2011b). An inverter with a discrete PID controller
with poles of the closed loop system located using the
Manabe (1998) discretized CDM (coefficient diagram
method) - is the first presented instantaneous control system
(Rymarski 2009). The control equation of the PID/CDM
controller for the VSI system is:
t0
VCTRL ( z )  1 2
VREF  CDM ( z ) 
r0  r1 z  r2 z
1 2
s0  s1 z  s2 z
 VOUT ( z )
r0  r1 z 1  r2 z  2
The difference control law of the PID/CDM controller is:
vCTRL (k )  t0vREF  CDM (k ) 
r1 r
 vCTRL (k  1)  2 vCTRL (k  2) 
r0 r0
s0 s s
 vOUT (k )  1 vOUT (k  1)  2 vOUT (k  2)
r0 r0 r0
where for the double-edge PWM and the time constant τ of
the closed loop system equal 3Tc (Tc=1/fc): r0=1, r1=0.1718,
r2=-0.1376, s0=-0.9267, s1=0.2787, s2=-0.0025, vCTRL is a
control voltage of the modulator, vREF-CDM is the reference
voltage of the control system and vOUT is normalized after
measurements. In the developed system the output of the
repetitive controller will be used in the calculation (12) of the
reference voltage. Fig. 3 shows that the oscillations for the
reverse-biased rectifier are suppressed, but unexpectedly
THD increased. When the rectifier is forward biased the
controller forces a high current charging load capacitance but
in the time instant when the rectifier is reverse biased it is
impossible to discharge the capacitor immediately however
the instantaneous feedback suppress the oscillations.
Fig. 3 Output voltage distortions for the PID/CDM controller
Similar effects occur with the simple deadbeat controller
which only measures the output voltage. In (Ben-Brahim et
al. 2003) the simple One Sample Ahead Preview controller
(its control law results in a deadbeat control) was presented.
It assumes that in the next sampling period the output voltage
will be equal to the reference voltage vOUT(k+1)=vREF(k+1). It
can be shown that the simplified model (3) is accurate
enough to design an OSAP controller. Assuming that the
modulator does not introduce an additional delay (such an
assumption would change the basic idea of OSAP) the
control equation of the OSAP-deadbeat controller for the VSI
system is:
z 1  z 1
VCTRL ( z )  2 V
1 REF  OSAP
( z)  2 VOUT ( z ) (6)
1 z 1  z 1
The difference control law of the OSAP-deadbeat controller
is:
vCTRL (k )  2vREF OSAP (k  1)  vCTRL (k  1) 
(7)
 2vOUT (k )  2vOUT (k  1)
(4) Fig. 4 presents the VSI output voltage for an OSAP-deadbeat
control system designed using the model presented in
(Rymarski 2009, 2010, 2011a). However it was necessary to
increase 50% the filter capacitor.
(5)
Fig. 4 Output voltage distortions for an OSAP-deadbeat
controller
A fuzzy controller does not depend on the previously
described model (Osterholtz 1995). Two variables of the
fuzzy-PD controller of the Mamdani type were assumed: an
error of the output voltage e=e(k)=vOUT(k)−vREF(k) and a
change of the output voltage error de=de(k)=|e(k)|−|e(k−1)|.
The variable y is a control voltage – the output of the fuzzy-
PD controller. For the step change of the load RO almost the
whole pulse of current VOUTmax/RO flows from the output filter
capacitor (the filter inductor current slowly increases). Thus
demax=VOUTmaxTc/(CFRO), for the previously assumed and
calculated values (VOUTmax=325 V, RO=46 Ω, Tc=39 µs,
CF=0.85 µF) demax=325 V. For a 10-bit analog to digital
converter with a 0 - 1023 range, if VOUTmax≡800, demax≡800.
The rules of Mamdani were used in the fuzzification. The
fuzzy sets of e, de and y are:
e={LOV (Low Output Voltage), OKOV (OK Output
Voltage), HOV (High Output Voltage)}, -1023<e<1023;
de={ED (Error Decreasing), EC (Constant Error), EI (Error
Increasing)}, -1023<de<1023;
y={LCV (Low Control Voltage), OKCV (OK Control
Voltage), HCV (High Control Voltage)}, -1<y<1.
Fig. 5 presents the fuzzy membership functions of e, de and
y. Fig. 6 shows the nonlinearity of the fuzzy-controller.
There are 9 fuzzy rules (Table 1) of the type: if [(e is ...) and
(de is ...)] then (y is... with the weight <0...1>). The weight
indicates the influence of de on the rules. A control based on
de is important for the step load, for the nonlinear load its
influence on the presented control results is low.
The standard properties of the Mamdani fuzzy controller
were used: the implication operator - minimum, the
aggregation operator - maximum, the defuzzification method
- center of gravity. Fig. 7 shows the output voltage distortions
for the Mamdani fuzzy controller
deadbeat controller is very sensitive to every change on VSI
parameters. The design of the fuzzy controller is so flexible
that it is much easier to design the model-based inverter
controller and the results of implementing both of them are
similar.

4. IMPLEMENTING THE ADDITIONAL CONTROL

LOOPS AND CONTROL INPUTS
For many years (Tomizuka et al. 1989) the best solution to
a) b) suppress the harmonics of the fundamental frequency fm of
the output waveform and to reduce a steady state error has
been to implement an additional negative feedback loop with
a discrete generator of harmonics. This loop only suppresses
the harmonics and steady state error so it requires an
additional instantaneous controller order to improve the
transient response for nonrecurring step load changes. Such a
controller is called a “repetitive controller” (RPC) (Luo et al.
c) 2006) and has a very high gain (in the range of frequencies
Fig. 5. Fuzzy membership functions of a) e, b) de and c) y below Nyquist frequency) for harmonics of fm and a DC
component. The transfer function GRPC of the repetitive
controller implemented in the control loop (Fig. 8) is (8).

Fig. 6. Surface of the transfer function of the fuzzy controller

Table 1. Fuzzy rules table

e=LOV e=OKOV e=HOV Fig. 8. Implementation of the double control loop PID/CDM
de=ED HCV, OKCV, LCV, weight=0.1
weight=0.1 weight=1
and RPC
de=EC HCV, OKCV, LCV, weight=0.5
weight=0.5 weight=0.5 K RPC z n S ( z 1 ) z  N
de=EI HCV, weight=1 OKCV, LCV, weight=1 GRPC ( z 1 )  (8)
weight=0.1 1  Q( z ) z  N
where N=fc/fm and N is even, znS(z-1) is a transfer function of
the compensator (the expected range: n=0 ÷ 10), KRPC is a
gain of the repetitive controller, Q(z) is a low pass filter with
amplification close to unity and nearly zero phase shift below
the cut off frequency. Most commonly Q(z) is designed as a
second order (Gangling et al. 2007) zero-phase-shift FIR
notch filter with the notch point located at the Nyquist
frequency. In the presented examples QRPC=1.

Fig. 7. Output voltage distortions for the fuzzy controller
The conclusion of the review of the three single-input (the
output voltage) instantaneous controllers for a VSI with a
nonlinear load testing is such that none of them can
effectively suppress the output voltage distortions. The
PID/CDM and OSAP-deadbeat controllers are designed using
that same inverter model but it can be calculated (Rymarski
2011b) that PID/CDM controller allows for a wide range of
inverter parameters. The presented single input OSAP-
Q( z)  QRPC ( z 2  4 z  6  4 z 1  z 2 ) / 16 . (9)
The transfer function of the compensator should be such that
znS(z-1)H(z-1)=1 (the unity gain and the zero phase shift) in a
frequency range up to the filter resonant frequency and for
higher frequencies |S(z-1)H(z-1)| should be strongly dumped.
H(z-1) is a transfer function of the inverter with the internal,
instantaneous PID/CDM control loop. The advantage of the
PID/CDM inner loop is the possibility of simplifying the
design of the compensator S(z-1) in the plug-in RPC and
assuming S(z-1)=1. In the presented inverter simulation n=3
was assumed for the pure lead zn. The magnitude of z3H(z-1)
will be close to 0 dB and the phase shift will be negligible in
the frequency range up to 20fm. The system with RPC is 13  12  RLF (11  1) (16)
stable if H(z-1) is stable and if for frequencies below the
Nyquist frequency (Gangling et al. 2007) the requirement g11  VDCF 0 sin(F 0Tc / 2) E(Tc / 2) (17)
(10) is fulfilled.
ξF≈0.5(1/ωF0)[(RLF+RCF)/LF] (18)
Q( z )  z n K RPC S ( z 1 ) H ( z 1 )  1 (10)
E(Tc )  exp(  F F 0Tc ) , E(Tc / 2)  exp( F F 0Tc / 2) (19)
The range of allowable values of the repetitive control gain is
F 0  1/ LF CF (20)
0<KRPC<2 (Luo et al. 2006) for an ideal compensation
znS(z-1)H(z-1) ≈1 and Q(z)≈1 in the important frequency range
up to 20fm, KRPC=1 ensures a sufficient stability margin for
the PID/CDM internal loop, for n=3 (Rymarski 2009). The
control law of the RPC controller is (11) and (12). These
equations should be connected with (5) for a
PID/CDM&RPC controller. Fig. 9 presents the VSI output
voltage distortions for the PID/CDM&RPC control loop. In
(Rymarski 2009, 2010) the PID/CDM&RPC controller was
analyzed in detail.
vRPC  OUT (k )  QRPC [(1 / 16)vRPC  OUT (k  N  2) 
Fig. 10. Output voltage distortions for a multi-input OSAP
 (4 / 16)vRPC  OUT (k  N  1)  (6 / 16)vRPC  OUT (k  N )  controller
 (4 / 16)vRPC  OUT (k  N  1)  (11)
 (1 / 16)vRPC  OUT (k  N  2)]  A 3-input OSAP controller has the highest efficiency of
suppressing output voltage distortions. However it is very
 K RPC [ Mv REF (k  n)  vOUT (k  N  n)] sensitive to every change in inverter parameters, e.g. the
initially calculated output filter capacitance CF (it works
vREF CDM (k )  vRPC OUT (k )  MvREF (k ) (12) better with at least a 20% higher value of C ).
F

5. EXPERIMENTAL MODEL MEASUREMENTS

An experimental low power model (VDC=48 V, S=200 VA,
M=0.8) of VSI with a PID/CDM&RPC controller was tested.
The choice of the best 3-level PWM scheme (the sequence of
power switch controls) is very important. The best scheme
was presented in (Rymarski 2010) and its concept is shown in
Fig. 11 (signal names are from Fig. 1).

Fig. 9 Output voltage distortions for the PID/CDM&RPC

controller

The deadbeat controller can work with an additional RPC

loop (Ben-Brahim et al. 2003). However using the filter
inductor current and the output current as additional input
variables of the controller (not only the output voltage) is
another solution. It was shown (Rymarski 2010) that an
inductor current that is inconvenient for measuring can be
satisfactorily estimated by means of the Kalman filter even
for step changes of the load. The control law of the 3-input
(vOUT, iO, iLF) OSAP is (13).
VDC
vCTRL (k )  [v REF (k  1)  11vOUT (k ) 
g11Tc (13)
 12iLF (k )  13iO (k )]
where φij are the elements of the fundamental matrix AD and
gij are the elements of the control matrix GD (Rymarski Fig. 11. 3-level PWM scheme
2011a):
11  [cos F 0Tc    F sinF 0Tc ]E(Tc ) (14) Fig. 12 presents the output voltage of the experimental
inverter. The problem with excessive current charging the
12  (1/ F 0CF ) sin(F 0Tc ) E(Tc ) (15)
load capacitor when using only the PID/CDM controller
(Fig. 12b) can be easily seen (THD of the output voltage
increases).
a) Open feedback loop b) PID/CDM controller
c) PID/CDM&RPC controller
Fig. 12. Output voltage for RO=47 Ω and CO=470 μF
6. CONCLUSIONS
This paper presents problems with suppressing the output
voltage distortions for a standard nonlinear rectifier RC load
using different types of control loops. It was shown (Fig. 3, 4,
7) that a simple control loop that measures only the output
voltage is insufficient. Two solutions for effectively
suppressing the distortions are presented. A repetitive
controller that “remembers” the output voltage error from the
previous fundamental period of the output voltage is the first
solution. This type of controller was tested in the “plug-in”
additional control loop with a PID/CDM inner loop. It was
shown (Rymarski 2009, 2010) that the PID/CDM inner
controller (the closed loop system has a unity magnification
and a low phase shift in the important frequency range) is
effective for cooperating with a repetitive controller. The
second solution of the improvement in control is controlling
not only the output voltage but also the filter inductor current
and the output current. This is the best solution when the
deadbeat control is implemented. The simulations show that a
multi-input deadbeat control suppresses distortions slightly
better but it is very sensitive to changes in the parameters of
the inverter and the load. That is why the PID/CDM&RPC
controller is the better choice for the VSI. The presented
output filter parameter calculations, control laws and PWM
scheme are ready for implementation in VSI designs.
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