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VHDL - IISc Prof. Kuruvilla PDF
VHDL - IISc Prof. Kuruvilla PDF
Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese
Introduction / Features 2
• Evolution • Open standard
– VHDL – VHSIC Hardware • Human readable
Description Language
• Portability
– DOD, USA 1970’s & 1980’s
– IEEE 1076.3 • Documentation, Simulation,
Synthesis
• Schematic • Hierarchical design (top-down or
– Connectivity Information (Net list) bottom-up)
– Hierarchy, but bottom-up • Higher Level constructs
– Portability (Schematic database, • Supports library based design
Libraries)
– Controller (FSM) Design external • Strict Type checking
– Design Description
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1
Schematic 3
source: linuxtoys.org
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VHDL Features 4
• Entity – Interface Specifications • Function
• Architecture – Functionality
e.g. 4 bit comparator
a(3)
b(3)
a
a(2)
a(1)
b(1)
a(0)
b(0)
Function
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2
Equality Comparator 5
-- 4 bit equality comparator
bit - ‘0’, ‘1’
library ieee; std_logic – ‘0’, ‘1’, ‘Z’, …
use ieee.std_logic_1164.all;
in out
entity eqcomp is
port (a, b: in std_logic_vector(3 downto 0);
equals: out std_logic);
end eqcomp; buffer inout
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Equality Comparator 6
• Comments start with -- anywhere on • Identifiers
the line – Alphabetic, Numeric or
underscore characters
• Library Packages – Not case sensitive
Components, Functions, Procedures, – The first character must be an
Data Objects alphabet
– The last character cannot be an
• Mode underscore
– in, out, inout, buffer – Two underscores in succession
are not allowed
• Range: downto, to (MSbit, LSbit)
– Bit order, Byte order (Little
Endian, Big Endian)
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3
Syntax, Operators 7
• Architecture Body • Logical Operators
– Architecture declaration – and, nand, or, nor, xor, xnor, not
• Component declarations
• Type declarations These are defined for data type
• Constant declarations “bit” and “boolean”
• Signal declarations For “std_logic” data type these
• Function, Procedure operators are overloaded in
definitions “ieee.std_logic_1164” package
– Architecture statement
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Operators 8
• Arithmetic Operators • These operators are defined
– +, -, *, / for “integer” and “real”
– ** (exponentiation) data types
– mod (modulo division) • For “std_logic” data type,
– rem (modulo remainder) these operators are
– abs (absolute value) overloaded in
A mod B = A – B * N “ieee.std_logic_unsigned”
A rem B = A − A / B ∗ B package
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4
Operators 9
• Relational Operators • Shift Operators
=, >, <, <=, >=, /=
sll (shift left logical), srl
These operators are defined for sla (shift left arithmetic), sra
“integer” and “real” data types rol (rotate left), ror
For “std_logic” data type, these
operators are overloaded in These operators are defined for
“ieee.std_logic_arith” package “bit” and “boolean” data types
For “std_logic” data type, these
operators are overloaded in
“ieee.std_logic_arith” package
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Operators 10
• Aggregate operator • Concatenation operator
Applied to elements of Concatenate different size
same type and size arrays of the same element
type.
signal a, b, c: std_logic;
signal tmp: std_logic_vector(2 type byte is array (7 downto 0)
downto 0); of bit;
tmp <= (a, b, c); signal count: byte;
count <= “010” & “00110”;
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5
Operators - precedence 11
1. Logical operators Increasing precedence from 1 to 6
2. Relational operators Operators of same category same
precedence.
3. Shift operators Left to right evaluations.
4. Adding operators “not” operator has precedence 6
5. Multiplying operators
6. Miscellaneous operators
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• Simulation / Synthesis
Synthesis
• Area / Speed Equations /
Logic
Simulation
Netlist
• FPGA / PLD
Constraints PAR /
Fitting
Static Timing
Configuration Analysis
bit stream Timing Model
Timing
Programming Simulation
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6
Design Flow - Tools 13
• VHDL Editor
• Synthesis Tool
• Constraint Editor
• Place and Route (PAR) / Fitting
Tool
• VHDL Simulator
– Functional/Behavioral simulation
– Logic Simulation
– Timing Simulation
• Static Timing Analysis Tool
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7
Data flow Model 15
-- 4 bit equality comparator
architecture arch_eqcomp of
library ieee; eqcomp is
use ieee.std_logic_1164.all; begin
equals <= (a(3) xnor b(3)) and
entity eqcomp is (a(2) xnor b(2)) and
(a(1) xnor b(1)) and
port (a, b: in std_logic_vector(3
downto 0); (a(0) xnor b(0)) ;
end arch_eqcomp;
equals: out std_logic);
end eqcomp;
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Concurrency 16
a x
a y b
c
y
b z d z
e
f
8
Behavioral Model 17
library ieee; architecture arch_eqcomp of
use ieee.std_logic_1164.all; eqcomp is
begin
entity eqcomp is eqproc: process (a, b)
port (a, b: in std_logic_vector(3 begin
downto 0); if (a = b) then
equals: out std_logic); equals <= ‘1’;
end eqcomp; else
equals <= ‘0’;
end if;
end process;
end arch_eqcomp;
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Process 18
• Sequential body • Higher level constructs
– The way simulator computes – if … then,
– Synthesis is based on the – case … when
statements – for … loop
• Process Body – while … loop
– Process declarative part
• Variable, Constant declarations
• Type declaration
• Function, Procedure
definitions
– Process statement part
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9
Process 19
• Sensitivity list
eqproc: process (a) – Compatibility between
begin simulation model and
if (a = b) then synthesis model (sensitivity
list – RHS of assignments,
equals <= ‘1’; and Conditions)
else – Focus of synthesis tool is the
equals <= ‘0’; structure of the circuit, not
end if; the real time behavior of the
end process eqproc; circuit. Simulation tool
focuses on latter
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Using Process 20
process (a,b,c)
begin
a y 0.
b y <= f1 (a,b,c)
c z
0
z <= f2 (a,b,c)
end process;
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10
Multiple processes, concurrency 21
a y
d eqproc: process (a, d, e)
e z begin
0
end process eqproc;
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Hierarchy 22
Component
Component Signal
a(3)
o
i b(3) signal
u
n t
p a(2)
p b(2)
u u equals
t t a(1)
s b(1)
s
a(0)
b(0)
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11
Structural Code 23
library ieee; architecture arch_eqcomp of eqcomp is
use ieee.std_logic_1164.all;
component xnor2
entity eqcomp is port (i1, i2: in std_logic, o1: out
port (a, b: in std_logic_vector(3 downto 0); std_logic);
equals: out std_logic); end component;
end eqcomp; component and4
port (i1, i2, i3, i4: in std_logic, o1: out
std_logic);
end component;
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Structural Code 24
c1: xnor2 port map (a(3), b(3), int1);
a(3) int1
c2: xnor2 port map (a(2), b(2), int2); b(3)
i1
i1 o1 i2 o1
i2 i3
i4
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12
Components 25
-- Components library ieee;
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
entity and4 is
entity xnor2 is port (i1, i2, i3, i4: in std_logic, o1:
port (i1, i2: in std_logic, o1: out out std_logic);
std_logic); end and4;
end xnor2;
architecture arch_and4 of and4 is
architecture arch_xnor2 of xnor2 is begin
begin o1 <= i1 and i2 and i3 and i4;
o1 <= i1 xnor i2; end arch_and4;
end arch_xnor2;
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Component instantiation 26
• Port map
– Formal to actual mapping
• Positional association
xnor2 port map (a(3), b(3), int1);
• Named Association
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13
Naming signals, ports 27
signal int1, int2, int3, int4: std_logic;
for i in 0 to 3 generate
signal int: std_logic_vector(3 downto 0); c: xnor2 port map (a(i), b(i), int(i));
end generate;
c1: xnor2 port map (a(3), b(3), int1);
c2: xnor2 port map (a(2), b(2), int2);
c3: xnor2 port map (a(1), b(1), int3); c4: and4 port map (int(0), int(1), int(2),
c4: xnor2 port map (a(0), b(0), int4); int(3), equals);
c5: and4 port map (int1, int2, int3, int4,
equals);
• open
c1: xnor2 port map (a(3), b(3), int(3));
c2: xnor2 port map (a(2), b(2), int(2)); when a component is instantiated if any of
its output is unused, those can be mapped
c3: xnor2 port map (a(1), b(1), int(1)); to ‘open’
c4: xnor2 port map (a(0), b(0), int(0));
c5: and4 port map (int(3), int(2), int(1), int(0), unused inputs must be tied to appropriate
equals); logic levels
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Simulation 28
• Types of Simulation
– Trace Simulation
• Steps
• Analog
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14
Simulation 29
• Simulation Time
D Q D Q
Comb
CK CK
– Event time at which
computation happens
CLK
– Events are ordered
chronologically
CLK
• Simulation Cycle
– Resolving concurrency, by
• Sequential Circuit sequential computation
– Cycle based simulation – Delta delay
• Simulated every clock cycle
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15
Simulation Cycle – Functional/Logic 31
a x
b
y
c y
Logic Simulation 32
• Issue 2: Functional/ Logic • How small should be the delta
simulation delay (for simulator
– Elements have zero delay implementation)?
– Solution: delta delay for – Smaller than the smallest time
resolving sequence. delay in the circuit,
• Events – Smaller than smallest change in
any input signal
– Events (on external signals and
one happens on internal signals
due to computation) are ordered
in simulation time and are
handled in the same order.
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Simulation Cycle - Feedback 33
S y
Z Z
R
architecture dflow of bff is
begin Y
Z <= R nand Y;
Y <= S nand Z; R
end dflow;
Time(ns) S R Y Z S
0 1 0 0 1
0 100 100 + d 100 + 2d
100 0 1
100 + d 1
Solution: Event driven computation
100 + 2d 0
Keep computing till stable.
100 0 1 1 0
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17
Process – Correct usage 35
process (a, b, c, d, e, f, x, y)
begin
0.
x <= f1 (a, b);
0
y <= f2 (c, d, x);
0
z <= f3 (e, f, y);
end process;
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18
Synthesis 37
• eql <= ‘1’ when (a = b) else ‘0’; Exponential Complexity
a3 a2 a1 a0 b3 b2 b1 b0 eql Width 4 2 exp 8 terms
0 0 0 0 0 0 0 0 1 Width 8 2 exp 16 terms
0 0 0 0 0 0 0 1 0
Operator Inferencing = ex-or / ex-
nor
y <= a + b;
0 0 0 1 0 0 0 0 0
y <= x + 1;
1 1 1 1 1 1 1 1 1
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Data Objects 38
• Classes • Constants
Constants, Signals, Variables, Files – For readability and easy modification
of code
constant width: integer := 8;
• Syntax
class object_name: data type;
• Variables
– Declared in sequential bodies
• Signals (process, functions, procedures).
Signals declared in architecture – Used in simulation extensively.
declarative region and used anywhere Indexing, temporary storage etc..
(architecture, processes, functions, Synthesis is not well defined in non-
procedures) trivial cases.
signal carry: std_logic_vector(7 variable count: integer range 0 to
downto 0); 255;
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19
Data Objects, Types 39
• Files • Data Types
Used in test benches to store input – Scalar: enumerated, integer,
vectors and to write output vectors. float
Screen output
– Composite: array, record
type logic_data is file of character;
file logical_name: logic_data;
file logical_name: logic_data is • Enumerated
“inpvec.dat”;
type state_type (init, sample, wait,
file logical_name: logic_data open
read_mode is “inpvec.dat”; interrupt, out);
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20
Data Types, Scalar Predefined 41
• Integer • Physical Types
type integer is range -2147483647 to type time is range -2147483647 to
2147483647; 2147483647
units
Range fs;
variable count: integer range 0 to ps = 1000 fs;
255; ns = 1000 ps;
constant width: integer := 16; us = 1000 ns;
ms = 1000 us;
• Floating types sec = 1000 ms;
min = 60 sec;
type real is range –1.0E38 to hr = 60 min;
+1.0E38 end units;
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Subtypes 42
• Subtype • What is the difference between
the above two?
– subtype my_int is integer range
48 to 56; – In the first one, all the operators
– subtype “UX01” is resolved defined for integer works. In the
std_ulogic range ‘U’ to ‘1’; second case various operators
need to be overloaded for the
• Type and subtype new my_int type.
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21
User defined Data Types 43
• User defined • Array Types
– type MVL is (‘U’, ‘O’, ‘1’, ‘Z’);
type word is array (15 downto 0) of bit;
– type index is range 0 to 15;
signal address: word;
– type word_length is range 31
downto 0;
– type volt_range is 3.3 downto 1.1; • Unconstrained Array (constrained
– type current is range 0 to 1E9 at the time of object declaration)
units
type bit_vector is array (natural range
nA; <>) of bit;
uA = 1000 nA; type std_logic_vector is array (natural
mA = 1000 uA; range <>) of std_logic;
amp = 1000 mA; signal a: std_logic_vector(3 downto 0);
end units;
– subtype filter_current is current
range 10 uA to 5 mA;
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22
Data Types - Composite 45
• Array assignments
busa.buffer_inp <= vec;
busb.buffer_inp <= busa.buffer_inp signal row: std_logic_vector(7 downto
busb.enable <= ‘1’; 0);
busc <= busb; row <= (‘1’, ‘0’,’1’,’1’, ‘1’, ‘1’,’1’,’1’);
row <= (7 =>’1’, 6 => ’0’, others => ’1’);
busa.buffer_out <= busa.buffer_inp row <= “10111111”
when (busa.enable = ‘1’) else row <= (‘1’, ‘0’, others => ‘1’);
(others => ‘Z’); row <= X”BF”
row <= (others => ‘0’);
• Alias row <= (others => ‘Z’);
signal address: std_logic_vector(31
downto 0); Base: Hexadecimal – X,
Octal – O,
alias top_ad: std_logic_vector(3 Binary - B
downto 0) is address(31 downto 28);
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Concurrent statements 46
• with-select-when output_signal: output(s),
sel: input
• when-else signals in expra, exprb, …, exprx: inputs
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23
with … select 47
with a select with a select
y <= ‘0’ when “00”, y <= b when “00”,
‘0’ when “01”, not(b) when “01”,
‘0’ when “10”, c when “10”,
‘1’ when “11”, b when “11”,
‘0’ when others; c when others;
• Truth Table
a(1) a(0) y
0 0 0
0 1 0
1 0 0
1 1 1
y = a(1) and a(0)
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with … select 48
Truth Table
a(1) a(0) b c y
0 0 0 x 0
0 0 1 x 1 Equation
0 1 0 x 1
y = a(1)/ and a(0)/ and b or
0 1 1 x 0
a(1)/ and a(0) and b/or
1 0 x 0 0
1 0 x 1 1 a(1) and a(0)/ and c or
1 1 0 x 0 a(1) and a(0) and b
1 1 1 x 1
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24
with - select 49
• For all the mutually exclusive values of an • It is very easy to work out the equations
input signal (‘select’ signal) or signals, from the descriptions, each choice
output is expressed, sometime as function forming a minterm or ‘OR’ of minterms
of other inputs (in case if an expression is used).
• In the simplest case, when output values • For Simulator, event on any input signal
are specified, it is a plain truth table and (select signal, signals in expression)
the choices specify the minterms of input would trigger a computation of the output
signals signal
• When output is expressed as a function of • Synthesis tool may not use the truth table,
other inputs for a choice of ‘select’ signal, if the standard operators/structures could
that may expand to multiple rows of truth be inferred from the code
table.
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With-select-when 50
4-to-1 Multiplexer • Equations
a
y(i) = a(i) and sel(1)/ and sel(0)/ or
b y b(i) and sel(1)/ and sel(0) or
c c(i) and sel(1) and sel(0)/ or
d d(i) and sel(1) and sel(0)
sel
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25
With-select-when 51
• Example - choices
a
b y with numb select
c prime <= ‘1’ when “010” | “011” | “101”
with b select | 111”,
y <= func1(a, c) when value_1, ‘0’ when others;
func2(a, c) when value_2,
00.
funci(a, c) when value_i,
00.
funcn(a, c) when others;
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when - else 52
• Syntax • General conditions
e.g. condition1: (a = b)
output_signal <= expa when cond1 else condition2: (d > 3)
expb when cond2 else
• Priority
00..
expx when condx else
expy;
• Truth Table ?
output_signal: output(s), • Yes, much more abstract
condi: condition in terms of inputs
expi: expression in terms of inputs
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26
when - else 53
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when - else 54
p(1) p(0) q(1) q(0) r(1) r(0) y
0 0 0 0 0 0 c
0 0 0 0 0 1 c
0 0 0 0 1 0 b
0 1 1 0 0 0 c
0 1 1 0 0 1 c
0 1 1 0 1 0 b
1 1 1 1 1 1 c
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27
when - else 55
• For the simulator, an event on any of
y <= a when (p > q) else the signals in conditions or
b when (r = 2) else expressions will trigger the
computation of the output signal.
c; • Synthesis tool may not use the truth
• In the code above, first condition table, if the standard operators/
translates to all those values of p and structures could be inferred from the
q for which (p > q). i.e. it translates code
to multiple rows of the truth table. In
this case, signal ‘r’ is a don’t care
• When it comes to second condition,
it translates to all those values of p, q prio <= “00” when (a = ‘1’) else
and r for which p <= q and r = 2. “01” when (b = ‘1’) else
Once again, it means multiple rows
of the truth table. “10” when (c = ‘1’) else
“11”;
Kuruvilla Varghese
when - else 56
en architecture dflow of transc is
dir
begin
b <= a when (dir = ‘1’ and en = ‘1’) else
a b (others => ‘Z’) ;
a <= b when (dir = ‘0’ and en = ‘1’ ) else
(others => ‘Z’ ) ;
library ieee; end dflow;
use ieee.std_logic_1164.all;
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28
Sequential Statements 57
• if-then-else a, b, signals of cond1: inputs
• case-when y: output
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if-then-else 58
• General conditions • Equations
• Priority
y = a and cond1 or
• Syntax 2
b and cond2 and not(cond1) or
if cond1 then c and cond3 and not(cond2) and
not(cond1) or
y <= a;
d and not(cond3) and not(cond2)
elsif cond2 then and not(cond1)
y <= b;
elsif cond3 then
y <= c;
else
y <= d;
end if;
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29
if-then-else 59
• Equivalent to when-else,
but if cond1 then
• Multiple outputs y <= a; z <= a and b;
elsif cond2 then
• Nesting
y <= b; z <= c;
elsif cond3 then
y <= c; z <= a;
a Y else
b z y <= d; z <= b;
c
end if;
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if-then-else 60
• More complex behaviour/structure can be • Equations
specified by nesting. E.g. if there are
multiple outputs and we may not be able
y = a and cond1 and cond2 or …
to specify all outputs for same conditions
if cond1 then
if cond2 then
y <= a;
elsif
00.
end if;
elsif
00.
end if;
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30
if-then-else 61
if cond1 then
if cond1 then y <= a;
y <= a; else
end if; y <= y;
cond1
end if;
a
y
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31
Implied Memory / Inferred latch 63
• It is difficult to expose this error in
simulation, as just verifying all
conditions would not be sufficient.
• Suppose, one output was missing in
condition 3, and the previous
condition simulated has the same
value expected of this output in
condition 3, then output will be
correct.
• If the designer has inadvertently
missed specifying an output, then
working out the condition for
exposing such an error would be
remote.
Kuruvilla Varghese
Case-when 64
• Syntax • All mutually exclusive values
of sel_signal need to be
case sel_signal is specified
when value1 => • No priority, Truth table
(statements)
when value2 =>
• Equivalent to with-select, but
(statements) • Multiple Outputs
000.. • Nesting
when valuex =>
(statements)
when others =>
(statements)
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32
Case-when 65
• Equations
case sel is x = a and (decode of sel = val1) or
when val1 => c and (decode of sel = val2) or …
x <= a;
y = b and (decode of sel = val1) or
y <= b;
d and (decode of sel = val2) or …
when val2 =>
x <= c;
y <= d; • Implied memory, if any output is not
when val3 => specified in all choices of selection
000 signal.
end case;
Kuruvilla Varghese
Case-when Nesting 66
• “case … when …’’ can be nested • Equation
with “if .. then ..’’ to specify
complex structure / behavior.
y = a and decode of (sel = val1)
case sel is and cond2 or 0
when val1 =>
if cond2 then
y <= a;
elsif
00.
end if;
when val2 =>
0
end case;
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33
Case-when 67
library ieee;
use ieee.std_logic_1164.all;
entity dmux1t4 is
port (y: in std_logic_vector(3 downto 0);
a
3 2 1 0
Kuruvilla Varghese
Demultiplexer 68
process (s, y) when others =>
begin a <= “0000”; b <= “0000”; c <= “0000”;
case s is d <= “0000”;
when “00” => end case;
a <= y; b <= “0000”; c <= “0000”; end process;
d <= “0000”; end arch_dmux1t4;
when “01” =>
b <= y; a <= “0000”; c <= “0000”;
d <= “0000”;
when “10” =>
c <= y; a <= “0000”; b <= “0000”;
d <= “0000”;
when “11” =>
d <= y; a <= “0000”; b <= “0000”;
c <= “0000”;
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34
Demultiplexer 69
process (s, y)
begin when others =>
a <= “0000”; b <= “0000”; a <= “0000”; b <= “0000”;
c <= “0000”; d <= “0000”;
c <= “0000”; d <= “0000”;
end case;
case s is end process;
when “00” =>
end arch_dmux1t4;
a <= y;
when “01” =>
b <= y;
when “10” =>
c <= y;
when “11” =>
d <= y;
Kuruvilla Varghese
Loops 70
• Concurrent: generate
• Sequential: loop
• Generate
– Equations
– Component Instantiations
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35
Generate - Example 71
carry(0)
sum(0)
a(0)
a b(0) carry(1)
sum
b
cin
sum(1)
a a(1)
b b(1) carry(2)
b
cout
cin
a
cin
carry(7) sum(7)
a(7)
b(7) carry(8)
Kuruvilla Varghese
Generate 72
carry(0)
• Equations
sum(0) for i in 0 to 7 generate
a(0)
b(0) carry(1) sum(i) <= a(i) xor b(i) xor carry(i);
carry(i+1) <= (a(i) and b(i)) or ((a(i) or
b(i)) and carry(i));
sum(1)
a(1) end generate;
b(1) carry(2)
• Component Instantiations
for i in 0 to 7 generate
u1: fulladd port map (carry(i), a(i), b(i),
carry(7) sum(7)
a(7) sum(i), carry(i+1));
b(7) carry(8) end generate;
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Conditional Loops 73
• if ... Generate (Concurrent • If the condition is true, then the
statement, no else /elsif) generate is done
• Useful to generate irregular
loop_label: if (condition / expression) structures, i.e. Conditional on
generate loop index (e.g. i = 2) different
000.. structures can be generated
000..
end generate;
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Loop Control 75
• Exit • Next
exit; next;
exit [loop_label]; next [loop_label];
exit [loop_label] when condition; next [loop_label] when condition;
if condition then
if condition then
exit;
next;
end if;
end if;
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clk
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38
Flip Flop - Simulator 77
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39
FF – Synthesis, Simulation 79
• clk’event is a predefined attribute
which is true whenever there is an
process (clk) event on the signal ‘clk’. The
begin statement clk’event and clk = ‘1’,
if (clk’event and clk = ‘1’) then would mean the positive edge of
q <= d; clock. Statement clk’event would be
end if; redundant for simulation.
end process; • The statement clk’event and clk =
‘1’, would also be true when clk
transits from ‘U’ to ‘1’ (std_logic),
this could occur at the beginning of
simulation.
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FF – Synthesis, Simulation 80
• To avoid this, functions
‘rising_edge(clk)’ and
‘falling_edge(clk)’ in
ieee.std_logic_1164 package
could be used
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40
D Latch 81
process (clk, d)
clk
begin
q if (clk = ‘1’) then
q <= d;
end if;
Synthesis Tool end process;
process (clk)
begin
if (clk = ‘1’) then
q <= d;
end if;
end process;
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D Latch 82
• ‘clk’ in the sensitivity list invokes • wait
process for computation only on clock
edges, hence ‘d’ is added to sensitivity
list to respond to changes in the input ‘d’ process
begin
• The statement clk = ‘1’ takes care of the
transparent latch behavior. if (clk = ‘1’) then
• Implied memory takes care of the latch
q <= d;
operation end if;
wait on clk, d;
end process;
• Equivalent concurrent statement
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41
Wait 83
• wait on sensitivity-list;
• wait until boolean-expression;
• wait for time-expression;
• Examples
wait on clk, d;
wait until count = 10;
wait for 10 ns;
wait on clk for 17 ns;
wait until sum > 100 for 50 ns;
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Asynchronous Reset 84
process (clk, reset)
q begin
d
if (reset = ‘1’) then
clk q <= ‘0’;
AR elsif (clk’event and clk = ‘1’) then
q <= d;
end if;
process (clk) end process;
begin
if (clk’event and clk = ‘1’) then
q <= d; • Concurrent statements
end if;
end process; q <= ‘0’ when (reset = ‘1’) else
d when (clk’event and clk = ‘1’);
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42
Registers with comb circuit 85
process (clk)
begin a
d q
if (clk’event and clk = ‘1’) then b
q <= a xor b; clk
end if;
end process;
• This means a single process can
code registers preceded by any
combinational circuit
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process (clk)
begin
comb
if (clk’event and clk = ‘1’) then
a
d q
b
** code for combinational
circuit ** clk
end if;
end process; • Note: Any assignment you do
here will have flip-flop/register
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43
Registers with comb circuit 87
• Combinational circuit at the
input ‘d’ can be coded within the
clk’event and clk = ‘1’ statement
• This code being in process
should be using if … then, case
… when, for … etc.
• Any signal connected to ‘d’ is
synchronous with clock, hence
such code always represent
synchronous behavior
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FF Synchronous Reset 88
• Asynchronous Reset
d q
process (clk, reset)
clk
begin
SR if (reset = ‘1’) then
q <= ‘0’;
elsif (clk’event and clk = ‘1’) then
q <= d;
end if;
end process;
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44
FF Synchronous Reset 89
process (clk)
d q begin
clk
if (clk’event and clk = ‘1’) then
if (reset = ‘1’) then
SR
q <= ‘0’;
else
q <= d;
• if … then allows nesting and
end if;
synchronous circuit can be coded end if;
• Nesting isn’t possible with
concurrent statement, hence
doesn’t make sense to code
synchronous circuit.
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d 0 D Q q
1
‘0’
reset
clk CK
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45
Synchronous circuit - synthesis 91
d q r
process (clk) ck ck
begin clk
if (clk’event and clk = ‘1’) then
q <= d;
r <= q;
• Above process executes sequentially, but
end if;
both the assignments happens after ‘t +
end process; delta’ time. This along with implied
memory makes cascaded flip-flops.
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Shift Register 92
ck ck ck ck
clk
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46
Shift Register 93
process (clk)
begin process (clk)
if (clk’event and clk = ‘1’) then begin
q(0) <= d(0); if (clk’event and clk = ‘1’) then
for i in 0 to 6 loop
q(i+1) <= q(i); q <= q(6 downto 0) & d(0);
end loop; end if;
end if; end process;
end process;
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Counter 94
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47
Counter 95
library ieee;
d q count use ieee.std_logic_1164.all;
+1
q use ieee.std_logic_unsigned.all;
clk clk
AR
entity count8 is port
reset (clk, reset, load: in std_logic;
din: in std_logic_vector(7 downto 0);
count: out std_logic_vector(7 downto 0));
end count8;
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Counter 96
count <= q;
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48
Coding Scenario 97
Topmost Level
Structural code
Components
Structural code
Concurrent statements
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Library, Packages 98
library ieee; use ieee.std_logic_1164.all;
d q
49
Library, Packages 99
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50
Writing component in Package 101
library ieee; entity dff is
use ieee.std_logic_1164.all; port (d, clk: in std_logic; q: out std_logic);
end dff;
package xy_pkg is architecture behave of dff is
component dff begin
port (d, clk: in std_logic; process (clk)
q: out std_logic);
begin
end component;
if (clk'event and clk = '1') then
end xy_pkg;
q <= d;
library ieee; end if;
use ieee.std_logic_1164.all; end process;
end behave;
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Instantiation 103
• Positional association
c1: dff port map (inp, sclk, int1);
• Named association
c1: dff port map (clk => sclk,
d => inp, q => int1);
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Generic 104
library ieee;
• Generic components use ieee.std_logic_1164.all;
• Components that suite
various data size, storage package xy_pkg is
component count
sizes etc. generic (size: integer := 4);
• e.g. Counter with port (clk, rst: in std_logic;
count: out
configurable output width std_logic_vector(size-1 downto 0);
• e.g. FIFO with configurable end component;
end xy_pkg;
width, configurable depth
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52
Generic Counter 105
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Instantiation 106
• Default value – 4
entity nand2 is
• Default Usage generic (tplh: time := 3 ns; tphl: time := 2
c1: count port map (clock, rst, co); ns);
port (i1, i2: in std_logic; o1: out std_logic);
end nand2;
• Generic
c1: count generic map (8) port 0000.
map (clock, rst, co);
o1 <= i1 nand i2 after (tplh + tphl) /2;
0000.
• Any number of parameters,
any type
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Generic in Hierarchy 107
Generics of components can be
mapped to the generics of the
architectures that instantiate those
components.
Configuration 108
• Configuration Specification • Configuration Declaration
– Binds the components – Binds a top level entity to one of
instantiated in the architecture to the many architectures it has.
entity-architecture pair in any – Bind the components used at any
design library. level of hierarchy to an entity-
– Specified in the architecture architecture pair in any design
declaration region library.
– Separate design unit.
– Hierarchical
– Specified at the end
Library & Packages, Entity,
Architecture 1,
Architecture 2, …, Configuration
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54
Configuration Specifications 109
library ieee, hs_lib, cm_lib;
use ieee.std_logic_1164.all;
a s1
sum
b
cin entity full_adder is
a s2 port (a, b, cin: in std_logic;
b s5 sum, cout: out std_logic);
b s3
cout end full_adder;
cin
a s4
cin
architecture fa_str of full_adder is
component xor2
port (d1, d2: in std_logic;
dz: out std_logic);
end component;
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Configuration Specifications 111
begin
x1: xor2 port map (a, b, s1); a s1
sum
x2: xor2 port map (s1, cin, sum); b
cin
a1: and2 port map (s2, a, b); s2
a
a2: and2 port map (s3, b, cin); b s5
a3: and2 port map (s4, a , cin); b s3
cout
cin
o1: or2 port map (s2, s3, s5); s4
a
o2: or2 port map (s4, s5, cout); cin
end fa_str;
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56
Packages: Operators, Functions 113
ieee.std_logic_1164 (ieee) subtype std_logic is resolved std_ulogic;
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Packages: Operators, Functions 115
ieee.std_logic_arith (synopsys) Overloaded operators
• Arithmetic Operators
type unsigned is array ( natural +, -, *, /
range <> ) of std_logic;
• Relational Operators
type signed is array ( natural range
<> ) of std_logic; <, >, =, /=, <=, >=
• Shift Operators
SHR, SHL
(unsigned – logical
signed – arithmetic)
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58
Packages: Operators, Functions 117
ieee.numeric_std (ieee) Overloaded operators
• Arithmetic Operators
type unsigned is array ( natural range <> +, -, *, /, abs, rem, mod
) of std_logic;
type signed is array ( natural range <> )
• Relational Operators
of std_logic; <, >, =, /=, <=, >=
• Logical operators
and, nand, or, nor, xor, xnor, not
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59
Type Conversions 119
• Automatic sl_vect <= std_logic_vector(usg_vect)
sl_vect <= std_logic_vector(sg_vect)
– Between base types and
usg_vect <= unsigned(sl_vect)
subtypes
sg_vect <= signed(sl_vect)
• Using Conversion Functions
– e.g. to_integer, conv_integer signed(“1101”)
• Type Casting
between signed, unsigned,
and std_logic_vector
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60
Arithmetic 121
signal a, b, s: unsigned(7 downto 0) signal a, b, s: unsigned(7 downto 0);
; signal s9: unsigned(8 downto 0) ;
signal s9: unsigned(8 downto 0) ; signal cin: std_logic ;
signal s7: unsigned(6 downto 0) ; -- Carry in
s9 <= (a & '1') + (b & cin);
-- Simple Addition, no carry out s <= s9(8 downto 1) ;
s <= a + b ;
-- Carry Out in result
s9 <= ('0' & a) + ('0' & b) ;
-- For smaller result, slice input
arrays
s7 <= a(6 downto 0) + b(6 downto 0)
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Delay Modeling 123
• Inertial delay, • Two parameters:
Minimum pulse width required for
• Transport delay the device to recognize the level
change (i.e. for the input to cross the
threshold)
• Inertial delay Propagation delay of the device
Models delay through capacitive
networks and through gates with
threshold values
Pulse rejection value less than the
inertial delay with “reject” clause.
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Delay Modeling 125
entity delaym is
end entity; 5 6 7 4 6 22 6 2
a
architecture arch_d of delaym is
signal a, x, y, z: bit ;
begin
x
a <= ‘1’ after 5 ns, ‘0’ after 11 ns,
‘1’ after 18 ns, ‘0’ after 22 ns,
‘1’ after 28 ns, ‘0’ after 30 ns, y
‘1’ after 32 ns, ‘0’ after 38 ns,
‘1’ after 40 ns;
z
x <= a after 5 ns;
y <= reject 3 ns inertial a after 5 ns;
z <= transport a after 5 ns; 5 10 15 20 25 30 35 40 45 50
end arch_d;
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d q library ieee;
clk
use ieee.std_logic_1164.all;
entity dff is
port (d, clk: in std_logic; q: out
std_logic);
end dff;
clk
ts th
architecture tcheck of dff is
d constant setup_time: time := 3 ns;
tco constant hold_time: time := 1 ns;
q begin
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63
Timing Example 127
process (d, clk) if (clk’event and clk = ‘1’) then
variable d_levent, clk_levent: time; assert now = 0 ns or (now – d_levent)
begin
>= setup_time
-- behavioral code of dff report “Setup time violation !”
if (clk’event and clk = ‘1’) then severity note;
q <= d after 10 ns; clk_levent := now;
end if; end if;
if d’event then end process;
assert now = 0 ns or (now – clk_levent) end tcheck;
>= hold_time
report “Hold time violation !”
severity note;
d_levent := now;
end if;
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Assert 128
Syntax
Levels
Note
Warning
Error
Failure
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64
Example - Demultiplexer 129
process (s, y) when others =>
begin a <= “0000”; b <= “0000”; c <= “0000”;
case s is d <= “0000”;
when “00” => end case;
a <= y; b <= “0000”; c <= “0000”; end process;
d <= “0000”; end arch_dmux1t4;
when “01” =>
b <= y; a <= “0000”; c <= “0000”;
d <= “0000”;
when “10” =>
c <= y; a <= “0000”; b <= “0000”;
d <= “0000”;
when “11” =>
d <= y; a <= “0000”; b <= “0000”;
c <= “0000”;
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architecture arch_dmux1t4 of dmux1t4 is c(0) <= y(0) and s(1) and not(s(0));
begin c(1) <= y(1) and s(1) and not(s(0));
c(2) <= y(2) and s(1) and not(s(0));
c(3) <= y(3) and s(1) and not(s(0));
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65
Example - Demultiplexer 131
architecture arch_dmux1t4 of dmux1t4 is
d(0) <= y(0) and s(1) and s(0); begin
d(1) <= y(1) and s(1) and s(0);
d(2) <= y(2) and s(1) and s(0); glp: for i in 0 to 3 generate
d(3) <= y(3) and s(1) and s(0); a(i) <= y(i) and not(s(1)) and not(s(0));
b(i) <= y(i) and not(s(1)) and s(0);
end arch_dmux1t4; c(i) <= y(i) and s(1) and not(s(0));
d(i) <= y(i) and s(1) and s(0);
end generate;
end arch_dmux1t4;
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66
When … else / Case 133
architecture arch_dmux1t4 of dmux1t4 is
architecture arch_dmux1t4 of dmux1t4 is begin
begin process (s, y)
begin
a <= y when (s = "00") else "0000"; a <= "0000"; b <= "0000"; c <= "0000";
b <= y when (s = "01") else "0000"; d <= "0000";
c <= y when (s = "10") else "0000"; case s is
d <= y when (s = "11") else "0000"; when "00" => a <= y;
when "01" => b <= y;
end arch_dmux1t4; when "10" => c <= y;
when "11" => d <= y;
when others => null;
end case;
end process;
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If … then 134
architecture arch_dmux1t4 of dmux1t4 is elsif (s = "10") then
begin c <= y; a <= "0000"; b <= "0000";
d <= "0000";
process (s, y) else
begin d <= y; a <= "0000"; b <= "0000";
c <= "0000";
if (s = "00") then end if;
a <= y; b <= "0000"; c <= "0000"; end process;
d <= "0000"; end arch_dmux1t4;
elsif (s = "01") then
b <= y; a <= "0000"; c <= "0000";
d <= "0000";
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67
If … then 135
process (s, y)
begin
a <= "0000"; b <= "0000"; c <= "0000";
d <= "0000";
if (s = "00") then a <= y;
elsif (s = "01") then b <= y;
elsif (s = "10") then c <= y;
else d <= y;
end if;
end process;
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If … then 136
process (s, y) process (s, y)
begin begin
if (s = "00") then a <= y; else a <= a <= "0000"; b <= "0000"; c <= "0000";
"0000"; end if; d <= "0000";
if (s = "01") then b <= y; else b <= if (s = "00") then a <= y; end if;
"0000"; end if; if (s = "01") then b <= y; end if;
if (s = "10") then c <= y; else c <= "0000"; if (s = "10") then c <= y; end if;
end if;
if (s = "11") then d <= y; end if;
if (s = "11") then d <= y; else d <=
"0000"; end if; end process;
end process;
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68
Ripple Adder 137
architecture arch_add8 of add8 is
signal carry: std_logic_vector (8 downto 0);
begin
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69
Carry Look Ahead Adder 139
architecture arch_add8 of add8 is carry(1) <= g(0) or (p(0) and carry(0));
signal carry: std_logic_vector(8 downto 0);
signal g, p: std_logic_vector(7 downto 0); carry(2) <= g(1) or (p(1) and g(0)) or
begin (p(1) and p(0) and carry(0));
carry(0) <= cin; cout <= carry(8); carry(3) <= g(2) or (p(2) and g(1)) or
(p(2) and p(1) and g(0)) or
glp: for i in 0 to 7 generate (p(2) and p(1) and p(0) and carry(0));
g(i) <= a(i) and b(i);
p(i) <= a(i) or b(i); 00000..
sum(i) <= a(i) xor b(i) xor carry(i);
end generate; end arch_add8;
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70
Shift Register 141
d7 d0
Source Reg
Shift
Dest Reg
d’7 d’1 ‘0’
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71
Universal Shift Register 143
library ieee;
use ieee.std_logic_1164.all;
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end arch_shift8;
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72
Universal Shift Register 145
-- shift right
process (reset, clk)
when "10" =>
begin
q(7 downto 0) <= rin & q(7 downto 1);
if (reset = '1') then
-- hold
q <= (others => '0');
when others => q <= q;
elsif (clk'event and clk = '1') then
end case;
case sel is
end if;
-- parallel load
end process;
when "00" => q <= pin;
end arch_shift8;
-- shift left
when "01" =>
q(7 downto 0) <= q(6 downto 0) & lin;
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+ +
1
D Q
a (7:0) z (7:0)
1
b(7:0)
0
D Q
0
a (7:0) b(7:0)
loc CK
clk loc CK
AR z (7:0) clk AR
rst
rst
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73
VHDL Code 147
library ieee;
use ieee.std_logic_1164.all; process (rst, clk)
use ieee.std_logic_unsigned.all begin
if (rst = '1') then q <= (others => '0');
entity dt1q2 is elsif (clk'event and clk = '1') then
port (clk, rst, loc: in std_logic; if (loc = '1') then
a, b: in std_logic_vector(7 downto 0); q <= q + a;
z: out std_logic_vector(7 downto 0)); else
end entity; q <= b;
end if;
architecture arch_dt1q2 of dt1q2 is end if;
signal q: std_logic_vector(7 downto 0); end process;
begin end arch_dt1q2;
z <= q;
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74
Block Diagram 149
c (7:0) =
z (7:0)
1 0
D Q
y (7:0)
y(6:0) & d
b CK
AR
a
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signal x: dtype2;
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75
VHDL to Circuit 151
V3
U3 U2 U1 U0
gnlp1: for i in 0 to 3 generate V2
V1
y(i) <= u and (v(i), v(i), v(i), v(i)); V0
end generate;
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end generate; W
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Design 153
• Synchronous 4 bit up/down
counter with parallel load +1
0 1
feature
0
-1 count
dir d q
q
1
• Block schematic din
load
• Behavioral VHDL Code clk clk
AR
rst
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77
FSM Coding 155
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78
FSM Coding 157
• NSL: Process, • OL: Concurrent statements
“case … when” (on present state) with (present state) … select
with nested “if (on inputs)
…then” for next state • NSL+FF: Process
• Flip Flops: Process, if (rst) ... then
“if (rst) ... then” elsif (clk’event and clk = ‘1’) then
elsif (clk’event and clk = ‘1’) case … when” (on present state)
then
• OL: Process
“case … when” (present state)
for outputs.
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79
Sequence Detector 159
• A simple sequence Detector. Sequence
101. Data shift clock used as FSM clock.
Overlapping detector. Moore Machine
reset din’
a detect = 0
clk din
din
detect din’ b detect = 0
Tx din Det din’
din
c detect = 0
din’ din
d detect = 1
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80
Sequence Detector: VHDL Code 161
when d => flfl: process (clk, reset)
if din = '0' then nx_state <= c; begin
else nx_state <= b; if (reset = '1') then pr_state <= a;
end if; elsif (clk'event and clk = '1') then
when others => pr_state <= nx_state;
nx_state <= a; end if;
end case; end process flfl;
end process nsl;
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Sequence Detector: VHDL Code 163
• -- NSL + OL process; FF process; comb: process (pr_state, din)
library ieee; begin
case pr_state is
use ieee.std_logic_1164.all;
when a => detect <= ‘0’;
if din = '1' then nx_state <= b;
entity sqdet1 is
else nx_state <= a;
port (din, clk, reset: in std_logic; end if;
detect: out std_logic); when b => detect <= ‘0’;
end sqdet1; if din = '0' then nx_state <= c;
else nx_state <= b;
architecture sqd1 of sqdet1 is end if;
type statetype is (a, b, c, d); when c => detect <= ‘0’;
signal pr_state, nx_state: statetype; if din = '1' then nx_state <= d;
begin else nx_state <= a;
end if;
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82
Sequence Detector - Mealy 165
• A simple sequence Detector. Sequence comb: process (pr_state, din)
101. Data shift clock used as FSM clock. begin
Overlapping detector. Mealy machine case pr_state is
when a => detect <= ‘0’;
reset din’
if din = '1' then nx_state <= b;
else nx_state <= a; end if;
a detect = 0 when b => detect <= ‘0’;
din
din if din = '0' then nx_state <= c;
din’ b detect = 0 else nx_state <= b; end if;
din’ din when c => detect <= din;
c detect = din if din = '1' then nx_state <= b;
else nx_state <= a; end if;
when others => detect <= ‘0’;
-- NSL + OL single process nx_state <= a;
end case;
end process comb;
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Synchronous Reset 167
-- Synchronous reset when NSL + OL is • State encoding
-- coded in single process
sequential, gray, one-hot-one,
-- Avoid implied latches on outputs
one-hot-zero
comb: process (reset, pr_state, din)
begin
case pr_state is
------
end case;
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Test Bench 169
• Interactive simulation • Test bench
• Design steps verification – Input test vectors could be stored
in a file
• Design Iterations – Output test vectors observed as
waveform or could be stored in a
file.
– Output could be checked against
the expected response stored.
– Automation, Documentation
– Same test bench could be used in
different design steps and in
design iterations.
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Test bench Signal Assignment 171
library ieee; use ieee.std_logic_1164.all; a <=
“0000”, -- a = b
entity comp_tb is “1111” after 100 ns, -- a > b
end comp_tb; “1110” after 200 ns, -- a < b
“1110” after 300 ns, -- a > b
architecture arch_comp_tb of comp_tb is “1010” after 400 ns, -- a < b
component comp4 “1111” after 500 ns; -- a = b
port (a, b: in std_logic_vector(3 downto 0); b <= “0000”, -- a = b
agtb, aeqb, altb: out std_logic); “1110” after 100 ns, -- a > b
end component; “1111” after 200 ns, -- a < b
signal a, b: std_logic_vector(3 downto 0); “1100” after 300 ns, -- a > b
signal agtb, aeqb, altb: std_logic; “1100” after 400 ns, -- a < b
begin “1111” after 500 ns; -- a = b
a1: comp4 port map (a, b, agtb, aeqb, altb); end arch_comp_tb;
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Test bench TV’s in Array 173
• Compile the design in to library – Check Process:
(normally work library).
• Declare a variable of type record
• Create test bench code with empty
Loop
entity.
• Declare the top level component of the • Read the array element to the
design. record variable
• Declare the signals of type of the top • Apply the stimulus to the input
level component. ports,
• Declare a record with port signals of • Verify the actual outputs match
top-level component. the expected output.
• Declare an array of this record. • Compile the test bench and run simulation.
• Initialize the array with the input test • Check the Messages for error; up on error
vectors and expected outputs observe debug messages and/or the
waveform
• Instantiate the component in the test
bench code.
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Test bench TV’s in Array 175
library ieee; type tblk is record
use ieee.std_logic_1164.all; rst: std_logic; clk: std_logic;
q: std_logic_vector(3 downto 0);
entity countf_tb is end record;
type testv is array (natural range <>) of tblk;
end countf_tb;
constant tv: testv :=
architecture arch_countf_tb of countf_tb is (('1', '0', "0000"), ('1', '0', "0000"),
component count4 ('0', '0', "0000"), ('0', '1', "0001"),
port (rst, clk: in std_logic; ('0', '0', "0001"), ('0', '1', "0010"),
q: out std_logic_vector(3 downto 0)); ('0', '0', "0010"), ('0', '1', "0011"),
end component; ('0', '0', "0011"), ('0', '1', "0100"),
signal clk, rst: std_logic; ('0', '0', "0100"), ('0', '1', "0101"),
signal q: std_logic_vector(3 downto 0); ('0', '0', "0101"), ('0', '1', "0110"),
('0', '0', "0110"), ('0', '1', "0111"));
begin
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uut: count4 port map (rst => rst, assert q = vtv.q report “Counter output is not
clk => clk, q => q); what expected” severity note;
test: process end loop;
variable vtv: tblk; assert false report “Test over” severity note;
begin wait;
for i in tv'range loop end process;
vtv := tv(i); end arch_countf_tb;
rst <= vtv.rst;
clk <= vtv.clk;
wait for 20 ns;
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Test bench: Timing Simulation 177
D Q
ts: Setup time: Minimum time input
must be valid before the active clock
CLK
edge
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• Setting up input
• Verifying the output
tclk
Input
tclk
ts
CLK tco
Output
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Test bench: Timing Simulation 179
• Clock Generation • Checking outputs
– Period, Initial offset, Duty cycle – Give a delay for the full run after
• Asynchronous Reset applying inputs and add ts + tco
– Remove tRR time before clock edge – Or if there is a data valid signal
detect it
– Example uses ts instead of tRR
• Applying Inputs Note: Period, setup time, and tco should
– Apply ts time before active clock be noted from the Static Timing Analysis
edge for test bench, and is with respect to
– Detect the clock edge explicitly or corresponding input/output pin/pad.
implicitly (e.g. add clock period –
setup)
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Test bench: Timing Simulation 181
library ieee; use ieee.std_logic_1164.all;
Divider use ieee.std_logic_unsigned.all;
entity lex9_tb is
end lex9_tb;
clk
rst dv architecture arch_lex9_tb of lex9_tb is
component nrdiv8
start
Divider port (
divdi(7:0) quoto(7:0) clk, rst, start: in std_logic;
dv: out std_logic;
divsi(7:0) remdo(8:0) divdi, divsi: in std_logic_vector (7 downto 0);
remdo: out std_logic_vector (8 downto 0);
quoto: out std_logic_vector (7 downto 0));
end component;
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Test bench: Timing Simulation 183
uut: nrdiv8 port map test: process
(clk => clk, rst => rst, start => start, variable vtv: tblk;
begin
dv => dv, divsi => divsi, divdi => divdi, wait for (period - (period * duty_cycle) -
remdo => remdo, quoto => quoto); setup);
clock: process -- clock process for clk rst <= '0';
begin wait for period;
wait for offset; for i in tv'range loop
clock_loop : loop vtv := tv(i);
clk <= '0'; start <= '1';
wait for (period - (period * duty_cycle)); divdi <= vtv.divdi;
clk <= '1'; wait for (period * duty_cycle); divsi <= vtv.divsi;
wait for period;
end loop clock_loop; start <= '0';
end process; wait for (onerun + setup + tco);
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Test bench: Timing Simulation 185
• You may do this at the end of
iteration to check the output
OR
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Test bench: Algorithmic 187
test: process
signal a, b: std_logic_vector(3 downto 0); begin
signal s: std_logic_vector(4 downto 0); for i in 0 to width-1 loop
constant width: integer := 16; a <= conv_std_logic_vector(i, 4);
constant delay: time := 12 ns; for j in 0 to width-1 loop
begin b <= conv_std_logic_vector(j, 4);
wait for delay;
-- component Instantiation assert s = conv_std_logic_vector(i+j, 5)
uut: adder4 port map (a => a, b => b, report "Sum is not what is expected"
s => s); severity note;
end loop;
end loop;
assert false report "Test Over"
severity note;
wait;
end process;
end arch_addtb1;
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