Heterogeneous ISA Chip multiprocessor

Name: Rashmi
Roll no.: 16D070057

Overview:​Heterogeneous core architecture is well known, where ISAs

were kept same and witnessed performance enhancement and energy
saving wrt homogeneous core architecture. This paper has thrown some
light on exploiting the heterogeneity in ISAs as well in addition to hetero
core. In this using 3 different ISA,where each is specialised in some aspect
,heterogeneity is exploited.
1. Energy-​efficient​ Thumb ISA
2. High performance​ x86-​-64 ISA
3. simple and traditionally​-​-RISC Alpha ISA
There is a wide diversity in these ISAs in terms of Code density,instruction
complexity, register pressure, predication support, floating-point arithmetic
vs emulation and SIMD processing .
Here I am listing few:
Thumb x86 Alpha
Code density high medium low

Dynamic more medium less

instruction count

register high medium low

pressure

Floating-​point Done in software

opera;ons in
Execution:
● Depending on the phase of the program the ISAs are switched
according to ISA affinity
● When power consumption is critical, power efficient ISA is used.
● Similarly, when performance is critical, high performance ISA is used
● As code is different for different ISAs, code translation is needed.
This should take place at equivalence point.
● The ISA migration takes place in two steps, namely Binary
Translation and Program State Transformation

Area of improvement:
● ISA suitable for each phase consisting of about 1 million instruction
window has to be explored with experimenting with different
workloads and their performance with different ISA.
● Minimizing the time of code migration.
● Choosing the suitable set of cores with different ISA among the pool
of possibilities(10^24)

Drawbacks:
● As discussed in the class, the other paper had explored that there is
no effect of ISA on performance. If we consider different ISAs with
same micro-architecture parameters, we may be able to say that
exploiting ISA heterogeneity might not help in performance
betterment.