CH 9 - Op-Amp - Part I PDF

Operational Amplifier [Op-Amp (OA)]
• Gem of analog circuits: extremely versatile

and has multitude of applications
• Two inputs, one output, and biased with
dual symmetric power supplies
• Extremely large open-loop gain and input
resistance, and very small output resistance
• Has very high bandwidth too  prone to
oscillations  needs to be compensated 
reduces available bandwidth to ~5-10 Hz
Aloke Dutta/EE/IIT Kanpur 1
• Most important property:
– Rejects signals common to both inputs
– Denoted by a parameter known as the
Common-Mode Rejection Ratio (CMRR)
– Has very high CMRR  suppresses noise
• Limitations/Anomalies:
– Offset Voltage and Offset Current
– Saturation Voltages
– Slew Rate
– Minimum Allowed Supply Voltage
Op-Amp Symbol & Schematic:
V0 = AVOL(V1 – V2)
VS+ Non-Inverting
Terminal
i1 +
V1
+
V1 V0 R0 V0
+
Ri Vi AvOLVi
–
V2
–
V2
i2 –
Inverting
VS– Terminal
Symbol
Schematic
V1, V2: Input Voltage, V0: Output Voltage, i1, i2: Input Current
VS+, VS–: Dual Symmetric Power Supplies, Ri: Input Resistance
R0: Output Resistance, AVOL: Open-Loop Gain

* OAs are essentially voltage amplifiers
 Note the VCVS configuration at the output
* Note that the difference signal Vi   V1  V2  is a
floating signal (i.e., a signal that is measured between
two points, none of which may be ground )
 However, the output V0 is always measured with
respect to ground
* Typical values: A VOL  105 , R i  1 MΩ, R 0  100 Ω,
VS and VS = ± 3 V (minimum) - ± 15 V, CMRR 
80 dB (104 ), Uncompensated Bandwidth  1 MHz,
Compensated Bandwidth  10 Hz
* Basically a voltage amplifier (amplifies ac as
well as DC, subject to power supply limits)
* For V1 > V2 , V0 is positive  terminal for V1 is
termed as non-inverting
* For V2 > V1 , V0 is negative  terminal for V2 is
termed as inverting
* Ri is extremely large  for all practical purposes,
the input currents to the op-amp can be neglected
 i1 = i 2 = 0
* Famous OA paradox: The input terminals are
open and short at the same time
Brief Background History:
* In 1965, Bob Widlar of Fairchild Semiconductors
(bought by ON Semiconductors in 2016) designed
the first monolithic (single substrate) OA
* Named it μA 709 (A was a prefix used for
Fairchild products)
* A number of improvements were carried out almost
immediately, and the next generation OA was
marketed as μA 741
* Became a huge hit, and 741 became synonymous with
OAs (uses bipolar technology )
Applications:
* Open-loop: No input-output connection, i.e., no
feedback
* Closed - loop:
 Negative (degenerative ) feedback: the output fed
back to the input in such a way that it opposes the
very cause producing it  stable system
 Positive (regenerative ) feedback: the output fed
back to the input in such a way that it adds to the
input and produces more output and the process
repeats  highly unstable system
Negative Feedback: V
+
V0
* Output fed back to the inverting
–
terminal of the OA through the FN V

Feedback
* V0 = A v  V   V   Network (FN)
* If due to some reason, V0 increases, then V  would

increase, which would pull V0 down
* Thus, the effect is opposing the cause that produced it
 Negative Feedback
 Stable System: All disturbances die down
automatically
Positive Feedback: Feedback
Network (FN)
* Output fed back to the non-inverting +
V
terminal of the OA through the FN V0
* V0 = A v  V   V   V
–
* If due to some reason, V0 increases, then V  would

increase, which would increase V0 further, and the
process would repeat
* Thus, the effect is aiding the cause that produced it
 Positive Feedback
 Highly Unstable System: All disturbances build up,
eventually leading to oscillations at the output
Open-Loop:
* Comparator
* Zero-Crossing Detector (Square-Wave Generator )
Comparator:
V0
VSAT+
Vi V0 Vi
V0 0
VR Vi
VR: Reference Voltage VSAT–

VTC for VR = 0
Compares Vi with VR
and produces output Diagram not to scale
* Generally, the power supply connections to the
OA are not shown for brevity, though they are
of course very much there
* We will follow this practice hence onward
* With VR  0, and due to very large A VOL :
 For positive Vi , V0 saturates at VSAT (positive
saturation voltage, which is very close to the
positive power supply )
 For negative Vi , V0 saturates at VSAT (negative
saturation voltage, which is very close to the
negative power supply )
* The finite slope of the VTC is caused by finite AVOL
* If AVOL were infinite, then the change of V0 would
have been instantaneous (i.e., Vi  0)
* Estimate of ΔVi :
 Let VSAT  15 V and A VOL  105 :

 Vi  VSAT  VSAT  A VOL   30 V  105
= 0.3 mV = 300 V (really small!)
* If VR  0, then the change would take place around VR
 Known as Comparator with Threshold
* Can be used in digital circuits too
 Known as Digital Comparator
Zero-Crossing Detector (Square - Wave Generator):
Vi, V0 Vi, V0
VSAT+ VSAT+
V0
T ON V0
VM
VR
2T  
0 T
t
0   t
Vi (rad)
–VM
T OFF
Vi
VSAT– VSAT–
VR = 0 VR > 0
* Simple comparator with sinusoidal input (Vi ) and

with a reference voltage VR
* Output changes state when input crosses zero (for
VR = 0) or crosses VR  VR  0 
* Duty Cycle () of a square wave:  = TON T ,
where T  = TON  TOFF  is the Time Period
* Note:
 For VR = 0,  = 50%
 For positive VR ,  < 50%
 For negative VR ,  > 50%
* By adjusting the sign and magnitude of VR , we
can achieve any value of 
* Note that amplitude of Vi is immaterial
Example: Vi = VM sin  t  , with VM  5 V, and
VR  1 V. Find .
 VR 
1
First, we find 1  sin    11.54, and
 VM 
2  180  1  168.46
Thus, the angle over which the output is high
=  2  1   156.92
156.92
 Duty Cycle  =  0.436 or 43.6%
360
Exercise: Evaluate  for VR =  1 V

Anomaly : Offset Voltage and Current:
* The previous two analyses assume that when
Vi = 0, V0 = 0, i.e., the VTC passes through
origin
* This is true for ideal OAs
* However, real OAs have an inherently built -in
voltage difference between its two inputs, which
would always make the output saturated , even
with zero input

* Happens due to component mismatch in the
OA circuit
* Known as the Offset Voltage (VOS )
* Typical values of VOS ~ 1-10 mV
* Also, for a real OA, the input currents i1 and
i 2 are not zero, but finite and unequal
 The difference between these two currents
is known as the Offset Current (IOS )
* Typical values of IOS ~ 10 nA or so

• Closed-Loop: Negative Feedback:
– Plethora of applications
• Inverting and Non-Inverting Amplifiers
• Summing Amplifier
• Voltage Follower
• Differential or Difference Amplifier (DA)
• Instrumentation Amplifier
• Level Shifter
• Active Filter (Low-Pass, High-Pass, Band-Pass)
• Integrator and Differentiator
• Logarithmic and Exponential Amplifier

Inverting Amplifier:
* R 2 provides negative feedback i2
R2
 Note that it is connected between Vi R1 –
V
V0
the output and the inverting ( ) i1
V
+
terminal  negative feedback

* V  and V  are the voltages at the non-inverting and
inverting terminals of the op-amp, respectively
 Note that V   0, since that terminal is grounded
* One very important assumption in op-amp circuit
analysis: R i    input current to the op-amp = 0
 i1  i 2   Vi  V   R1   V   V0  R 2
* Also, V0  A vOL  V   V    A vOL V 
* Thus, the closed -loop gain (A vCL ) can be expressed as:
1
V0  R1 1  R1  
A vCL     1   (show )
Vi closed-loop  R 2 A vOL  R 2  
* The negative sign in front implies that the output
voltage is exactly out -of -phase with the input voltage
(i.e., they are 180° apart )  Inverting Amplifier
* Note: If A vOL  , then A vCL   R 2 R1
 An extremely simple expression results

* Note that the closed -loop gain is just equal to the
resistor ratio (feedback resistor/input resistor)
* Caution: For this simplification to hold, A vOL should
be at least 100 times R 2 R 1 (will produce 1% error )
* Lower values of A vOL will correspondingly produce
more error in the result
* Thus, blindly using the simplified result without any
regard to A vOL is perilous!
* Note also that the resistance seen by the input Vi is
simply equal to R1 (to be discussed next)

Concept of Virtual Ground & Summing Point Constraint:
* Valid only when the OA is under negative feedback
* Due to the large open-loop gain (A vOL ) of the OA, the
difference between the voltages at the inverting and
non-inverting terminals is vanishingly small
* Thus, if the non-inverting terminal is grounded (i.e.,
Real Ground ), then the inverting terminal is also assumed
to be at ground potential , even though actually it may
not be so
 Known as Virtual Ground (to distinguish it from
actual ground)
* The assumption that V + = V  as well as i1 = i2 = 0
is known as the Summing Point Constraint
* These two assumptions make the analysis of OA
circuits absolutely trivial
* Extending this argument, we can say that for OAs
under negative feedback, the voltages at the inverting
and non-inverting terminals always track each other,
such that their difference is zero (almost!)
* Caution: These assumptions are applicable only for
OAs under negative feedback, never apply these
assumptions when the OA is under positive feedback
Important Assumptions for OA Circuit Analysis:
* R i    Zero input currents to the OA
* A vOL    Summing Point Constraint can be
applied at the input terminals under negative feedback
* R 0  0  The output behaves like an ideal voltage
source
* The OA can source and sink any current, up to the
maximum permissible limit , at its output
* Be very careful while applying KCL at the output
terminal of an OA, since the OA may be sourcing
or sinking current (which would have opposite signs)
Limitations : Saturation Voltages :
Vi (V) V0 (V)
1 10
0 0
t t
R2 = 10 k
–1 –10
V0 (V) clipped output
15
R1 = 1 k
VSAT+ = 15 V
VSAT– = –15 V
0
t
R2 > 15 k
–15
clipped output

Limitations : Bandwidth (Unity -Gain Cutoff) :
* OAs are compensated for stability with regard
to unwanted oscillations
* Compensation creates a pole in the frequency
response characteristic, typically at about 5 -10 Hz
* After that, the gain rolls off at  20 dB /decade
* The frequency at which the magnitude of this gain
becomes unity (i.e., 0 dB ) is known as the unity -gain
cutoff frequency (f T )
* Relation: A vOL  f OL  A vCL  f CL  f T , where f OL and
f CL are the open-loop and closed -loop cutoff frequencies
Av (dB)
AvOL (~ 100 dB)

–20 dB/decade
AvCL
0
fOL fCL fT
f
(~ 5-10 Hz) (~ 1 MHz)
(log scale)
As AvCL, fCL, and vice-versa

Limitations : Slew Rate :
* Slew Rate (SR) is the maxuimum possible rate of
change of the output with respect to time (in V/sec),
which is constant for a given OA, and is typically
about 0.5 -2 V /μsec
* Given by: SR  M VSAT  0 V0  0 A Vi
where M : Full -power bandwidth: Maximum
possible bandwidth when the output is
swinging between ± VSAT
0 : Bandwidth when the output is swinging
between ± V0 (< ± VSAT )
Example :
Let R1  1 k, R 2  10 k, VSAT  15 V, and SR =
1 V/sec. Find 0 for Vi  10 mV, 100 mV, and 1 V.
A  10,  0 
SR

1 V μsec 
A Vi 10  Vi
Thus, for Vi = 10 mV, 0  10 Mrad/sec
= 100 mV, = 1 Mrad/sec
= 1 V, = 100 krad/sec
Note: 0 is an inverse function of both gain  A 
and the input signal amplitude (Vi )
Thus, as A and Vi , 0 
An Interesting Scenario :
The amplitude and frequency of the sinusoidal
input signal is such that the output becomes
both saturation voltage and slew rate limited
V0
VSAT+
Sinusoidal
slope = SR
Input
0
t
VSAT–

Dramatic Effect of SR Limitation :
Vi, V0 Vi, V0
Vi
Vi, V0
t t
V0
Frequency = f1 (no SR limitation)

Frequency = f2 (> f1) (moderate SR limitation)
Vi, V0
Vi
Under unity feedback

configuration ((to be
discussed later) t
V0
Frequency = f3 (> f2) (severe SR limitation)

Limitation : Output Current Source /Sink Capability :
* OAs have a limit on the R2
10 k
maximum current (i 0,max ) R1 i2
that they can source or sink Vi 1 k
i0
V0
i1
* This puts a lower limit on the
RL iL
value of the load resistance 50 
that it can drive

* Let Vi  1 V  V0  10 V (without R L )
* With RL : KCL at the output (note that V0 is positive )
V0 V0
  i 0  max   (OA has to source current )
R2 RL
* For i 0,max  25 mA, V0  1.24 V (note that the
nominal value is 10 V )
* This severe attenuation in the output voltage is
caused by the limited current drive capability
of the OA coupled with the small value of R L
* Thus, there is a minimum value of R L , beyond
which the output will start to attenuate  find
this minimum value of R L for this example (Ex.)
* Caution: While using KCL at the output node of an
OA: Always check if the current being sourced /
sunk by the OA is below i 0,max
Summing Amplifier (or simply Summer) :
RF
* i1  i 2  i3  i f (no input current
if
to the OA) V1 R1
V0
V1 V2 V3 V0 i1
    V2 R2
R1 R 2 R 3 RF
(virtual ground at the i2
V3 R3
inverting terminal )
i3
 RF RF RF 
 V0    V1  V2  V3 
 R1 R2 R3 
n
 RF 
   Vi 
i 1  R i 
* Note that the circuit produces an weighted sum of
the input voltages, with the weighting factor given
by R F R i for the i th input
* Ex: If R1  1 k, R 2  2 k, R 3  5 k, and
R F  10 k, then V0   10V1  5V2  2V3 
* Immensely popular in earlier days of analog
computers
* With the advent of digital computers, has lost favor
* All the limitations discussed for inverting amplifier
hold for all OA circuits to be discussed, including
this one
Non-Inverting Amplifier : R2
* Note that the feedback is still R1

i2
negative (output fed back to

i1
V0
the inverting terminal of the OA) Vi
* Input Vi applied to the non-inverting terminal

* Applying summing point constraint:
Vi Vi  V0 V0 R2
i1  i 2     A vCL   1
R1 R2 Vi R1
* Thus, input and output are in phase, and the magnitude
of the voltage gain  1  Non-Inverting Amplifier
* The input signal source Vi is not loaded at all by the
OA, since the input resistance is infinite
Voltage Follower :
* An interesting application of the non-inverting amplifier
* Put R 2 = 0 (short -circuit ), i.e., connect the output
directly to the inverting terminal of the OA
* Then, AvCL = 1, irrespective of the value of R1
* Thus, R1 can as well be removed (open-circuit )
* Resulting circuit is known as voltage
follower , since the output follows the
V0
input with unity gain and no phase shift Vi
* This configuration is also known as buffer ,

with Ri  , R0  0, and Av = 1
* Frequently used for isolation between stages
* Another name for this configuration is unity
feedback configuration, since the entire output
is fed back to the input
* Also, since the closed -loop gain is unity, the
bandwidth of the circuit is equal to fT (maximum)
* Used also for impedance matching, when a driver
circuit having high output resistance drives a load
having low input resistance

Differential (or Difference) Amplifier (DA) :
R2
* Extremely useful circuit:
i2
Amplifies the difference V1
R1
– V0
i1 V
between the two input V
+
V2
signals, while rejecting R3
R4
signals common to both inputs
 An excellent noise suppressor
* To analyze this circuit, we apply summing point
constraint , which yields V  = V  , and input
current to the OA = 0
* Note: The circuit has only negative feedback
V1  V  V   V0  R4
* i1  i 2   and V  V2
R1 R2 R4  R3
R2  R2   R 4 R3 
* Thus, V0   V1  1    V2
R1  R1  1  R 4 R 3 
* Exercise: Show that the same result could also have
been obtained by applying Superposition Principle
* An interesting outcome: Make R 2 R1  R 4 R 3
R2
 V0   V2  V1   (1)
R1
 A perfect differential output , with no common-
mode signal present there!  CMRR  
* For a DA, the output voltage V0 is expressed as:
V0 = A dm Vid + A cm Vic
where
Vid = differential -mode input voltage = V2  V1
Vic = common-mode input voltage =  V1  V2  2
A dm = differential -mode gain
A cm = common-mode gain
Common-Mode Rejection Ratio:
CMRR  20 log10 A dm A cm (expressed in dB )
* Compare with (1): A dm  R 2 R1 , A cm = 0, and
CMRR  
* It is obvious that if R 2 R1  R 4 R 3 , then A cm  0,
and would result in a finite CMRR
* Exercise: Find A dm , A cm , and CMRR, if R 2 R1 
10 and R 4 R 3 = 11
* Immensely useful circuit, particularly for telemetry
applications
* Differential Amplifier is the heart of another
extremely useful block, namely Instrumentation
Amplifier

Instrumentation Amplifier :
* Bread-and-Butter Circuit for Instrumentation Engineers
* Used for field telemetry applications, where the points
of measurements and processings are far away
 The signal may get thoroughly corrupted by noise
during transmission, and it becomes extremely
difficult to extract using conventional circuits
* Requirements of such a circuit:
 Should have extremely high input resistance, so
that the measuring instrument does not load the signal
 Should have perfect impedance matching
 Should have extremely high Adm and very small
Acm (ideally zero)
 An extremely large CMRR is a necessity to
suppress noise
* Simplest circuit solution:
 Precede a DA (having high Adm and CMRR) by
a buffer (having high Ri providing perfect
impedance matching)
* Resulted in the Instrumentation Amplifier

V1 Vy R RF
1
R2
R1 3 V0
R2
2
V2 Vx R
RF
Instrumentation Amplifier

* Note: OAs 1 and 2 are buffers, while OA 3 is a DA
* Both 1 and 2 have negative feedback , thus we can
apply the summing point constraint for both of them
* Thus, voltages at nodes A and B are equal to the
input voltages V1 and V2 , respectively
* Also, since OAs 1 and 2 do not draw any input current,
 the current through the branch R 2 -R 1 -R 2 is the same
* Thus, Vx and Vy can be immediately expressed in terms
of V1 and V2

* Note that the input resistance seen by the inputs
V1 and V2 is infinitely large, thus the circuit does
not cause any loading of the input signal
* OA3 being a simple DA, the output voltage V0 can
be easily expressed as:
RF R F  2R 2 
V0 
R
 Vx  Vy  
R 
1    V2  V1 
R1 
where Vx and Vy have been expressed in terms of
V1 and V2 (Exercise: Prove this expression for V0 )

* Note that the voltage gain of the first stage (i.e.,
the buffer stage) is 1  2R 2 R1 
* Generally, R1 is kept variable, so that the gain
of the circuit can be adjusted
 R1 is known as the gain resistor
* Extremely useful circuit, and instrumentation
engineers can't live without it!
* Note that resistors have tolerance, thus, even
though the ideal expression for V0 indicates
infinite CMRR, in actual situations, the CMRR
would be finite, but large
Level Shifter:
R2
* Adds DC offset to a time -varying
Vi R1
signal V0
* Circuit resembles an inverting

VR
amplifier , with a reference voltage
VR applied at the non-inverting terminal
* Negative feedback present in the circuit can be easily
identified  summing point constraint can be
applied  the voltage at the inverting terminal is
also VR

R2  R2 
* Thus, V0   Vi  1   VR (by superposition)
R1  R1 
* The magnitude of the DC offset , amounting to
1  R 2 R1  VR , can be easily identified from
the above expression
* Note also that the sign of the DC offset can be
changed by changing the sign of VR
* For a specific requirement of the DC offset ,
either the resistor ratio  R 2 R1  or the reference
voltage  VR  or both can be changed

For Continuously Varying VR :
* Uses two fixed value resistors (R) and a
+VCC
potentiometer  R   R
* Biased using dual power supply  VCC :
R'
the same supply that powers the OA +
VR
* The range of VR (Exercise: Prove it): R –
VCC R  VCC R  –V CC
  VR  
2R  R  2R  R 
* For higher resolution, use potentiometer with higher
number of turns  CROs use this technique to add
DC offset to a signal
Active Filters:
* We have already seen passive filters using resistors,
inductors, and capacitors
* Passive filters are incapable of producing voltage
gain (the gain is always  1)
* Filters can also be constructed using OAs, which
can provide for voltage gain
 Known as Active Filters
 Can design LPF , HPF , and BPF using OAs

LPF :
* First note that the OA is under
C
negative feedback ,  virtual
Vi R1 R2
ground concept can be applied V0
* Thus, the circuit is simply an

inverting amplifier , with a
capacitor C in parallel with a resistor R 2 in the
feedback branch
* Resistor R2 is necessary,  without it, the OA
won't have any DC feedback path, and will go
under open-loop, with output saturating to ±VSAT
* Impedance of parallel combination of R 2 and C:
 1  R2
Z  R2   
 jC  1  jR 2 C
V0 Z R 2 R1 K
* Thus,   
Vi R1 1  jR 2C 1  j c
 K    R 2 R1  is the low -frequency (or pass -band )
gain, with the negative sign implying 180° phase
shift between input and output
 c   1  R 2 C   is the upper cutoff frequency
* From the transfer function, LPF behavior is obvious
2: Upper Zero
Crossing Frequency phase
|V0/Vi| (dB)
(degrees)
slope =
20 log 10|K| 180 –45/decade
slope =
–20 dB/decade 135
pass-band 90
0 0
c 2  c c c 
(log scale) (log scale)
Asymptotic Gain Plot Asymptotic Phase Plot
* Note: Gain controlled by R1 and R 2 , while cutoff

frequency controlled by C  tremendous flexibility
* Also known as a first -order filter , since the transfer
function has only a single pole
* Note that the transfer function has a single pole at c
 The gain stays constant at 20log10 K till c ,
and then drops @ 20 dB/decade
* For very low frequency    0  , the phase angle
of the output is 180  or, equivalently,  180 
(due to the presence of the negative sign in front
of the transfer function) till 0.1c , and then starts
to drop @45/decade till 10c , resulting in a
final phase of 90 (or, equivalently,  270) as

HPF :
* Only difference from LPF is that Vi R1
C
R2
V0
C is taken off from the feedback
branch and put in the input branch
* Impedance of the series combination of R1 and C:
1 1  jR1C
Z1  R1  
jC jC
V0 R2 jR 2 C j 1
* Thus,   
Vi Z1 1  jR1C 1  j c
1   1/  R 2 C   is the lower zero crossing frequency
c   1/  R1C   is the lower cutoff frequency
* Note: As   0, V0 Vi  0; and as   ,
V0 Vi  c 1  R 2 R1 (constant)
 HPF behavior established
* Pass-Band Gain = c 1  R 2 R1
 For large pass-band gain, R 2 R1 should be large
 R 2 should be much larger than R1
 ω1  ωc
* 1 is known as lower zero crossing frequency, since at
this frequency V0 Vi = 1 (0 dB), and then increases
@ 20 dB/decade till c , after which it becomes constant

phase
|V0/Vi| (dB)
(degrees)
slope =
20 log 10|R 2/R1| 270 –45/decade
slope = 225
+20 dB/decade
pass-band 180
0 90
 c 
(log scale)
0
c c c 
(log scale)
* Note: As   0, phase = 180 (due to the negative sign

in front of the transfer function) + 90 (constant phase
contributed by 1 ) = 270
BPF :
* Combination of LPF and HPF: R1 -C 1 creates lower cutoff
(for HPF ), and R2 -C 2 creates upper cutoff (for LPF )
* Impedance of series combination
of R1 and C1:
C2
1 1  jR1C1
Z1  R1   C1
jC1 jC1
Vi R1 R2
V0
* Impedance of parallel combination

of R 2 and C2 :
 1  R2
Z2  R 2   
 jC2  1  jR 2 C2
V0 Z2 jR 2 C1
* Thus,  
Vi Z1 1  jR1C1 1  jR 2C2 
j 1

1  j L 1  j H 
1   1/  R 2 C1   is the lower zero crossing frequency
L   1/  R1C1   is the lower cutoff frequency (for HPF)
H   1/  R 2 C2   is the upper cutoff frequency (for LPF)
* Pass-Band = H  L
* Pass -Band Gain = R 2 R1 , thus for large pass-band gain ,
R 2  R1  C2  C1 (  H > L and 1  L )
phase (degrees)
270
2: Upper Zero slope =
|V0/Vi| (dB) Crossing Frequency –45°/decade
225
20 log 10(R 2/R 1)
180
pass-band
135
(bandwidth)
90
slope =
+20 dB/decade
45
slope =
–20 dB/decade 0
L H 
0 (log scale)
 L H   L H
(log scale) L H
* In plotting the phase, it is assumed that H  100L

* Note that the phase ranges between ± 90° ,
characteristic of a BPF
Design Problem: Pass-band gain = 40 dB, lower cutoff
frequency = 200 Hz, bandwidth = 800 Hz.
Choose R 1 = 1 k, pass-band gain = 40 dB = 100
 R 2 = 100 k
f L  200 Hz = 1  2R1C1   C1  0.8 F
Bandwidth = 800 Hz  f H  f L  BW  1 kHz
 1  2R 2 C2   C2  1.6 nF (Note:  C1 )
f1 = 2 decades below f L  2 Hz
f 2  2 decades above f H = 100 kHz
Check: f1  1  2R 2 C1   2 Hz (checked!)

Integrator: C
* Time -domain application: output an

Vi R i2
integrated version of input V0
* Looks exactly similar to an LPF : note i1
that the function performed by an LPF

in frequency - domain is exactly the same as that done
by an integrator in time- domain
* Identifying negative feedback and applying virtual
ground concept:
Vi dV0
i1  i 2   C
R dt
t
1 1
 V0    Vi dt    Vi dt  V0  0 
RC τ0
  (= RC) is the time constant of integration
 V0 (0) is the initial value of V0 at t = 0
* Thus, if Vi is a square pulse, V0 will be triangular ;
and for triangular Vi , V0 will be parabolic, etc.
* Practical integrators would have a resistor R 2
shunting the capacitor C in the feedback path to
prevent any open-loop condition of the OA, which
would saturate the output at  VSAT

* Caution: The time constant R 2 C created by this
additional resistor should in no way affect the
integration time constant  (= RC)
* This makes the design of a practical integrator
little tricky
* Also, the capacitor needs to be discharged
periodically to prevent any undesirable
accumulation of charges in it
* Used sparingly

Differentiator: R
* Another time -domain application: C i2

Vi
output a differentiated version of input V0
* Looks exactly similar to an HPF : note i1
that the function performed by an HPF

in frequency - domain is exactly the same as that done
by a differentiator in time- domain
* Identifying negative feedback and applying virtual
ground concept:
dVi V0
i1  i 2  C 
dt R
dVi dVi
 V0  RC  τ
dt dt
 (= RC) is the time constant of differentiation
* Thus, a triangular input will produce a square wave
output, etc.
* This circuit also is rarely used since it tends to
am plify the noise present at the input (note that
the derivative of a noise spike can be dangerously
large!)
* Occasionally used for waveshaping

Logarithmic Amplifier: D
* Output logarithmic function of input

Vi R i2
* Non-linear application due to the V0
presence of a non-linear element i1
(diode D) in the feedback path

* This circuit is a little complicated, since the feedback
path gets broken when the diode becomes reverse
biased and the output saturates to VSAT
* However, when the diode is forward biased , then the
feedback path is maintained , with the diode voltage
equal to  V0 (due to virtual ground )
* Note that under this condition, negative feedback is
maintained and virtual ground concept can be applied
  V0  
 i 2  IS exp     1
  VT  
IS : Reverse Saturation Current of diode
VT : Thermal Voltage (26 mV at T = 300 K)
Vi   V0  
 i1  i 2   IS exp     1
R   VT  
 Vi  
 V0  VT ln    1  (1)
 IS R  
Observations:
* For Vi = 0, V0 = 0, i.e., the VTC passes through
origin
* For positive Vi , a current equal to Vi / R will
flow through R, and the same current would flow
through D as well, thus developing an output
voltage V0 , given by (1)
* For Vi  IS R, then the  1 term in (1) can be
neglected, and V0 becomes a true logarithmic
function of Vi

* Note that the maximum output voltage can only
be equal to the negative of diode voltage, which
typically ranges between 0 to about 1 V (for
Si diodes)
* Note that due to the logarithmic dependence of V0
on Vi , a large change in Vi can be compressed to
a small change in V0
* For negative Vi , the diode becomes reverse biased ,
the feedback path gets broken, the OA becomes
open-loop, the inverting terminal acquires a finite
negative voltage, and V0 swings to VSAT +
Exponential Amplifier: R
* Dual of Logarithmic Amplifier D i2

Vi
* Note that the negative feedback V0
path is always maintained through i1
the resistor R (virtual ground applicable )

* Note also that so long as the diode remains reverse
biased , the input signal Vi can't reach the OA
terminal, and V0 would be zero
* Thus, for all negative Vi , V0 = 0
* For positive Vi , the diode becomes forward biased
* Note the limited positive range of Vi
* Thus,
  Vi   V0
i1  i 2  IS exp    1  
  VT   R
which gives:
  Vi  
V0  IS R exp    1
  VT  
* For Vi  4VT , which is about 100 mV at room
temperature, the  1 term can be neglected, and
the output becomes a true exponential function
of the input
* Note that the role of this circuit is exactly opposite
to that of the logarithmic amplifier:
 While the logarithmic amplifier compresses a large
change in the input voltage into a small variation of
the output voltage, the exponential amplifier, on the
other hand, expands a very small range of the input
voltage into a very large range of the output voltage
* Caution: Due to the exponential dependence of V0 on Vi ,
with an increase in Vi , V0 would increase rapidly, and the
output may get saturated at VSAT pretty quickly
 Puts an upper limit on Vi for fidelity in operation

CH 9 - Op-Amp - Part I PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CH 9 - Op-Amp - Part I PDF

Uploaded by

Copyright:

Available Formats

Operational Amplifier [Op-Amp (OA)]

• Gem of analog circuits: extremely versatile

Aloke Dutta/EE/IIT Kanpur 3

terminal of the OA through the FN V

* If due to some reason, V0 increases, then V  would

* If due to some reason, V0 increases, then V  would

VR: Reference Voltage VSAT–

* Simple comparator with sinusoidal input (Vi ) and

Aloke Dutta/EE/IIT Kanpur 15

Aloke Dutta/EE/IIT Kanpur 16

Aloke Dutta/EE/IIT Kanpur 17

Aloke Dutta/EE/IIT Kanpur 18

terminal  negative feedback

Aloke Dutta/EE/IIT Kanpur 20

Aloke Dutta/EE/IIT Kanpur 21

V0 (V) clipped output

Aloke Dutta/EE/IIT Kanpur 25

AvOL (~ 100 dB)

As AvCL, fCL, and vice-versa

Aloke Dutta/EE/IIT Kanpur 27

Aloke Dutta/EE/IIT Kanpur 30

Frequency = f1 (no SR limitation)

Under unity feedback

Frequency = f3 (> f2) (severe SR limitation)

Aloke Dutta/EE/IIT Kanpur 31

that it can drive

* Note that the feedback is still R1

negative (output fed back to

* Input Vi applied to the non-inverting terminal

* This configuration is also known as buffer ,

Aloke Dutta/EE/IIT Kanpur 38

Aloke Dutta/EE/IIT Kanpur 42

Aloke Dutta/EE/IIT Kanpur 44

Aloke Dutta/EE/IIT Kanpur 45

Aloke Dutta/EE/IIT Kanpur 46

Aloke Dutta/EE/IIT Kanpur 47

* Circuit resembles an inverting

Aloke Dutta/EE/IIT Kanpur 49

Aloke Dutta/EE/IIT Kanpur 50

Aloke Dutta/EE/IIT Kanpur 52

* Thus, the circuit is simply an

Asymptotic Gain Plot Asymptotic Phase Plot

* Note: Gain controlled by R1 and R 2 , while cutoff

Aloke Dutta/EE/IIT Kanpur 58

Asymptotic Gain Plot Asymptotic Phase Plot

* Note: As   0, phase = 180 (due to the negative sign

* Impedance of parallel combination

Asymptotic Gain Plot Asymptotic Phase Plot

* In plotting the phase, it is assumed that H  100L

Aloke Dutta/EE/IIT Kanpur 63

* Time -domain application: output an

* Looks exactly similar to an LPF : note i1

that the function performed by an LPF

Aloke Dutta/EE/IIT Kanpur 65

Aloke Dutta/EE/IIT Kanpur 66

* Another time -domain application: C i2

* Looks exactly similar to an HPF : note i1

that the function performed by an HPF

Aloke Dutta/EE/IIT Kanpur 68

* Output logarithmic function of input

presence of a non-linear element i1

(diode D) in the feedback path

Aloke Dutta/EE/IIT Kanpur 71