Output Stages 1

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Requirements:
* Sufficient drive current/power transfer to load
* Low output distortion
* Ideal voltage source: Thevenin equivalent V0 with R 0 → 0
* Voltage gain A v independent of load (ideally unity)
* No phase shift between input and output
* Low Standby Power (while not driving any load)
* High Power Conversion Efficiency 
average power delivered to load

average power drawn from supply
* Should not degrade frequency response
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BJT output stages preferred due to their large current
handling capability
Classification:
Depends on the conduction angle ()
 angle over the complete cycle (360) for which
the output transistors are on
* Class A:  = 360 and max 25% (large standby power)
* Class B:  slightly less than 180 and max 78.5%
* Class AB:  = 180 and max 78.5%
* Class C:  180 - Used in RF applications
We shall be discussing only about Class B and Class AB

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Class B:
Uses complementary set of output transistors
(npn and pnp, NMOS and PMOS)
One takes care of the positive half cycle, while
the other takes care of the negative half cycle
 slightly less than 180 for each
Both ouput devices never on simultaneously
 Zero Standby Power − significant advantage
Also known as Push-Pull stage

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During positive half cycle, the stage pushes current
through load, while during negative half cycle, the
stage pulls current away from the load
Very high max of 78.5%
However, there is a big limitation, known as Crossover
Distortion occuring during zero crossings of signal
This is because for a BJT/MOS Class B stage, we need a
voltage at least equal to V /VTN (VTP ) for the output stage
transistors to turn on
This is also known as Deadband Distortion

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Class AB:
Eliminates crossover distortion by prebiasing the
output transistors, so that they remain at the verge
of conduction in the standby state
 exactly equal to 180
max slightly less than 78.5% due to a small amount
of standby power
Extremely popular and most widely used

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 VCC
Class B Push-Pull Output Stage:
Q1
BJT Implementation: Vi V0

Also known as Complementary Output Stage

Q2 RL
Uses dual symmetric power supply (VCC -VEE )
Typical values used:  3 V,  5 V,  12 V,  15 V VEE

Q-point: Vi = V0 = 0  VBE1 = VEB2 = 0

 Both Q1 and Q 2 cutoff  Zero standby power
As Vi  beyond zero, VBE1  and VEB2 
Note: VBE1 + VEB2 = 0 (always)
 Q1 moves towards turning on and Q2 is pushed
deeper into cutoff
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However, Vi has to become at least equal to V for
Q1 to conduct (based on the simple model of diode)
Till then, V0 remains zero
Once Vi becomes greater than V , Q1 turns on, supplies
current to the load (R L ), and V0 starts to increase
Similarly, As Vi  below zero, VBE1  and VEB2 
 Q2 moves towards turning on and Q1 is pushed
deeper into cutoff
Again, Vi has to become at least equal to − V for
Q 2 to conduct

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Once Vi becomes less than − V , Q 2 turns on,
pulls current away from the load (R L ), and V0
starts to decrease (note that V0 is negative
under this condition)
That's the origin of the name Push-Pull
Note: Each output transistor remains on for
half the cycle

Voltage Transfer Characteristic (VTC):

Plot of V0 versus Vi
Note the deadband (V0 = 0) between − V and V

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 V0

[VCC – VCE1(sat)]

Q1 saturated

Q1, Q2 off Q1 on
Q2 off

slope ~ 1
–V
[VEE + VEC2(sat) – VEB2]
0
[VCC – VCE1(sat) + VBE1] Vi
V
slope ~ 1

Q2 on
Q1 off

Q2 saturated

[VEE + VEC2(sat)]

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For positive Vi above V , V0 increases almost linearly
with Vi with a slope slightly less than unity and no
phase shift, since it is a CC stage
As V0 , VCE1 , and Q starts to move towards saturation
 Positive V0,max = VCC − VCE1(sat )
However, for this to happen, Vi has to be greater than
VCC ( there is an extra drop of VBE1 )
 This point will never be reached
The characteristic for negative Vi can be similarly
understood

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Crossover Distortion:
Vi, V0

VM Crossover
(Deadband)
Vi V0
Distortion

V

0
t
–V

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Quantified by  (refer to the diagram)
−1 V 
Given by:  = sin  
 M
V
VM : Amplitude of the input signal
Appears four times over a complete cycle
Quantified by a term known as the Total Crossover
Distortion (TCD), expressed in percent:
2
TCD = 100%

Problem becomes more acute as VM 
For VM < V , no output (V0 = 0 always)

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MOS Implementation:
VDD
Working principle absolutely
VSS
similar to BJT implementation
M1
Only exception that V Vi V0
replaced by VTN and VTP
M2
Q-point: Vi = V0 = 0 RL
Note that both devices VDD

suffer from body effect VSS

 VTN and VTP function of V0

 VTC significantly nonlinear
 Output shows more distortion

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Output can swing all the way between VDD and VSS
However, as V0  during the positive half cycle, VDS1 
 M1 may enter linear region
Similar situation will occur during the negative half
cycle, and M 2 may enter linear region
This produces additional distortion in the output
Added to the fact that MOS devices are inherently
much poorer than their BJT counterparts in terms of
current carrying ability, makes this stage quite a poor
choice (needs very large W/L ratio)

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Class AB Push -Pull Output Stage:
Note: In a Class B stage, crossover distortion arises
due to the fact that the transistors are absolutely cold
in the standby state, i.e., dead off
If somehow they can be prebiased , such that they are
very close to the turn-on state, but not quite there,
then a slight swing of input either way would make
one of these transistors turn on and either supply
current to the load or pull current away from load
 This is the whole idea behind a Class AB stage
Obvious fallout: Dissipation of standby power

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Note the additional circuitry VCC
in terms of IQ -Q3 -Q 4
Q3 and Q 4 are diode-connected IQ

This combination facilitates +

Q1

creation of a DC bias VBIAS Q3 I0

V0
between the bases of Q1 and Q 2 VBIAS

Consider idling condition with Q4

RL
Vi
–
R L open-circuited (I0 = 0) Q2

Neglecting base currents of Q1 -Q 2 , VEE

I BIAS flows through Q3 -Q 4 , and
develops a voltage drop:

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  IQ2 
VBIAS = VBE3 + VBE4 = VT ln 
 I I 
 S3 S4 
IQ , IS3 , and IS4 chosen in such a way that VBIAS 2V
Note: VBIAS is also equal to (VBE1 + VEB2 )
Thus, Q1 -Q 2 remain at the verge of conduction,
carrying a standby (or idling) current IStandby
 Causes standby (or idling) power dissipation
Noting that
 IStandby
2

VBIAS = VBE1 + VEB2 = VT ln  
I I
 S1 S2 

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and equating the two equations for VBIAS:
IS1IS2
Istandby = IQ
IS3 IS4
Q1 -Q 2 has to supply/sink large current to/from load
Hence, their BE junction areas are made large
 Large IS
IS of Q1 -Q 2 is typically 10 times or more than that of Q3 -Q 4
 IStandby is at least 10 times or more that of IQ
 Adds to power overhead of the circuit
There are better versions of the circuit available,
which we would explore in the chapter on op-amps

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Another Option:
Use VBE -multiplier circuit VCC

 R2 
VBIAS = VBE3 1 +  IQ
 R1 
Q1
Values of R1 and R 2 chosen +
R2
such that VBIAS 2V V0
Q3 VBIAS
(We have come across a similar
R1 RL
problem in the mid-sem exam) Vi
–
Q2
Since the resistors appear as a
VEE
ratio, this circuit has excellent
thermal tracking behavior
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