ESc201, Lecture 30: (Digital)

Mapping of Boolean expression to a Network of gates available in the library.

Let’ss try to implement a function by SOP .
Let
y = x1 . x 2 .x 3 + x1.x 2 .x 3 +x1.x 2 .x 3 +x1.x 2 .x 3

x1  
 x1 . x 2  x 2 .x 
x 3  x1 . x 2  x 2 .x
x3
x2  x1 . x 3  x1 .x 3  x 3
x3

x1
x2
x3
y
x1
x2
x3
Much ado about nothing !! Bad Example.
x1
x2
x3
 ESc201, Lecture 30: (Digital)
Implementation using only NAND gates
NAND to Inverter x x .x=x
NAND to AND x
y
x.y
x
x.y x
NAND to OR
y
y f = x . y = x+y

I l
Implementation
t ti using
i only
l NOR gates
t

NOR to Inverter x
x x + x=x
NOR to OR
y
x+y x
x+y x
NOR to AND y
y f = x + y = x.y
 ESc201, Lecture 30: (Digital) Implementation using only NOR gates
To implement using NOR gates, it is easiest to start with minimized Boolean
expression
i ini POS form.
f f =(a+b).(c+d).(f+g)
(a+b) (c+d) (f+g)
a
b

c AND
d f

g
h
a
b OR
c UNNECESSARY
f
There is a one
one--to
to--one mapping between OR
OR--AND
d
network and NOR network.
g T implement
To i l t SoP
S P expression
i usingi NOR gates,
gates
t , determine
d t i first
fi t the
th
h corresponding PoS expression and then follow the procedure outlined here. OR

x
yz
00 01 11 10
Implement f(x,y,z) = x .z+x .z using NOR gates
x
1 0 0 1 x
0 z
z
1 0 1 1 0 x f x f
 f =( x +z).(x + z) z
z
Similarly PoS expression can be implemented as NAND network by first converting it to SoP
expression and then following the procedure outlined earlier
 ESc201, Lecture 30: Digital Design Flow
x
System Description
x y z f y system f
z
0 0 0 0
Truth Table
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
Boolean Expression
1 0 1 1 f = x .y.z+x
y z+x . y.z+x
y z+x . y.z+x
y z+x . yy.zz
1 1 0 0
1 1 1 1

Minimized  f = x .z+x
z+x .z=z
z=z
Boolean Expression x
y

y
z C
Gate Netlist
Gate Netlist for circuit 
for circuit
level description x
z
 ESc201, Lecture 30: (Digital: Implementation Hazards)
A hazard or glitch in digital logic is a fault in the logic system due to a change at the input.
C
Causes and
d effects:
ff t
Due to some form of delay caused by logic elements (NOT, AND, OR gates etc.), results in the logic
not performing its function properly. It is a temporary problem, and the logic will finally come to the
desired function,, but the gglitch may
y propagate
p p g and cause pproblems.
Static-1 Hazard: The output should be 1 but goes momentary to 0 as a result of an input change (possible in AND-
Static- AND-
OR circuits) . Hence in SOP implementation with finite Gate delay.
BC00 01 11 10 Assume B=1, C=1, and A changes from 1 to 0
A 0 2 6 4
f =A.C
=A C +A
+A.B
B A
0 0 1 1 0 x
A x
1 3 7 5 B f
1 0 0 1 1 y
C y f
Remedy is to take another term shown by the dotted loop Glitch
t
Static--0 Hazard: The output should be 0 but goes momentary to 1 as a result of an input change
Static
(possible in OR-
OR-AND circuits). Hence POS implementation with finite gate delay.
YZ 00 01 11 10 X=0,Y=0, and Z changes from 0 to 1
Assume X=0,
X 0 2 6 4 f =(Y +Z) (X+ Z) Z
0 1 0 0 0 a a
Z
1 3 7 5 Y f b spike
1 1 1 1 0
X b f
Remedy is to take another factor shown by the dotted loop Glitch
t
Function hazards are non-
non-solvable hazards which occurs when more than one input variable changes
at the same time. Dynamic hazards often occur in larger logic circuits where there are different routes
to the output (from the input).
 ESc201, Lecture 30: (Digital) Representing positive and negative binary
One extra bit is required to carry sign information. Sign bit = 0 numbers
represents positive number and Sign bit = 1 represents negative no.
no
decimal Signed decimal Signed decimal Signed 1’s decimal Signed 2’s
Magnitude Magnitude complemen complemen
0 0000 -0 1000 t t

1 0001 -1 1001 -1 1110 -1 1111

2 0010 -2 1010 -2 1101 -2 1110

3 0011 -3 1011 -3 1100 -3 1101

4 0100 -4 1100 -4 1011 -4 1100

5 0101 -5 1101 -5 1010 -5 1011

6 0110 -6 1110 -6 1001 -6 1010

7 0111 -7 1111 -7 1000 -7 1001

Binary Subtraction How does one perform Subtraction of binary bits? 9’s complement
Complement of a number Decimal system:
10’s complement
9’s n-digit number x is 10n-1-x
9 s complement of n-
Can also be done for each digit
9’s complement of 85 ? 102  1  85  99  85  14
i.e. 9-5=4 and 9-8=1
9's complement of 123 = 999  123  876
10 n-digit number x is 10n –xx= 99’ss complement +1
10’ss complement of n- Check out for
10's complement of 123 = 9's complement of 123+1  877 yourselves that if the
568--123=445 568+877=1_445 number after subtraction is
Does it work for subtraction? 568
How to represent the carry of 1? The number is positive. negative, then the carry digit is 0.
 ESc201, Lecture 30: Digital Complement of a binary number
1’s complement
Bi
Binary system: 2’s complement
n--bit number x is 2n -1 -x
1’s complement of n

2’ complement off n
2’s n--bit i 2n -x
i number x is

1’s complement of 1011 ? 24  1  1011 or 1111  1011  0100

1’ complement
1’s l t is
i simply
i l obtained
bt i d by
b fli
flipping
i a bit (changing
( h i 1 to
t 0 and
d 0 to
t 1)
1's complement of 1001101 = 0110010
22'ss complement of 1010 = 11'ss complement of 1010+1  0101  1  0110
2's complement of 110010 =? After Flipping + adding 1  001110
Another way for those who cannot add a 1 : Leave all least significant 0’s as they are, leave
first 1 from the right unchanged and then flip all subsequent bits.
Advantages of using 2’s complement x1 S
10 – 6 = ? 1010  1010 2 Adder
x2 CY
1010 610   0110 2  1's complement is 1001  2's complement is 1010
+1010
10100
If Carry is 1; then number
obtained is positive.
 0100 2  410 Answer is +4
 ESc201, Lecture 30: (Digital) Binary Addition
A Binary Full-
Full-
A Binary Half-
Half-Adder unit
Adder unit takes
t k only
takes l 22--inputs,
i t produces
d a sum and
d a carry.
1 0 1 2-inputs Plus a
0 1 carry bit from
0 0 1 1 1 the previous
0 1 1 Half -Adder unit
1 0 1 (Cin).
Only Sum and NO Carry bit is Produced Carry(C) Sum (S) 1
1 1 111
Addition of 33--bit and 4-
4-bit C S S 110
101 1101 binary numbers need to ---------
110 + 1110 take the Carry from each 1110
1011 of the Half-
Half-Adder sum
11011
bits to the next higher bit. Cout Full Adder Cin
For each bit pair
S Half Adder Truth Table Full--Adder Truth Table
Full
a b S C
a b Cin S Cout a b
0 0 0 0 0 0 0 0 0
C Half Adder
0 1 1 0 0 0 1 1 0
S = a .b .c in + a .b .c in
1 0 1 0 0 1 0 1 0 + a .b .c in + a .b .c in ;
a b 0 1 1 0 1
a 1 1 0 1 C o u t = a .b .c in + a .b .c in
XOR S 1 0 0 1 0
b S a b+a b;
S=a.b+a.b; 1 0 1 0 1 + a .b .c in + a .b .c in
1 1 0 0 1
AND C C=a.b 1 1 1 1 1
Can also be done with Half -
Adder units (Check HA#8)