Bipolar Transistor Gate

Vcc = 5 V
• Consider a bipolar transistor in logic circuits
RC 1 kW
 It is operated in either two states Vout

 produces the two logic levels Vin RB

10 kW
fully conducting state (saturated / turned on)

or

fully non-conducting state (cut-off state)

1
 Bipolar Transistor Gate

• The simple but very practical logic inverter

Vcc = 5 V

RC 1 kW
Vout

V in RB

10 k W

V BE(ON) = 0.7V
V BE(SAT) = 0.8V
V CE(SAT) = 0.1V

2
 Bipolar Transistor Gate

1. When Vin is less than the turn on voltage VBE(ON) for the transistor

 collector current will essentially be zero

 output voltage Vout = VCC
V =5V
cc

R 1kW
C
V
2. When the input voltage is increased above VBE(ON) out

R
V in B

 transistor turns ON 10 kW

 enter the forward active region

 collector current IC =  IB

3. As input voltage (increase)   Output voltage (decrees) 

Vout = VCC – IC Rc

3
 Bipolar Transistor Gate
With sufficient input voltage, when the output voltage has fallen
sufficiently, the transistor will enter the saturation region.

V =5V
cc

R 1k W
C
V
out

R
V in B

10 k W

When the transistor enters the saturation region,

• The output voltage Vout remains fixed at VCE(sat) » 0.1 V,
• Output voltage shows very little change as the input voltage is further
increased.
4
 Voltage Transfer Characteristic

• One of the principal properties of interest in any digital circuit is the voltage-
transfer characteristic (VTC).

– VTC relates the output voltage to the input voltage under steady-state or
low frequency conditions.

VOUT
Active
V =5V
Cutoff
cc Saturation
BP1
VOH 5.0

R 1kW 4.0
C
V
out
3.0
R
V in B
2.0
10 kW

1.0

VOL BP2
1.0 2.0 3.0 4.0 5.0
VIN

VIL VIH

5
 Voltage Transfer Characteristic
V =5V
cc

At Breakpoint 1 (BP1) R
C
1 kW
V
– input voltage is just at the point of turning on the
out

transistor the transistor is at the edge of Vin

R
B
conduction. 10 kW
But
– output voltage is still very close to the cut-off
value
• collector current very small

At Breakpoint 2 (BP2)
– input voltage sufficient so that the transistor is at
the edge of saturation region

– collector current nearly at maximum value

• since any further increase in the input voltage
results in hardly any change the output voltage.

6
 Voltage Transfer Characteristic
• These breakpoints separate the following 3 regions of operation V =5V
– Cutoff, Active and Saturation
cc

R 1 kW
C
VOUT V
out

Active R
Cutoff Vin B
Saturation
BP1 10 kW
The co-ordinates of BP1 and BP2 are VOH 5.0

BP1 : (VIL, VOH)

4.0

BP2 : (VIH, VOL) 3.0

2.0

1.0

VOL BP2
1.0 2.0 3.0 4.0 5.0
VIN

VIL VIH

VIL input low voltage is the MAX value of VIN to guarantee that VOUT = VOH

VIH input high voltage is the MIN value of VIN to guarantee that VOUT = VOL

7
 Voltage Transfer Characteristic
Obtain numeric values for these quantities from circuit analysis.
VOUT
V =5V
cc Active
Cutoff
Saturation
R 1 kW BP1
C
V VOH 5.0
out

R 4.0
Vin B

10 kW 3.0
VBE(ON) = 0.7 V
VBE(SAT) = 0.8 V 2.0

VCE(SAT) = 0.1 V 1.0

VOL BP2
1.0 2.0 3.0 4.0 5.0
VIN

VIL VIH

1. VOH is equivalent to VCE with the transistor at edge of cut-off region, i.e. VCC
VOH = VCC

2. VOL is equivalent to VCE with transistor at the edge of saturation region. i.e. VCE(SAT)
here in this example VCE(SAT) = 0.1 V

 VOL = VCE(SAT)
8
 Voltage Transfer Characteristic
V V =5V
OUT
cc

Active

Cutoff Saturation
BP1
V 5.0 R 1k W
OH C
V
4.0
out

3.0
R
V in B

2.0
10 k W
1.0

BP2
V V
OL
IN
1.0 2.0 3.0 4.0 5.0

V V
IL IH

3. VIL which is the input voltage just sufficient to turn on the transistor.
In this example VBE(ON) = 0.7 V
 VIL = VBE(ON)

4. VIH is the input voltage just sufficient to saturate the transistor.

With the transistor just at the edge of saturation


VCC -VCE(SAT)
IC = IC(EOS ) IC (EOS) =
RC 9
 Voltage Transfer Characteristic
V

But also at the edge of the active region

OUT

Active

Cutoff


Saturation
BP1

I C ( EOS ) = h FE I B ( EOS )
V 5.0
OH

4.0

Thus where the input is VIH 3.0

2.0

V - V 1.0

 I
B ( EOS)
= IH BE( SAT) V
OL
BP2
V
IN
R 1.0 2.0 3.0 4.0 5.0

B
V V
IL IH

R V - V
= V + B  CC CE( SAT)
V V =5V
cc
IH BE( SAT) R h
C FE
R 1 kW
C
V
out
10 k W 5 - 0 .1
V = 0 .8 +  = 1 .5V Vin
R
B
IH 1k W 70
10 kW

 BP1 co-ordinates are VIN = 0.7 V and VOUT = 5.0 V

 BP2 co-ordinates are VIN = 1.5 V and VOUT = 0.1 V
10
 Metrics
Logic Levels
Positive Logic

VIL maximum allowed voltage at input for a logic low level

VIH minimum allowed voltage at input for a logic high level

VOUT
V OH 5.0 V Active
Cutoff Saturation
BP1
VOH 5.0

HIGH NM H
4.0

LS 3.0
1.5 V V IH
2.0

TW 1.0

0.7 V V IL BP2
VOL
LOW NM L V OL 0.1 V 1.0 2.0 3.0 4.0 5.0
VIN

VIL VIH
Input Output
11
 Metrics
• Between the two levels the transistor is in the active region,
– output level is not uniquely determined
– where because of the loose control on the transistor parameters.

• Hence this is a forbidden region

• The difference between VIH and VIL is the Transition Width.

TW = V - V
IH IL
= 1 .5 - 0 .7

VOUT = 0 .8 V
Active
Cutoff
Saturation
VOH 5.0 BP1
V 5.0 V
OH
4.0

HIGH NM
3.0 H

LS
2.0
1.5 V V
IH
1.0 TW
BP2
VOL VIN 0.7 V
LOW
V
IL NM
1.0 2.0 3.0 4.0 5.0 L V 0.1 V
OL

Input Output
VIL VIH
12
 Metrics
• Logic Swing is defined as the difference between the two output voltage levels

LS = VOH - VOL VOH 5.0 V

= 5.0 - 0.1 HIGH NMH

= 4.9 V LS
1.5 V VIH

TW
0.7 V VIL
• Noise Margins LOW NML VOL 0.1 V

NM H = VOH - V IH Input Output

= 5.0 - 1.5 V
OUT

= 3.5 V
Active
Cutoff Saturation
BP1
V 5.0
OH

4.0

NM L = V IL - VOL 3.0

= 0.7 - 0.1 2.0

1.0

= 0.6 V V
OL
1.0
BP2

2.0 3.0 4.0 5.0

V
IN

13
V V
IL IH
 Fan-Out

• Maximum number of load gates (circuits) of similar design as the driver

gate that can be connected to the output of a logic circuit.

Vcc = 5 V

RC 1 kW RC 1 kW
Vout
RB
Vin RB
Qo
10 k W Q1
10 k W

 In this example only one load gate is connected.

 The fan out from the driver Qo is 1.

14
 Fan-Out
• Noted that VOH for the individual inverter is VCC=+5V and the High noise margin NMH=3.5V.
– In all of these discussions the load was zero

Now the load is 1.

• VOH at VOUT is due to voltage divider action of RC and RB.

V =5V
cc

VOH = VBE ( SAT ) + R I

B RB
R 1 kW R 1 kW

VCC - VBE( SAT ) 

C C
RB V
VOH = VBE ( SAT ) + out

RC + RB V
in
R
B R
Q B
o Q
10 kW 1
10 kW

= 0.8 +
10
5.0 - 0.8
1 + 10
= 4.6V

• This is due to the application of one load gate

 VOH has been reduced from 5.0V to 4.6V.

15
 Fan-Out
Consequently NMH is also reduced V =5V
cc

Vcc = 5 V
R 1 kW
C
V
out
R 1 kW R 1 kW R
C V C Vin B


out
10 kW
V R
in B R
NM = V - V
Q B
o Q
10 kW
H OH IH
1
10 kW

= 4 .6 - 1 .5 V - V
I = IH BE(SAT)
B ( EOS) R
= 3 .1 V
B

R V - V
B  CC CE(SAT)
V = V +
IH BE(SAT) R h
C FE

10 k W 5 - 0 .1
V = 0 .8 +  = 1 . 5V
IH 1k W 70

Thus, the question becomes:

• What is the maximum number of load gates that can be connected to the output F ?
– What is maximum Fan-out ?

16
 Fan-Out
The answer found from finding the limit when NMH=0.

NMH = 0 V =5V
 Eqn. 2
cc

VOH = VIH
R 1 kW R 1 kW
C V C
out

V R
in B R
Q B
o Q
10 kW 1
10 kW

Note from the circuit, that when:

• Q0 is off and with a load of N gates connected

– There are N base resistors RB
– All effectively connected in parallel to VBE(SAT)

17
 Fan-Out
• Change Eqn. 1 to take account of N load
gates and then combining it with Eqn. 2. V
cc
=5V

 Solving for N in this quantity, we have the R

C
1 kW
V
R
C
1 kW

maximum number of load gates

out

V R
in B R
Q B
o Q
10 kW 1
10 kW

VOH = VBE(SAT) +
RB
+
RC RB

VCC -VBE( SAT) 

Vcc = 5 V
RC RC RC RC
1 kW 1 kW 1 kW 1 kW
RB Vout
R B  VCC - VCE ( SAT ) 
V - V BE ( SAT ) = V BE ( SAT ) +
RB
V BE ( SAT ) + N   Vin
Qo
RB

RC  
CC 10 kW Q1
RC + R B h FE  10 kW

N
VCC - V BE ( SAT ) RB
N  h FE - RB

VCC - VCE ( SAT ) 10 kW

Q2
RC

RB
10 kW
Q3

19
 Fan-Out

• Using the numeric values

5 - 0 .8 10
N  70 - = 50
5 - 0 .1 1

• Since a fractional gate load is impractical

 All fan-out problems we conservatively round down

 50.8  50

• Since NMH =0 this gives the absolute maximum number of load gates for
the fan-out

• One could also solve this problem by letting NMH=NML

20
 Propagation Delay

• The switching times of the Bipolar junction transistor

• Calculated by carrying out analysis of the charge-control model of the BJT.

5 V

5 ms
0 V
v (t)
i

t t t t t t
0 1 2 3 4 5
5 V
v (t)
o

0.1 V

Delay time : t = t -t Saturation time : t = t -t

d 1 0 s 4 3
Fall time : t = t -t Rise time : t = t -t
f 2 1 r 5 4 22
 Propagation Delay

• Qualitative analysis of the switching sequences:

• If the input voltage is a rectangular pulse at time t0,

– it can be assumed that the input abruptly changes from 0 to 5V

• As the input had previously been 0 V

 Transistor had been in the Cut-off.
 Output voltage is VCC = 5 V

23
 Propagation Delay

5 V

5 ms
0 V
v (t)
i

t t t t t t
0 1 2 3 4 5
5 V
v (t)
o

0.1 V

Delay time : t = t -t Saturation time : t= t -t

d 1 0 s 4 3
Fall time : t = t -t Rise time : t= t -t
f 2 1 r 5 4

Following the step input at time t0 there is no change at the output until time t1
– t1 is the time when collector current causes a noticeable decrease in output voltage.

The delay time (t1 - t0) is due to:

• The voltage across the emitter and collector junctions being unable to change instantaneously
due to the junction capacitances at these depletion regions.

The fall time (t2 – t1) is due to:

• Again due to the junction capacitance effects
• Also includes the effects of the finite transit time of the transistor.
24
 Propagation Delay
5V

5 s
0V
v (t)
i

t t t t t t
0 1 2 3 4 5
5V
v (t)
o
0.1 V

Delay time : t = t -t Saturation time : t = t -t

d 1 0 s 4 3
Fall time : t = t -t Rise time : t = t -t
f 2 1 r 5 4

At time t2 the transistor is at the edge of saturation,

· thus output voltage is essentially constant at VCE(sat) (=0.1 V).

At some time t3 (in this example 5 seconds) there is another step change in the input voltage back to 0 V.

The saturation time (t4 - t3) is due to:

· the removal of the overdrive charge from the neutral base region, or the base and collector regions.

The rise time (t5- t4) is due to:

· similar to fall time, but transistor is now turning off.

At time t5, the transistor is at the edge of cutoff,

· Thus the output is back to VCC.
25
 Propagation Delay
5V

5 s
0V
v (t)
i

t t t t t t
0 1 2 3 4 5
5V
v (t)
o
0.1 V

Delay time : t = t -t Saturation time : t = t -t

d 1 0 s 4 3
Fall time : t = t -t Rise time : t = t -t
f 2 1 r 5 4

• After t5, there is another delay, which is not apparent from the output waveform transistor

• The final recovery time (t6- t5)

– Base voltage changes form VBE(on) to 0 V, the quiescent input voltage.

• The switching times as calculated above are of very much interest to the digital IC designer.

• However of more interest to the digital IC user are the propagation delay times.
– These times are measured between two reference levels on the input and output voltage
waveforms. 26
 Propagation Delay
5V

5 ms
0V
v (t)
i

t t t t t t
0 1 2 3 4 5
5V
v (t)
o

0.1 V

Delay time : t = t -t Saturation time : t = t -t

d 1 0 s 4 3
Fall time : t = t -t Rise time : t = t -t
f 2 1 r 5 4

For in the inverter circuit the turn-on delay time tPHL is measured as the output is changing from a high
voltage level to a low voltage level.
t
t = t + f
PHL d 2

4 .2
= 0 . 73 +
2
= 2 .8 ns

For the turn-off delay time tPLH is measured as the output is changing from a low voltage level to a high
voltage level.
t t +t
t = t + r tp = PHL PLH
 PLH s 2
2
15 
= 24 + 2.8 + 31
2 =
2
= 31 ns
= 17 ns
27
 Summary

• Implementation Issues

• Need to analyse at the component level

• Need to take into account how these component level issues effect system level design

28
29