5EI06 R15

VNR VIGYANA JYOTHI INSTITUTE OF ENGINEERING AND TECHNOLOGY

(AUTONOMOUS)
III B.Tech I-Semester II-MID Examinations-November-2019
Linear and Digital IC Applications
(Electronics and Communication Engineering)
Time: 90 Minutes DOE: 09-11-2019(FN) Max. Marks: 30M
Part A
Answer the following. (3X2 = 6M)

1. a) Define the following terms as related to DAC: i) Linearity ii) Resolution [CO-2][BL-1]
b) What is meant by Tri-state logic? [CO-3][BL-1]
c) What is race around condition? How is it avoided? [CO-3][BL-1]

Part B
II. Answer one question from each Unit. (3X8=24M)
UNIT-I
1. a) Draw the circuit of a R-2R Ladder type DAC for 3 bits and derive expression for output voltage.
[CO-2][BL-3][4M]
b) Draw the schematic block diagram of dual slop A/D converter and explain its operation. Derive
expression for its output voltage
[CO-2][BL-4][4M]
(OR)
2. List the basic building blocks of a PLL and explain the operation of VCO with neat schematics.
[CO-2][BL-1][8M]
UNIT-II
3. a) What is the need of interfacing? Explain how the interfacing can be provided when TTL
drives the CMOS. [CO-2][BL-1][4M]
b) Explain the CMOS operation with open drain output.
[CO-2][BL-2][4M]
(OR)
4. a) What is meant by Tri-state logic? Draw the circuit diagram of Tri-state TTL logic and explain
its functionality. [CO-2][BL-5][5M]
b) Discuss the advantages and disadvantages of CMOS over TTL gate.
[CO-2][BL-5][3M]

UNIT-III
5. a) Design a 4 to 16 decoder using two 74×138 IC’s . [CO-3][BL-5][4M]
b) Implement the following Boolean expression using 74×151 IC F(z)=AB+BC+AC.
[CO-3][BL-5][4M]
(OR)
6. a) Design a modulo 6 counter using IC 7490. [CO-3][BL-3][4M]
b) Write short notes on Edge trigger flip flop and Master Slave flip flop. [CO-3][BL-1][4M]