Operating Systems

CS F372

Memory Management

Biju K Raveendran
 Paging Hardware

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 Paging Model of Logical & Physical Memory

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 Paging Example

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 Paging – Calculating internal fragmentation
• Page size = 2,048 bytes
• Process size = 72,766 bytes [35 pages + 1,086 bytes]
• Internal fragmentation of 2,048 - 1,086 = 962 bytes
• Worst case fragmentation = 1 frame – 1 byte
• On average fragmentation = 1 / 2 frame size
• So small frame sizes desirable?
• But each page table entry takes memory to track
• Page sizes growing over time
– Solaris supports two page sizes – 8 KB and 4 MB
– Intel supports two page sizes – 4KB and 4MB
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 Paging
• Disadvantage:
– Internal fragmentation
• Reduce the page size to reduce fragmentation
– Overhead because of increase in More page
table entries
• Advantage:
– Separation of user view of memory & actual
physical memory
– User process cannot access memory outside
of its page table
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 Implementation of Page Table
• Frame table will have one entry corresponding to each
physical page frame. Only one frame table per OS.
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PRLR) indicates size of the
page table
• In this scheme every data/instruction access requires
two memory accesses. One for the page table and one
for the data/instruction.

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 Implementation of Page Table
• The two memory access problem can be solved by the
use of a special fast-lookup hardware cache called
associative memory or translation look-aside buffers
(TLBs)
• Some TLBs store address-space identifiers (ASIDs) in
each TLB entry – uniquely identifies each process to
provide address-space protection for that process
• Instructions to load or modify the page table registers
are privileged.

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 Associative Memory
• Associative memory – parallel search
Page # Frame #

Address translation (p, d)

– If p is in associative register, get frame # out
– Otherwise get frame # from page table in
memory
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 Paging Hardware with TLB

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 Effective Access Time
• Associative Lookup =  time unit
• Assume memory cycle time is 1 microsecond
• Hit ratio – percentage of times that a page number is
found in the associative registers; ratio related to
number of associative registers
• Hit ratio = 
• Effective Access Time (EAT)
EAT = [(1 + )  + (1 + )(1 – )]/ 

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 Effective Access Time
• Example
– Hit ratio 80%
– 20 nsec to search in TLB
– 100 nsec to access Memory
– Effective Memory Access Time
– (E M A T) = (0.80 X 120) + (0.20 X 220) = 140 nsec
– (0.8 X 120 + 0.2 X 120) / 0.8 = 150nSec
If hit ratio is 98% then
EAT = (0.98 X 120) + (0.02 X 120) / 0.98= 122.45 nsec
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