OPERATING SYSTEMS CS F372

BIJU K RAVEENDRAN & TEAM

LECT #42: MEMORY MANAGEMENT

 Implementation of Page Table
• Frame table will have one entry corresponding to each
physical page frame. Only one frame table per OS.
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PRLR) indicates size of the
page table
• In this scheme every data/instruction access requires
two memory accesses. One for the page table and one
for the data/instruction.

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 Implementation of Page Table
• The two memory access problem can be solved by the
use of a special fast-lookup hardware cache called
associative memory or translation look-aside buffers
(TLBs)
• Some TLBs store address-space identifiers (ASIDs) in
each TLB entry – uniquely identifies each process to
provide address-space protection for that process
• Instructions to load or modify the page table registers
are privileged.

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 Translation Lookaside Buffer
• Each virtual memory reference can cause two physical
memory accesses
– One to fetch the page table
– One to fetch the data
• To overcome this problem a high-speed cache is set up
for page table entries
– Called a Translation Lookaside Buffer (TLB)
• Contains page table entries that have been most recently
used
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 Translation Lookaside Buffer
• Given a virtual address, processor examines the TLB
• If page table entry is present (TLB hit), the frame number
is retrieved and the real address is formed
• If page table entry is not found in the TLB (TLB miss), the
page number is used to index the process page table
• First checks if page is already in main memory
– If not in main memory a page fault is issued
• The TLB is updated to include the new page entry
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 Associative Memory
• Associative memory – parallel search
Page # Frame #

Address translation (p, d)

– If p is in associative register, get frame # out
– Otherwise get frame # from page table in
memory
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 Paging Hardware with TLB

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 Effective Access Time
• Associative Lookup =  time unit
• Assume memory cycle time is 1 microsecond
• Effective Access Time (EAT)
EAT = [TLB Time * # of hits + (Memory Access Time +
TLB Time)* Number of misses] / #of memory accesses

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 Effective Access Time
• Example
– # of memory requests: 1000, Number of Misses 200
– 20 nsec to search in TLB
– 100 nsec to access Memory
– Effective Memory Access Time?

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 Memory Protection
• Memory protection implemented by associating
protection bit with each frame
• One bit to specify the page is read write or read only
• Valid-invalid bit attached to each entry in the page
table:
– “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal
page
– “invalid” indicates that the page is not in the process’
logical address space
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 Valid (v) or Invalid (i) bit in a page table

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