A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_GM+ ICH7-M core logic
3

2007-03-20 3

REV:0.5

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 1 of 47
A B C D E
 A B C D E

Compal confidential
File Name : LA-3491P
Volga 2.0
1 1
Fan Control
page 4
Mobile Yonah/Merom Thermal Sensor Clock Generator
uFCPGA-478 CPU ADM1032AR ICS9LP306BGLFT
page 4,5,6 page 4 page 15

FSB
H_A#(3..31) 533/667MHz H_D#(0..63)

CRT DDR2-SO-DIMM X2
page 16 Intel Calistoga MCH DDR2 -400/533/667 BANK 0, 1, 2, 3 page 13,14
945GM
LVDS Conn PCBGA 1466 Dual Channel
page 17 page 7,8,9,10,11,12

2 2

DMI
USB2.0
USB Conn x2
page 29

MODEM AMOM
AC-LINK/Azalia
Audio Conexant CX20548
PCI-E BUS Intel ICH7-M CX20549-12
page 27

page 26
INTEL LAN PCI BUS mBGA-652
82562V 10 /100 AMP & Audio Jack
LED page 18,19,20,21 SATA TPA6017A2 page 28
page 23
page 31 SATA HDD Connector
3 3
SPI page 22
Mini-Card
CardBus Controller
RTC CKT. RJ45/11 CONN WLAN SPI ROM PATA Slave
IDE ODD Connector
page 19 page 23 page 25 CB-1410 25LF080A
page 31 page 22
page 24
LPC BUS
Power OK CKT.
page 34 Slot 0
page 24

Power On/Off CKT. SMSC KBC 1070

page 30
page 31

Touch Pad CONN. Int.KBD

4 DC/DC Interface CKT. page 32 page 30 4

page 33

Power Circuit DC/DC

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

Page 37、38、39、40 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 2 of 47
A B C D E
 5 4 3 2 1

Symbol Note :
Voltage Rails
Power Plane Description S0-S1 S3 S5
: means Digital Ground

VIN Adapter power supply (18.5V) N/A N/A N/A

D
B+ AC or battery power rail for power circuit N/A N/A N/A : means Analog Ground D

+CPU_CORE Core voltage for CPU ON OFF OFF

+VCCP 1.05V power rail for Processor I/O and MCH/ICH core power ON OFF OFF NOXDP@ : means just build when XDP function disable.
+0.9V 0.9V switched power rail for DDRII Vtt ON OFF OFF LP@ : means just build when Low power clock gen. install
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF BATT@ : means need be mounted when 45 level assy or rework stage.
+1.8V 1.8V power rail for DDRII ON ON OFF 45@ : means need be mounted when 45 level assy or rework stage.
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF 14@ : means need be mounted when 14.1"
+3VALW 3.3V always on power rail ON ON ON* WLAN@ : means need be mounted when have wireless LED Function
+3VS 3.3V switched power rail ON OFF OFF WLAN14@ : means need be mounted when have wireless LED Function and 14"
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+RTC_VCC RTC power ON ON ON
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
CONN@ : means ME parts
Debug@ : means Mini debug card use

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Calistoga 945GM R3 SA0000059L0
C
Calistoga 945GM R1 SA0000059A0 C

Calistoga 940GML R3 SA000011C10

Calistoga 940GML R1 SA000011C00

ICH7 R3 SA00000V1A0
ICH7 R1 SA00000V1F0
IAT50 945GM FF 46147932L01
IAT50 940GML DF 46147932L02
IAT50 940GML DF 46147932L03 (No WLAN)
B IAT60 945GM FF 46147932L21 B

IAT60 940GML DF 46147932L22

External PCI Devices IAT60 940GML DF 46147932L23 (No WLAN)
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
CARD BUS D6 AD22 2 C

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
A
DDR SO-DIMM 1 A4 10100100 A

CLOCK GENERATOR (EXT.) D2 11010010

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 3 of 47
5 4 3 2 1
 5 4 3 2 1

H_D#[0..63] <7>

<7> H_A#[3..31]
JP1A
+3VS
H_A#3 J4 E22 H_D#0
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 XDP_DBRESET#_R
R10
M3 E26 1 2 @ 1K_0402_5%
H_A#6
H_A#7
K5
M1
A5#
A6#
D2#
D3# H22
F23
H_D#3
H_D#4
ITP-XDP Connector Change to same as +VCCP
H_A#8 N2
A7# D4#
G25 H_D#5 Chimay 4/6 Change value in 5/02
H_A#9 A8# D5# H_D#6
J1 A9# D6# E25
D H_A#10 H_D#7 JP29 XDP_TDI R2 54.9_0402_1% D
N3 A10# D7# E23 1 2
H_A#11 P5 K24 H_D#8 1 2
H_A#12 A11# D8# H_D#9 XDP_BPM#5 GND0 GND1 XDP_TMS R3 54.9_0402_1%
P2 A12# D9# G24 3 OBSFN_A0 OBSFN_C0 4 1 2
H_A#13 L1 J24 H_D#10 XDP_BPM#4 5 6
H_A#14 A13# D10# H_D#11 OBSFN_A1 OBSFN_C1 XDP_TDO R4 54.9_0402_1%
P4 A14# D11# J23 7 GND2 GND3 8 1 2
H_A#15 P1 H26 H_D#12 XDP_BPM#3 9 10
H_A#16 A15# D12# H_D#13 XDP_BPM#2 OBSDATA_A0 OBSDATA_C0 XDP_BPM#5 R5 54.9_0402_1%
R1 A16# D13# F26 11 OBSDATA_A1 OBSDATA_C1 12 1 2
H_A#17 Y2 K22 H_D#14 13 14
H_A#18 A17# D14# H_D#15 XDP_BPM#1 GND4 GND5 XDP_HOOK1 R2199 1
U5 A18# D15# H25 15 OBSDATA_A2 OBSDATA_C2 16 2 @ 54.9_0402_1%
H_A#19 R3 N22 H_D#16 XDP_BPM#0 17 18
H_A#20 A19# D16# H_D#17 OBSDATA_A3 OBSDATA_C3 XDP_TRST# R6 51_0402_1%
W6 A20# D17# K25 19 GND6 GND7 20 1 2
H_A#21 U4 P26 H_D#18 21 22
H_A#22 A21# D18# H_D#19 OBSFN_B0 OBSFN_D0 XDP_TCK R7 54.9_0402_1%
Y5 A22# D19# R23 23 OBSFN_B1 OBSFN_D1 24 1 2
H_A#23 U2 L25 H_D#20 25 26
H_A#24 A23# D20# H_D#21 GND8 GND9
R4 A24# D21# L22 27 OBSDATA_B0 OBSDATA_D0 28
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 29 30 This shall place near CPU
H_A#26 A25# D22# H_D#23 OBSDATA_B1 OBSDATA_D1
T3 A26# D23# M23 31 GND10 GND11 32
H_A#27 W3 P25 H_D#24 33 34
H_A#28 A27# D24# H_D#25 R2200 XDP@ OBSDATA_B2 OBSDATA_D2
W5 A28# D25# P22 35 OBSDATA_B3 OBSDATA_D3 36
H_A#29 Y4 P23 H_D#26 1K_0402_5% 37 38
H_A#30 A29# D26# H_D#27 H_PW RGOOD GND12 GND13
W2 A30# D27# T24 1 2H_PWRGOOD_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_CPU_XDP CLK_CPU_XDP <15>
H_A#31 Y1 R24 H_D#28 XDP_HOOK1 41 42 CLK_CPU_XDP# CLK_CPU_XDP# <15>
<7> H_REQ#[0..4] A31# D28# HOOK1 ITPCLK#/HOOK5
L26 H_D#29 +VCCP 43 44 +VCCP
H_REQ#0 D29# H_D#30 VCC_OBS_AB VCC_OBS_CD H_RESET#_R R2201 1
K3 REQ0# D30# T25 2 1 45 HOOK2 RESET#/HOOK6 46 2 1K_0402_1% H_RESET#
H_REQ#1 H2 N24 H_D#31 C1455 0.1U_0402_16V7K 47 48 XDP_DBRESET#_R R2202 2 1 200_0402_1% XDP_DBRESET#
H_REQ#2 REQ1# D31# H_D#32 HOOK3 DBR#/HOOK7 XDP@
K2 REQ2# D32# AA23 XDP@ 49 GND14 GND15 50
H_REQ#3 J3 AB24 H_D#33 51 52 XDP_TDO XDP@
H_REQ#4 REQ3# D33# H_D#34 SDA TD0 XDP_TRST#
L5 REQ4# D34# V24 Removed at 5/30.(Follow 53 SCL TRST# 54
V26 H_D#35 55 56 XDP_TDI R2203 XDP@
H_ADSTB#0 L2
D35#
W25 H_D#36 Chimay) XDP_TCK 57
TCK1 TDI
58 XDP_TMS 0_0402_5%
<7> H_ADSTB#0 ADSTB0# D36# TCK0 TMS
H_ADSTB#1 V4 U23 H_D#37 59 60 XDP_PRE 1 2
<7> H_ADSTB#1 ADSTB1# D37# GND16 GND17
U25 H_D#38
C D38# H_D#39 CONN@ SAMTE_BSH-030-01-L-D-A C
D39# U22
AB25 H_D#40 Place R2203 within 200ps (~1") to CPU
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK A22 D42# H_D#43
<15> CLK_CPU_BCLK BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
D45# Y22
AC26 H_D#46

H_ADS# H1
D46#
D47# AA24
AC22
H_D#47
H_D#48
Thermal Sensor ADM1032AR-2
<7> H_ADS# ADS# D48#
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49# +3VS
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53 2
<7> H_DRDY# DRDY# D53#
R12 H_HIT# G6 AD20 H_D#54 C2
<7> H_HIT# HIT# D54#
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
<7> H_HITM# HITM# D55#

1
1 2 H_IERR# D20 AF23 H_D#56 0.1U_0402_16V4Z
+VCCP H_LOCK# IERR# D56# H_D#57 1 R13
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58 U1
<7> H_RESET# RESET# D58#
AD21 H_D#59 1 8 ICH_SMBCLK 10K_0402_5%
D59# H_D#60 VDD SCLK
<7> H_RS#[0..2] AE25

2
H_RS#0 D60# H_D#61 H_THERMDA ICH_SMBDATA
F3 RS0# D61# AF25 2 D+ SDATA 7
H_RS#1 F4 AF22 H_D#62 C3
H_RS#2 RS1# D62# H_D#63 H_THERMDC THERM_SCI#
G3 RS2# D63# AF26 1 2 3 D- ALERT# 6 THERM_SCI# <20>
H_TRDY# G2
<7> H_TRDY# TRDY# 2200P_0402_50V7K THERM# 4 5
H_DINV#0 THERM# GND
DINV0# J26 H_DINV#0 <7>
M26 H_DINV#1 R14
DINV1# H_DINV#1 <7>
XDP_BPM#0 AD4 V23 H_DINV#2 +3VS 1 2 ADM1032AR-2_MSOP8
BPM0# DINV2# H_DINV#2 <7>
XDP_BPM#1 AD3 AC20 H_DINV#3
BPM1# DINV3# H_DINV#3 <7>
XDP_BPM#2 AD1 10K_0402_5% Address:1001_101
B XDP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] <7>
H23 H_DSTBN#0 <13,14,15,20,25> ICH_SMBCLK ICH_SMBCLK
XDP_DBRESET# C20 DSTBN0# H_DSTBN#1 ICH_SMBDATA
<20> XDP_DBRESET# DBR# DSTBN1# M24 <13,14,15,20,25> ICH_SMBDATA
H_DBSY# E1 W24 H_DSTBN#2
<7> H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
<19> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0
<19,40> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
<7> H_DPWR# DPWR# DSTBP1#
XDP_BPM#4 AC2 MISC Y25 H_DSTBP#2
<40> H_PROCHOT# PRDY# DSTBP2#
XDP_BPM#5 AC1 AE24 H_DSTBP#3
PREQ# DSTBP3#
+VCCP 1 R15 2 H_PROCHOT# D21
PROCHOT#
56_0402_5% +5VS
<19> H_PWRGOOD H_PW RGOOD D6
H_CPUSLP# D7
PWRGOOD PWM Fan Control circuit
<7> H_CPUSLP# XDP_TCK SLP#
AC5 TCK
XDP_TDI AA6 A6 H_A20M# JP3
TDI A20M# H_A20M# <19>

1
XDP_TDO AB3 A5 H_FERR# 1 1
TDO FERR# H_FERR# <19> 1
R16 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# D1 C4 C5
TEST1 IGNNE# H_IGNNE# <19> 2
R17 2 1 51_0402_5% TEST2 D25 B3 H_INIT#
TEST2 INIT# H_INIT# <19>
XDP_TMS AB5 C6 H_INTR CH751H-40_SC76 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_85205-0200
TMS LINT0 H_INTR <19> 2 2
XDP_TRST# AB6 B4 H_NMI CONN@
H_NMI <19>

2
TRST# LINT1
Follow datasheet 12/05 LEGACY CPU
THERMAL +3VS
H_THERMDA A24 D5 H_STPCLK# FAN
H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# <19>
A25 THERMDC SMI# A3 H_SMI# <19>
H_THERMTRIP# C7
<7,19> H_THERMTRIP# THERMTRIP#

1
2
5
6
5
H_THERMDA, H_THERMDC routing together. U2 D

1
FOX_PZ47903-2741-42_YONAH 1 G Q1

P
Trace width / Spacing = 10 / 10 mil <30> FAN_PWM INB
4 3 AO6402_TSOP6 @ ZD1
THERM# 2 O S
CONN@ INA

G
RLZ5.1B_LL34

4
TC7SH00FU_SSOP5

2
A +VCCP A
1

R19
R18 H_DPSLP# 1 2

@ 56_0402_5% @ 56_0402_5%
R20 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H_DPRSTP# 1 2 2006/10/26 2006/07/26 Title

Issued Date Deciphered Date
B

@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
E

H_PROCHOT# 3 1 OCP# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OCP# <20,30,42>
C

Q2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
@ MMBT3904_SOT23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 4 of 47
5 4 3 2 1
 5 4 3 2 1

+VCCP +VCC_CORE
Length match within 25 mils JP1B JP1C
D D
The trace width 18 mils space

1
<40> VCCSENSE VCCSENSE AF7 AB26 AE18 K1
VCCSENSE VSS VCC VSS
+VCC_CORE 7 mils <40> VSSSENSE VSSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
R21 R22 AD25 AB15 M2
V_CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2

10U_0805_10V4Z
R23 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1

1 2 VSSSENSE 1 1 M6 AA22 AB14 A26

VCCP VSS VCC VSS

C6

C7
N6 AD22 AA13 D26
R24
2K_0402_1%
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
Close to CPU pin N21
T21
VCCP VSS AC19
AF19
AA12
AD12
VCC YONAH VSS E24
B21
Close to CPU pin AD26 VCCP VSS VCC VSS
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22

POWER, GROUNG, RESERVED SIGNALS AND NC

W21 VCCP VSS AA16 AE12 VCC VSS E21
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
<40> H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
CPU_VID0 AD6 AD13 AC10 B16
<40> CPU_VID0 VID0 VSS VCC VSS
CPU_VID1 AF5 AC14 AC9 A16
<40> CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
<40> CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
<40> CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
C <40> CPU_VID4 VID4 VSS VCC VSS C
CPU_VID5 AF2 AA11 AE9 E16
<40> CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
<40> CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
V_CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
<15> CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 CPU_BSEL1
1 <15> CPU_BSEL1
CPU_BSEL2
B23
C21
BSEL1 VSS AD8
AC8
F20
E20
VCC VSS B11
A11
<15> CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+VCC_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25

0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R25

R26

R27

R28

AA17 C5 C15 T26

mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
B B
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

FOX_PZ47903-2741-42_YONAH FOX_PZ47903-2741-42_YONAH
CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 5 of 47
5 4 3 2 1
 5 4 3 2 1

D +VCC_CORE D

1 1
C8
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M
2 2
1 1 1 1 1 1
C9 C10 C11 C12 C13 C14 C15
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2

+VCC_CORE

1 1
C16
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M
2 2
1 1 1 1 1 1
C17 C18 C19 C20 C21 C22 C23
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2

+VCC_CORE

1 1
C24
Place these capacitors on L8
(Sorth side,Secondary Layer) 10U_0805_6.3V6M
2 2
1 1 1 1 1 1
C25 C26 C27 C28 C29 C30 C31
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2

C C
+VCC_CORE

1 1
C32
Place these capacitors on L8
(Sorth side,Secondary Layer) 10U_0805_6.3V6M
2 2
1 1 1 1 1 1
C33 C34 C35 C36 C37 C38 C39
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2

Mid Frequence Decoupling

+VCC_CORE

330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7

1 1 1 1 1 1 ESR <= 1.5m ohm

C40 + C41 + C42 + C43 + C44 + C45 +
Capacitor > 1980uF
330U_D2E_2.5VM_R7
2 2 2 2 2 2
B
02/26 Change C43、C44、C45 to B

@ 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7 1.9mm height for PV build short

term solution

+VCCP

1
1 1 1 1 1 1
C47 + C48 C49 C50 C51 C52 C53

330U_D2E_2.5VM_R9 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 6 of 47
5 4 3 2 1
 5 4 3 2 1

<4> H_D#[0..63] H_A#[3..31] <4> Description at page11.

U3A U3B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 <20> DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 <15>
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# <20> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <15>
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# <20> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 <15>
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T1
HD4# HA7# <20> DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T2
D H_D#6 HD5# HA8# H_A#9 CFG4 CFG5 D
G1 HD6# HA9# F9 CFG5 F15 CFG5 <11>
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 PAD T3
HD7# HA10# <20> DMI_TXP0 DMIRXP0 CFG6
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# <20> DMI_TXP1 DMIRXP1 CFG7 CFG7 <11>
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 PAD T4
HD9# HA12# <20> DMI_TXP2 DMIRXP2 CFG8

DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <20> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD T5
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
H4 HD12# HA15# H13 CFG11 D15 CFG11 <11>
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <20> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <20> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>

CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T6
HD15# HA18# <20> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T7
HD16# HA19# <20> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T8
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <20> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <20> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <20> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <20> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# <13> M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 CLK_MCH_REF#

CLK
HD27# HA30# <14> M_CLK_DDR2 SM_CK2 D_REF_CLKN CLK_MCH_REF# <15>
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 CLK_MCH_REF
HD28# HA31# <14> M_CLK_DDR3 SM_CK3 D_REF_CLKP CLK_MCH_REF <15>
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0
W6 HD30# <13> M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 MCH_SSCDREFCLK# MCH_SSCDREFCLK# <15>
H_D#31 T5 M_CLK_DDR#1 AT1 D41 MCH_SSCDREFCLK
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP MCH_SSCDREFCLK <15>
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 GMCH_H32
HD33# HREQ#1 <14> M_CLK_DDR#3 SM_CK3# CLK_REQ#
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 <13> DDR_CKE0_DIMMA AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 DDR_CKE1_DIMMA AT20
HD36# HREQ#4 <13> DDR_CKE1_DIMMA SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# <14> DDR_CKE2_DIMMB SM_CKE2 NC0 C
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39
HD38# <14> DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 <4> NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# <13> DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1

NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 M_ODT0 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBP#[0..3] <4> <13> M_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 H_DSTBP#0 +1.8V M_ODT1
AB4 HD49# HDSTBP#0 K3 <13> M_ODT1 BA12 SM_ODT1 NC12 BA41
H_XSCOMP/H_YSCOMP trace H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 <14> M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
width and spacing is 5/20. HD51# HDSTBP#2 <14> M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R29 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R30 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 V_DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 <20> PM_BMBUSY# T32

HD58# HDINV#3 H_DINV#3 <4> RESERVED1
1

H_D#59 AC6 R32

HD59# RESERVED2
R31

R32

H_D#60 AB5 <13,14> DDR_THERM# PM_BMBUSY# G28 F3

H_D#61 HD60# H_RESET# DDR_THERM# PM_BMBUSY# RESERVED3
AD10 HD61# HCPURST# B7 H_RESET# <4> F25 PM_EXTTS0# RESERVED4 F7

RESERVED
PM
H_D#62 AD4 E8 H_ADS# <20,40> DPRSLPVR R33 1 2 0_0402_5% PM_EXTTS#1 H26 AG11
HD62# HADS# H_ADS# <4> PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,19> H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# <4>
2

HD63# HTRDY# H_DPWR# PWROK PM_THERMTRIP# RESERVED6

HDPWR# J9 H_DPWR# <4> AH33 PWROK RESERVED7 H7
H8 H_DRD Y# 2 1 PLTRST_R# AH34 J19
HDRDY# H_DRDY# <4> <18,20,22,24,25,30,31> PLT_RST# RSTIN# RESERVED8
J13 C3 H_DEFER# R34 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# <4> RESERVED9
H_VREF K13 D4 H_HITM# <18> MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# <4> ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# <4> RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# <4> RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# <20,40> VGATE_INTEL R35 1 2 @ 0_0402_5% PWROK A35
HYRCOMP HBREQ0# H_BR0# <4> RESERVED13
H_YSCOMP U1 C6 H_BNR# <20,30> PM_POK R36 1 2 0_0402_5%
HYSCOMP HBNR# H_BNR# <4>
H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# <4> +3VS
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# <4>
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# <4>
24.9_0402_1%

24.9_0402_1%

V_DDR_MCH_REF
1

Layout Note: R39

trace width and
R37

R38

B4 H_RS#0 DDR_THERM# 2 1
HRS0# H_RS#1 Route as short 10K_0402_5%
HRS1# E6 spacing is 20/20.
D6 H_RS#2 as possible
HRS2#
H_RS#[0..2] <4>
2

R40
CALISTOGA_FCBGA1466~D +1.8V PM_EXTTS#1 2 1
@ 10K_0402_5%

1
M_OCDOCMP0
R41 M_OCDOCMP1

Layout Note: 100_0402_1%

40.2_0402_1%

40.2_0402_1%
2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /

1
V_DDR_MCH_REF
<13,14> V_DDR_MCH_REF
0.1U_0402_16V4Z

H_SWNG1 trace width and spacing is 18/20. R44

R42

R43
GMCH_H32 1 2 CLKREQC# CLKREQC# <15>
1 R45 0_0402_5%
+VCCP +VCCP

2
C54

100_0402_1% @ @
+VCCP
2

2
221_0603_1%

221_0603_1%
1

1
100_0402_1%
1

R46

R47
R48

A A
2

H_SWNG0 H_SWNG1
2

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1 Stuff R42 & R43 for A1 Calistoga

1

200_0402_1%

R49

R50

1
R51

C57

C55

C56

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

2
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 7 of 47
5 4 3 2 1
 5 4 3 2 1

D D

U3D U3E
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
<13> DDR_A_BS#0 SA_BS0 SA_DQ0 <14> DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
<13> DDR_A_BS#1 SA_BS1 SA_DQ1 <14> DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
<13> DDR_A_BS#2 SA_BS2 SA_DQ2 <14> DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
<13> DDR_A_DM[0..7] AK35 DDR_A_D5 <14> DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
<13> DDR_A_DQS[0..7] AL27 DDR_A_D17 <14> DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
C DDR_A_DQS4 DDR_A_D22 DDR_B_DQS4 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
<13> DDR_A_DQS#[0..7] AN20 DDR_A_D27 <14> DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
<13> DDR_A_MA[0..13] SA_DQ38 AL14 <14> DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
<13> DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 <14> DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
<13> DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 <14> DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
<13> DDR_A_WE# SA_WE# SA_DQ58 <14> DDR_B_WE# SB_WE# SB_DQ58
T9 PAD SA_RCVENIN# AK23 AF6 DDR_A_D59 T10 PAD SB_RCVENIN# AK16 AK3 DDR_B_D59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
T11 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T12 PAD AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 8 of 47
5 4 3 2 1
 5 4 3 2 1

D D

PEGCOMP trace width

and spacing is 18/25 mils. R52 +1.5VS_PCIE
U3C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 SDVOCTRL_CLK EXP_COMPO D38

EXP_RXN0 F34
LVDSA0+ B37 G38
<17> LVDSA0+ LVDSA1+ LA_DATA0 EXP_RXN1
<17> LVDSA1+ B34 LA_DATA1 EXP_RXN2 H34
LVDSA2+ A36 J38
<17> LVDSA2+ LA_DATA2 EXP_RXN3
EXP_RXN4 L34
LVDSA0- C37 M38
<17> LVDSA0- LVDSA1- LA_DATA#0 EXP_RXN5
<17> LVDSA1- B35 LA_DATA#1 EXP_RXN6 N34
LVDSA2- A37 P38
<17> LVDSA2- LA_DATA#2 EXP_RXN7
EXP_RXN8 R34
LVDSB0+ F30 T38
<17> LVDSB0+ LB_DATA0 EXP_RXN9
LVDSB1+

LVDS
<17> LVDSB1+ D29 LB_DATA1 EXP_RXN10 V34
LVDSB2+ F28 W38
<17> LVDSB2+ LB_DATA2 EXP_RXN11
EXP_RXN12 Y34
LVDSB0- G30 AA38
<17> LVDSB0- LB_DATA#0 EXP_RXN13
LVDSB1- D30 AB34
<17> LVDSB1- LB_DATA#1 EXP_RXN14
LVDSB2- F29 AC38
<17> LVDSB2- LB_DATA#2 EXP_RXN15
LVDSAC+ A32 D34
<17> LVDSAC+ LA_CLK EXP_RXP0
LVDSAC- A33 F38
<17> LVDSAC- LVDSBC+ LA_CLK# EXP_RXP1
<17> LVDSBC+ E26 LB_CLK EXP_RXP2 G34
LVDSBC- E27 H38
R53 <17> LVDSBC- LB_CLK# EXP_RXP3
J34

PCI-EXPRESS GRAPHICS
ENABLT BKLT_CTL EXP_RXP4
1 2 <17> BKLT_CTL D32 LBKLT_CTL EXP_RXP5 L38
C ENABLT C
<17,30> ENABLT J30 LBKLT_EN EXP_RXP6 M34
+3VS R2211 1 2 10K_0402_5% H30 N38
100K_0402_5% R2212 1 LCTLA_CLK EXP_RXP7
2 10K_0402_5% H29 LCTLB_DATA EXP_RXP8 P34
LCD_CLK G26 R38
<17> LCD_CLK LDDC_CLK EXP_RXP9
LCD_DAT G25 T34
<17> LCD_DAT ENAVDD LDDC_DATA EXP_RXP10
<17> ENAVDD F32 LVDD_EN EXP_RXP11 V38
2 1 LIBG B38 LIBG EXP_RXP12 W34
R54 1.5K_0402_1% C35 Y38
LVBG EXP_RXP13
C33 LVREFH EXP_RXP14 AA34
+3VS C32 AB38
LVREFL EXP_RXP15

EXP_TXN0 F36
+1.5VS R2172 1 2 0_0402_5% COMPS A16 G40
R2173 LUMA TVDAC_A EXP_TXN1
+1.5VS 1 2 0_0402_5% C18 TVDAC_B EXP_TXN2 H36
+1.5VS R2174 1 2 0_0402_5%
CRMA A19 J40
TVDAC_C EXP_TXN3
1

TV
EXP_TXN4 L36
+1.5VS 1 2 J20 TV_IREF EXP_TXN5 M40
R55 R56 R57 N36
10K_0402_5% 10K_0402_5% 0_0603_5% EXP_TXN6
B16 TV_IRTNA EXP_TXN7 P40
+1.5VS 1 2 B18 R36
2

R2251 TV_IRTNB EXP_TXN8

B19 TV_IRTNC EXP_TXN9 T40
LCD_CLK 0_0402_5% V36
LCD_DAT EXP_TXN10
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 TV_DCONSEL0 EXP_TXN12 Y36
EXP_TXN13 AA40
EXP_TXN14 AB36
EXP_TXN15 AC40
<16> CRT_SMBCLK C26 DDCCLK
CRT

<16> CRT_SMBDAT C25 DDCDATA EXP_TXP0 D36

EXP_TXP1 F40
VSYNC H23 G36
HSYNC VSYNC <16> VSYNC HSYNC VSYNC EXP_TXP2
<16> HSYNC G23 HSYNC EXP_TXP3 H40
3

B B
<16> CRT_BLU E23 BLUE EXP_TXP4 J36
D23 BLUE# EXP_TXP5 L40
D2 C22 M36
<16> CRT_GRN GREEN EXP_TXP6
B22 GREEN# EXP_TXP7 N40
<16> CRT_RED A21 RED EXP_TXP8 P36
@ PACDN042_SOT23~D B21 R40
1

RED# EXP_TXP9
EXP_TXP10 T36
EXP_TXP11 V40
2 1 CRT_IREF J22 W36
CRT_IREF EXP_TXP12
EXP_TXP13 Y40
R58 AA36
255_0402_1% EXP_TXP14
EXP_TXP15 AB40

CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 9 of 47
5 4 3 2 1
 5 4 3 2 1

+1.5VS_DPLLA +1.5VS_DPLLB

Place close to Pin G41 1 2

R59
0_1206_5%

+2.5VS +2.5VS

0.1U_0402_16V4Z
+1.5VS_DPLLA L1 +1.5VS_DPLLB L2
1 CHB1608U301_0603 @ CHB1608U301_0603
C59 2 1 +1.5VS 2 1 +1.5VS

C58
D 0.1U_0402_16V4Z D
U3H
+VCCP +2.5VS 2

0.1U_0402_16V4Z
C62
VCC_SYNC H22 1 2 1 1

0.1U_0402_16V4Z
C63
1 1

330U_D2E_2.5VM
C60
AC14 + + @
VTT0

330U_D2E_2.5VM
C61
AB14 VTT1 VCCTX_LVDS0 B30
W14 C30 +1.5VS_PCIE
VTT2 VCCTX_LVDS1 R60 2 2 2 2
V14 VTT3 VCCTX_LVDS2 A30
T14 0_0805_5%
VTT4 10U_0805_6.3V6M
R14 VTT5 VCC3G0 AB41 2 1 +1.5VS
P14 AJ41
N14
VTT6
VTT7
VCC3G1
VCC3G2 L41 W=40 mils 1
M14 VTT8 VCC3G3 N41 1 C65 1 C66
L14 R41 +
VTT9 VCC3G4
AD13 VTT10 VCC3G5 V41
AC13 Y41 10U_0805_6.3V6M
VTT11 VCC3G6 2 2 2
220U_D2_2VM_R9

AB13 VTT12
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL
Y13 VTT14 VCCA_3GBG G41 +2.5VS
C67

+ W13 H41 C64

VTT15 VSSA_3GBG 220U_D2_2VM_R9 BLM11A601S_0603
V13 VTT16
U13 L3
2 VTT17

2200P_0402_50V7K
T13 E21 MCH_CRTDAC 1 2 +2.5VS
VTT18 VCCA_CRTDAC0

0.1U_0402_16V4Z
R13 VTT19 VCCA_CRTDAC1 F21
N13 VTT20 VSSA_CRTDAC2 G21 1 1
M13 VTT21

C74

C75
L13 VTT22
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA 2 2
AA12 VTT24 VCCA_DPLLB C39 +1.5VS_DPLLB
Y12 VTT25 VCCA_HPLL AF1 +1.5VS_HPLL
W12 VTT26
V12 VTT27
U12 VTT28 VCCA_LVDS A38 +2.5VS
T12 VTT29 VSSA_LVDS B39
C
R12 VTT30 C
+1.5VS
P12 VTT31 12/28
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
R2221 PCI-E/MEM/PSB PLL decoupling
4.7U_0805_10V4Z

2.2U_0805_16V4Z

L12 VTT34 VCCA_TVBG H20 2 1

R11 VTT35 VSSA_TVBG G20
1 1 P11 0_0402_5%
VTT36
C76

C77

N11 VTT37
M11 E19 R2222 +1.5VS_3GPLL +1.5VS
VTT38 VCCA_TVDACA0 R64 R65
R10 VTT39 VCCA_TVDACA1 F19 2 1
2 2 3GPLL 2
P10 VTT40 VCCA_TVDACB0 C20 1 2 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N10 D20 0_0402_5% 0.5_0805_1% 0_0805_5%
VTT41 VCCA_TVDACB1 R2223
M10 VTT42 VCCA_TVDACC0 E20
P9 VTT43 VCCA_TVDACC1 F20 2 1 1 1 1
N9 C79
VTT44

C78

C80
M9 0_0402_5%
VTT45 R2224
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 AH2 2 2 2
VTT47 VCCD_HMPLL1 2 1
N8 VTT48
M8 0_0402_5% @
VTT49 10U_0805_6.3V6M
P7 VTT50 VCCD_LVDS0 A28 +1.5VS
N7 VTT51 VCCD_LVDS1 B28
M7 C28 +1.5VS
VTT52 VCCD_LVDS2 R2225
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 2 1
M6 VTT55 VCCDQ_TVDAC H19
MCH_A6 0_0402_5% +1.5VS_MPLL +1.5VS_HPLL
A6 VTT56
0.47U_0603_10V7K

R5 A23 +3VS R67 R68

VTT57 VCCHV0
P5 VTT58 VCCHV1 B23 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
0.1U_0402_16V4Z

1 N5 B25 0_0805_5% 0_0805_5%

VTT59 VCCHV2
C84

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M5 VTT60 1 1
P4 AK31 C86
VTT61 VCCAUX0
N4 VTT62 VCCAUX1 AF31 1 1 1 1
2
C85

M4 AE31 10U_0805_6.3V6M C88 C90

VTT63 VCCAUX2 2 2

C87

C89
R3 VTT64 VCCAUX3 AC31
B P3 AL30 10U_0805_6.3V6M 10U_0805_6.3V6M B
VTT65 VCCAUX4 2 2 2 2
N3 VTT66 VCCAUX5 AK30
0.22U_0603_10V7K

M3 VTT67 VCCAUX6 AJ30

R2 AH30 +1.5VS
VTT68 VCCAUX7
P2 VTT69 VCCAUX8 AG30
0.1U_0402_16V4Z

1 M2 VTT70 VCCAUX9 AF30

C91

MCH_D2 D2 AE30
VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1
0.22U_0603_10V7K

R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C92

1 P1 VTT74 VCCAUX13 AG29

+VCCP +1.5VS
C93

N1 VTT75 VCCAUX14 AF29

2
0.47U_0603_10V7K

M1 VTT76 VCCAUX15 AE29

VCCAUX16 AD29

2
2
1 VCCAUX17 AC29
C94

AG28 D3 D4
VCCAUX18
VCCAUX19 AF28 CH751H-40_SOD323 CH751H-40_SOD323
VCCAUX20 AE28 @ @
2 AH22

1 1

1 1
VCCAUX21
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 AJ20 R70 +2.5VS R71 +3VS
VCCAUX33 VCCAUX24
AE14 VCCAUX34 VCCAUX25 AH20
Y14 AH19 @ 10_0402_5% @ 10_0402_5%
VCCAUX35 VCCAUX26
AF13 P19

2
VCCAUX36 VCCAUX27
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15
VCCAUX38 VCCAUX29
AE12 VCCAUX39 VCCAUX30 P15
AD12 VCCAUX40 VCCAUX31 AH14

CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up

U3F CFG[19:18] have internal pull down

+VCCP +1.5VS +VCCP U3G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 AF27 W33 AT41 VCCSM_LF4 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 VCCSM_LF5
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_10V7K

0.47U_0603_10V7K
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C97
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)

C98
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34

2 2 0 = Lane Reversal Enable *
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30 0 = Calistoga *
C99

(Acc ording to Intel Napa Schematic Checklist & CRB

C100

C101

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30

Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30 CFG11 Rev1.301 document 2.2Kohm pull-down resistor
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 r1e q u=e s tReserved
)
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29
+1.8V
11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 0 = 1.05V *(Default)
10U_0805_6.3V6M U25 AA17 U30 AH28 CFG18 1 = 1.5V
VCC_NCTF27 VCCAUX_NCTF27 VCC27 VCC_SM27
1U_0603_10V4Z

T25 W17 T30 AJ27

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C102

C103

C104

C105
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
C106 C107 AC24 R17 N30 AY26
VCC_NCTF31 VCCAUX_NCTF31 VCC31 VCC_SM31 2 2 2 2
C108

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
10U_0805_6.3V6M U24 AB16 V29 AJ26
VCC_NCTF37 VCCAUX_NCTF37 VCC37 VCC_SM37
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
330U_D2E_2.5VM_R9

R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_10V7K
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
220U_D2_2VM_R9

V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22

C110

1 1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1

T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22

C111
+ + R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
C109

AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22

2 R72
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 <7> CFG5 1 2 @ 2.2K_0402_5%
2 2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R73 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 <7> CFG7
@ R21 V15 P27 AJ22
VCC_NCTF54 VCCAUX_NCTF54 VCC54 VCC_SM54 R74
AD20 VCC_NCTF55 VCCAUX_NCTF55 U15 N27 VCC55 VCC_SM55 AK21 <7> CFG9 1 2 @ 2.2K_0402_5%
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R75 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 <7> CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 N26 AW19 R76 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 <7> CFG12
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
V19 AE26 N25 AU19 1 1 R77 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 <7> CFG13
330U_D2E_2.5VM_R9

U19 AE25 M25 AT19 C113 C114 + C112

VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62 R78
T19 VCC_NCTF63 VSS_NCTF3 AE24 L25 VCC63 VCC_SM63 AR19 <7> CFG16 1 2 @ 2.2K_0402_5%
1 AD18 AE23 P24 AP19 @ 220U_D2_4VM
C115 VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
+ AB18 AE21 M24 AJ19 10U_0805_6.3V6M
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
Y18 AE19 AA23 AJ17 10U_0805_6.3V6M
2 VCC_NCTF68 VSS_NCTF8 VCC68 VCC_SM68
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
@ VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
L23 VCC73 VCC_SM73 AY15
+VCCP

0.47U_0603_10V7K
AC22 AW15 R79 1 2 @ 1K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG18
M19 AB22 AV15 R80 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 <7> CFG19
L19 AR6 Y22 AU15 1 R81 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 <7> CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15

C116
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 VCCSM_LF2 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 VCCSM_LF1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K

0.47U_0603_10V7K

L16 VCC110 N21 VCC85 VCC_SM85 AH12

M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
CALISTOGA_FCBGA1466~D AC20 BA8
VCC88 VCC_SM88
C117

C118

AB20 VCC89 VCC_SM89 AY8

Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

U3I U3J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 12 of 47
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7] V_DDR_MCH_REF <7,14>

<8> DDR_A_D[0..63] JP4

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D7 1 1
<8> DDR_A_DM[0..7] VSS DQ4

C119

C120
DDR_A_D0 5 6 DDR_A_D1
DDR_A_D4 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<8> DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D6
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D12 D
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
Place near JP34 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D10 35 36 DDR_A_D9
DDR_A_D11 DQ10 DQ14 DDR_A_D15
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D21 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D16
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#2 49 50
DQS2# NC DDR_THERM# <7,14>
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C121

C122

C123

C124

C125

C126

C127

C128

C129
53 VSS VSS 54
DDR_A_D22 55 56 DDR_A_D18
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D25 61 62 DDR_A_D29
DDR_A_D24 DQ24 DQ28 DDR_A_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D27 73 74 DDR_A_D26
DDR_A_D30 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9V 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9V <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7> M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D35 123 124 DDR_A_D36
DDR_A_D32 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C130

C131

C132

C133

C134

C135

C136

C137

C138

C139

C140

C141

C142

133 134 DDR_A_D39

DDR_A_D38 VSS DQ38 DDR_A_D34
135 DQ34 DQ39 136
DDR_A_D33 137 138
DQ35 VSS DDR_A_D40
139 VSS DQ44 140
DDR_A_D45 141 142 DDR_A_D44
B DDR_A_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D47
DDR_A_D43 DQ42 DQ46 DDR_A_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D52 157 158 DDR_A_D48
DDR_A_D53 DQ48 DQ52 DDR_A_D49
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9V NC,TEST CK1 M_CLK_DDR1 <7>
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168
RP1 RP2 56_0404_4P2R_5%
Pla ce these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 closely JP34,all 171 172
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" DDR_A_D51 173 DQ50 DQ54 174 DDR_A_D50
DDR_A_D55 175 176 DDR_A_D54
RP3 56_0404_4P2R_5% RP4 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D56 179 180 DDR_A_D60
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D61 181 DQ57 DQ61 182 DDR_A_D57
183 VSS VSS 184
RP5 56_0404_4P2R_5% RP6 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_A_RAS# DM7 DQS7#
1 4 4 1 DDR_A_MA9 187 VSS DQS7 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA12 DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP7 56_0404_4P2R_5% RP8 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA4 <4,14,15,20,25> ICH_SMBDATA
ICH_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA2 ICH_SMBCLK 197 198
<4,14,15,20,25> ICH_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
RP9 56_0404_4P2R_5% RP10 56_0404_4P2R_5%

1
10K_0402_5%

10K_0402_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0 1
DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C143 FOX_ASOA426-M4R-TRCONN@

R82

R83
A A
RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2
0.1U_0402_16V4Z
2
SO-DIMM A
3 4 1 M_ODT0
REVERSE

2
M_ODT1 1 4 3 2 DDR_A_MA13

56_0404_4P2R_5% RP13 56_0404_4P2R_5%

4 1 DDR_CKE1_DIMMA BOT side
3 2 DDR_A_MA11 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 13 of 47
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF <7,13>
<8> DDR_B_DM[0..7] JP5

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D1
<8> DDR_B_MA[0..13] 5 DQ0 DQ5 6

C144

C145
DDR_B_D5 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D2
15 VSS DQ7 16
D DDR_B_D7 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP34 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D21 43 44 DDR_B_D16
DDR_B_D20 DQ16 DQ20 DDR_B_D17
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C146

C147

C148

C149

C150

C151

C152

C153

C154
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC DDR_THERM# <7,13>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D22 55 56 DDR_B_D18
DDR_B_D23 DQ18 DQ22 DDR_B_D19
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
<8> DDR_B_BS#2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9V 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9V A10/AP BA1 DDR_B_BS#1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D37 123 124 DDR_B_D33
DDR_B_D36 DQ32 DQ36 DDR_B_D32
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C155

C156

C157

C158

C159

C160

C161

C162

C163

C164

C165

C166

C167

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D35 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D34 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D43
DDR_B_D47 DQ42 DQ46 DDR_B_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D49
DDR_B_D53 DQ48 DQ52 DDR_B_D52
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9V 163 164 M_CLK_DDR2
closely JP10,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP14 RP15 56_0404_4P2R_5% trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_BS#0 1 4 4 1 DDR_CKE3_DIMMB 177 178
DDR_B_MA10 DDR_B_MA11 DDR_B_D60 VSS VSS DDR_B_D56
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP18 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS#1 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D58 189 190
RP20 56_0404_4P2R_5% RP21 56_0404_4P2R_5% DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_RAS# 1 4 4 1 DDR_B_MA7 193 194 DDR_B_D63
DDR_CS2_DIMMB# 2 DDR_B_MA6 ICH_SMBDATA VSS DQ63
3 3 2 <4,13,15,20,25> ICH_SMBDATA 195 SDA VSS 196
ICH_SMBCLK 197 198 R84
<4,13,15,20,25> ICH_SMBCLK SCL SA0
RP22 56_0404_4P2R_5% RP23 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA4 203 204
GND GND

1
10K_0402_5%
DDR_B_WE# 2 3 3 2 DDR_B_MA2 1 10K_0402_5%

R85
A RP24 C168 FOX_ASOA426-M2RN-7F CONN@ A
56_0404_4P2R_5% RP25 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT3
3 4 1 M_ODT2
DDR_B_MA13
0.1U_0402_16V4Z
2
SO-DIMM B
1 4 3 2
STANDARD

2
56_0404_4P2R_5% RP26
4 1 DDR_B_BS#2 Bottom side
3 2 DDR_CKE2_DIMMB

56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 14 of 47
5 4 3 2 1
 5 4 3 2 1

+CK_VDD_MAIN1

FSLC FSLB FSLA CPU SRC PCI 1 2

+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz R86 0_0805_5% 1
C170
1 1 1
C171 C172 C173 C169 2 1 CLK_48M_ICH
0 0 1 133 100 33.3 10U_0805_10V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K @ 5P_0402_50V8C
2 2 2 2 C174 2 1 CLK_14M_ICH
@ 4.7P_0402_50V8C
+CK_VDD_MAIN2 C175
0 1 1 166 100 33.3 2 1 CLK_PCI_ICH Place close to U4
R88 @ 4.7P_0402_50V8C
+3VS 1 2 1 2 CK_VDD_REF C176 2 1 CLK_14M_KBC
Table : ICS954306 R87 0_0805_5% 1 1 1 1_0805_1% @ 4.7P_0402_50V8C
C177 C178 C179 C180 2 1 CLK_PCI_EC
1 2 CK_VDD_48 @ 4.7P_0402_50V8C
D D
FSB Frequency Selet: 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R89 C185 2 1 CLK_DEBUG_PORT
2 2 2 2.2_0805_1% @ 5P_0402_50V8C
C1456 2 1 CLK_33M_LPC
+CK_VDD_DP @ 4.7P_0402_50V8C
Stuff CLK_Ra CLK_Rb CLK_Rc
CPU Driven R90 12/05 ICS recommend Place crystal within C1457 2 1 CLK_33M_CBS
1 2 @ 4.7P_0402_50V8C
+3VS
0_0805_5%
500 mils of CK410
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf 1
C181
1
C182
1
C183
1
C184
1
C1469

Stuff CLK_Rd CLK_Re CLK_Rf 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 C186 2
533MHz 1 33P_0402_50V8J

1
+CK_VDD_DP +CK_VDD_MAIN1 U4
No Stuff CLK_Ra CLK_Rb CLK_Rc
Y1 Routing the trace at least 10mil
16 57 CLK_XTAL_IN 14.31818MHZ_16P
VDD X1
Stuff CLK_Rd

2
CK_VDD_48 10 56 CLK_XTAL_OUT C187 2 1 33P_0402_50V8J
VDD48 X2
667MHz 1
No Stuff CLK_Ra CLK_Rb CLK_Rc C188 5
+CK_VDD_DP VDDPCI R92 LP@0_0402_5%
SATACLKT 28 1 2
CLK_Re CLK_Rf 0.1U_0402_16V4Z 24 12/25
2 VDDSRC
2 R93 1 CLKIREF
SATACLKC 29 R94 1 2 LP@0_0402_5%
@ 0_0402_5% 1 33
+VCCP C189 VDDSATA
1 41 52 CPU_BCLK 1 2 CLK_CPU_BCLK
VDDSRC CPUCLKT0 CLK_CPU_BCLK <4>
C190 0.1U_0402_16V4Z R98 24_0402_5%
Place near U4
2

2 CK_VDD_REF CPU_BCLK# CLK_CPU_BCLK#

50 VDDCPU CPUCLKC0 51 1 2 CLK_CPU_BCLK# <4>
@ R97 @ 0.1U_0402_16V4Z R102 24_0402_5%
56_0402_5% 2
55 VDDREF
Place these components
R99 CLK_Rd 49 MCH_BCLK 1 2 CLK_MCH_BCLK
8.2K_0402_5% R101 33_0402_5% CPUCLKT1 R95 24_0402_5%
CLK_MCH_BCLK <7> near each pin within 40
1

FSA 2 1 1 2 <20> CLK_48M_ICH CLK_48M_ICH 2 1 FSA 11 48 MCH_BCLK# 1 2 CLK_MCH_BCLK#

MCH_CLKSEL0 <7> CLK_MCH_BCLK# <7>
C
R100 FSB
FSLA/USB_48MHz CPUCLKC1 R96 24_0402_5% mils. C

<5> CPU_BSEL0 1 2 15 FSLB/TEST_MODE

R103 1K_0402_5%
0_0402_5% <20> CLK_14M_ICH CLK_14M_ICH 2 1 CLKREF1 59 FSLC/TEST_SEL/REF1
1

CLK_Ra R104 33_0402_5% 64 PAD T32 CLKREQD# 1 2 C191

R105 *CLKREQA# @ 1000P_0402_50V4Z
Must fine tune12/08 18 SSCDREFCLK 1 2 MCH_SSCDREFCLK CLKREQC# 1 2 C1461
LCDCLK_SST/SRCCLKT0 MCH_SSCDREFCLK <7>
1K_0402_5% CLKIREF 46 R106 24_0402_5% @ 1000P_0402_50V4Z
R107 910_0402_1% IREF SSCDREFCLK#1 MCH_SSCDREFCLK#
19 2 MCH_SSCDREFCLK# <7>
2

LCDCLK_SSC/SRCCLKC0 R108 24_0402_5%

61 CPU_STOP#
H_STP_CPU#
<20> H_STP_CPU#
H_STP_PCI# 8 22
+VCCP <20> H_STP_PCI# PCI/SRC_STOP# SRCCLKT2
CLK_ENABLE# 9 23
<40> CLK_ENABLE# Vtt_PwrGd#/PD SRCCLKC2
2

CLK_PCI_ICH 2 R111 1 PCI_ICH 7 12/25

<18> CLK_PCI_ICH **SEL_LCDCLK#/PCICLK_F1
R112 33_0402_5% 30 PCIE_SATA 1 2 CLK_PCIE_SATA
SATA1/SRCCLKT4 CLK_PCIE_SATA <19>
R113 24_0402_5%
1K_0402_5% CLK_14M_KBC 2 1 CLKREF0 60 31 PCIE_SATA# 1 2 CLK_PCIE_SATA#
<30> CLK_14M_KBC REF0/PCICLK1 SATA1/SRCCLKC4 CLK_PCIE_SATA# <19>
R114 33_0402_5% R115 24_0402_5%
1

FSB 1 2 62
MCH_CLKSEL1 <7> *REQ_SEL/PCICLK2
CLK_DEBUG_PORT 2 1 R117 PCI_MINI
<25> CLK_DEBUG_PORT
1 2 R116 DEBUG@ 33_0402_5% 1 63 PAD T33
<5> CPU_BSEL1 *SEL_PCI1/PCICLK3 *CLKREQB#
R118 1K_0402_5% 10K_0402_5%2 1 R2209 PCI_CLK3
0_0402_5% 2 1 PCI_EC 2 20
<30> CLK_PCI_EC **SEL_SATA1/PCICLK4 SRCCLKT1
1

CLK_Rb R119 33_0402_5%

@ R120 CLK_33M_CBS
2 1 PCI_CBS 3 21
<24> CLK_33M_CBS **SEL_SATA2/PCICLK5 SRCCLKC1
R121 33_0402_5%
0_0402_5% +3VS CLK_33M_LPC
2 1 PCI_LPC 6
<31> CLK_33M_LPC PCICLK6
CLK_Re R2171 33_0402_5% 26
2

SRCCLKT3
R122 2 1@ 10K_0402_5% PCI_EC
SRCCLKC3 27
B ICH_SMBDATA B
<4,13,14,20,25> ICH_SMBDATA 54 SDATA
+VCCP
<4,13,14,20,25> ICH_SMBCLK ICH_SMBCLK 53 35 PCIE_ICH 1 2 CLK_PCIE_ICH
SCLK SATA2/SRCCLKT5 CLK_PCIE_ICH <20>
R123 24_0402_5%
2

34 PCIE_ICH# 1 2 CLK_PCIE_ICH#
SATA2/SRCCLKC5 CLK_PCIE_ICH# <20>
R125 R124 24_0402_5%
2 R126 1 NOXDP@10K_0402_5% +3VS
R129 1K_0402_5% <7> CLK_MCH_REF CLK_MCH_REF 24_0402_5% 2 1R127 MCH_REF 13 NOXDP@
8.2K_0402_5% DOTT_96MHz CLKREQC#
2 R128 1 CLKREQC# <7>
1

CLKREF1 2 1 1 2 <7> CLK_MCH_REF# CLK_MCH_REF# 24_0402_5% 2 1R131 MCH_REF# 14 45 CPU_XDP 1 0_0402_5%

2 CLK_CPU_XDP
DOTC_96MHz *CPUCLKT2_ITP/CLKREQC# CLK_CPU_XDP <4>
R1133 XDP@ 24_0402_5%
MCH_CLKSEL2 <7>
1 2 R130 37 MCH_3GPLL 1 2 CLK_MCH_3GPLL
<5> CPU_BSEL2 SRCCLKT6 CLK_MCH_3GPLL <7>
R133 1K_0402_5% R134 24_0402_5%
0_0402_5% 36 MCH_3GPLL# 1 2 CLK_MCH_3GPLL#
SRCCLKC6 CLK_MCH_3GPLL# <7>
1

CLK_Rc 4 R135 24_0402_5%

@ R136 GND
NOXDP@ : means just build when XDP function disable. 12 43
0_0402_5% GND SRCCLKT8
CLK_Rf XDP@ : means just build when XDP function enable. 17 42 12/25
2

GND SRCCLKC8 R22261 NOXDP@10K_0402_5%

2 +3VS
NOXDP@ 0_0402_5%
When this time, docking PCI express will not work. 58 GND
2 R2227 1 CLKREQD#
CLKREQD# <25>
47 44 CPU_XDP# 1 2 CLK_CPU_XDP#
+3VS GNDCPU *CPUCLKC2_ITP/CLKREQD# CLK_CPU_XDP# <4>
LCD(Low)/SRC(High) R2206 XDP@ 24_0402_5%
Pin44/45 function select 25 39 PCIE_MCARD 1 2 CLK_PCIE_MCARD
clock select GNDSRC SRCCLKT7 CLK_PCIE_MCARD <25>
R140 24_0402_5%
1

+3VS +3VS 40 38 PCIE_MCARD#1 2 CLK_PCIE_MCARD#

GNDSRC SRCCLKC7 CLK_PCIE_MCARD# <25>
R142 R141 24_0402_5%
32 GNDSATA
1

@ 10K_0402_5%
R143 R144
2

CLK_ENABLE#
A 10K_0402_5% 10K_0402_5% ICS9LP306_TSSOP64 A
1

* Internal Pull-Up Resistor

2

R145 PCI_ICH PCI_MINI ** Internal Pull-Down Resistor

1

300_0402_5%
R146 R147
1 2

@ 10K_0402_5% @ 10K_0402_5%
J1 Security Classification Compal Secret Data Compal Electronics, Inc.
2

NO SHORT PADS 2006/10/26 2006/07/26 Title

Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
Size Document Number Rev
*High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz
High:Pin44/45 = CLKREQ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.5
*Low:Pin44/45 = CPUCLK2_ITP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3491P
Date: Tuesday, March 20, 2007 Sheet 15 of 47
5 4 3 2 1
 A B C D E

CRT CONNECTOR +2.5VS

1
D5 D6 D7

1 1
DAN217_SC59DAN217_SC59DAN217_SC59

3
CRT_VCC
12/26
@ @ @

JP6
6
11
CRT_RED L4 1 2 BK2125LL121_0805 CRTL_R 1
<9> CRT_RED
7
SMBDAT 12
CRT_GRN L5 1 2 BK2125LL121_0805 CRTL_G 2
<9> CRT_GRN
8
13
CRT_BLU L6 1 2 BK2125LL121_0805 CRTL_B 3
<9> CRT_BLU
9

1
1 1 1 1 1 1 14 16
+5VS C195 C196 C197 C198 C199 C200 4 17
R148 R149 R150 10
75_0402_1% 75_0402_1% 75_0402_1% SMBCLK 15
2 2 2 2 2 2
5

2
5

U5 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J22P_0402_50V8J SUYIN_070912FR015S207CR

L7
P

OE#

HSYNC 2 4 R151 2 1 0_0402_5% 1 2 CRT_HSYNCRFL

<9> HSYNC A Y FBMA-L11-160808-800LMT_0603
G

74AHCT1G125GW_SOT353-5 L8
3

R152 2 1 0_0402_5% 1 2 CRT_VSYNCRFL

1 FBMA-L11-160808-800LMT_0603

2 C201 2
+5VS
0.1U_0402_16V4Z
2
1 1
5

2
U6 C202 C203
D8 D9
P

OE#

VSYNC 2 4 10P_0402_50V8J 10P_0402_50V8J

<9> VSYNC A Y 2 2
G

74AHCT1G125GW_SOT353-5 @ DAN217_SC59 @ DAN217_SC59

3

1
+5VS +5VS
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1
C1483
C1482

2 2

+3VS
+5VS R_CRT_VCC CRT_VCC
C1482 close to U6,
C1483 close to JP6 D10 F1
2 1 1 2
3 3

1
RB411D_SOT23 1A_6VDC_MINISMDC110
1 R153 R154
R155
0119 HSYNC、VSYNC refernece +5VS C205 2.2K_0402_5% 2.2K_0402_5%
0.1U_0402_16V4Z R156 4.7K_0402_5%

2
2 Q3
2N7002_SOT23
4.7K_0402_5%
SMBDAT CRT_SMBDAT

S
1 3 CRT_SMBDAT <9>

Q4

G
2
2N7002_SOT23

SMBCLK CRT_SMBCLK

S
1 3 CRT_SMBCLK <9>

G
2
1 1
C206 C207

220P_0402_25V8K 220P_0402_25V8K
2 2

+3VS

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 16 of 47
A B C D E
 5 4 3 2 1

LVDS CONN +LCDVDD

1 1
LCD/PANEL BD. CONN.
C208 C209 +LCDVDD
+LCDVDD +3VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z +5VALW
2 2

S
1 3

D
R157

2
Q5
100_0402_5% R158 SI2301BDS_SOT23

G
2
D D
47K_0402_5%
LVDS connector

1
1
D
Q6 2
JP7 2N7002_SOT23 G
S

3
INVPWR_B+ 1 2 LVDSA2+ LVDSA2+ <9> Q7 1 1
3 4 R159

1
LVDSA2- D C211
5 6 LVDSA2- <9> C212 C210
7 8 <9> ENAVDD 1 2 2
LVDSA1+ LVDSA1+ <9> G 4.7U_0805_10V4Z 4.7U_0805_10V4Z
+LCDVDD 9 10 LVDSA1- 2N7002LT1G_SOT23 0.047U_0402_16V7K 2 2
S

3
11 12 LVDSA1- <9> 47K_0402_5%

2
+3VS 13 14 2
LVDSA0+ +3VS R2247 C213
15 16 LVDSA0+ <9>
LVDSBC+ LVDSA0- 100K_0402_5%
<9> LVDSBC+ 17 18 LVDSA0- <9>
LVDSBC- 0.1U_0402_16V4Z
<9> LVDSBC- 19 20 1
LVDSAC+

1
LVDSB0+ 21 22 LVDSAC- LVDSAC+ <9> R2189
<9> LVDSB0+ 23 24 LVDSAC- <9>
LVDSB0- 1.8K_0603_1%
<9> LVDSB0- 25 26 INVTPWM
27 28
C214

C215

C216

LVDSB1+ DISPLAYOFF#
<9> LVDSB1+ 29 30
LVDSB1- DAC_BRIG DAC_BRIG
<9> LVDSB1- 31 32 LCD_CLK 12/28
33 34

1
LVDSB2+ LCD_DAT LCD_CLK <9>
<9> LVDSB2+ 35 36 LCD_DAT <9>
LVDSB2-
<9> LVDSB2- 37 38
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
R2190
39 40 1K_0402_1% @ R160
1
1

1
ACES_88107-4000G 1 2
<30> INV_PWM

2
CONN@
@ 0_0402_5% +3VS
11/21
2

2
2

C217

C218
C C

5
U7

P
2 4 INVTPWM
<9> BKLT_CTL A Y

G
@ NC7SZ14M5X_SOT23-5

3
2 1
R162 @ 100K_0402_5%

R161
1 2
B+ INVPWR_B+ 0_0402_5%

L9 1 2 0_0805_5%

@ L10
1 2 +3VS
FBMA-L11-201209-221LMA30T_0805

2
R163
3.3K_0402_5%

1
@ R166
1 2 DISPLAYOFF#
<9,30> ENABLT DISPLAYOFF# <30>
0_0402_5%

+3VS
B B

5
U29 @
1

P
B
Y 4
<30,32> LID_SW# 2 A

G
TC7SH08FU_SSOP5

3
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 17 of 47
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

R167 1 2 8.2K_0402_5% PCI_DEVSEL#

R168 1 2 8.2K_0402_5% PCI_STOP#

R169 1 2 8.2K_0402_5% PCI_TRDY#

R170 1 2 8.2K_0402_5% PCI_FRAME# U8B +3VS

<24> PCI_AD[0..31]
PCI_AD0 E18 D7 PCI_REQ0#
R171 1 AD0 REQ0#
2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 AD1 GNT0# E7

5
PCI_AD2 A16 C16 PCI_REQ1# U30 @
R172 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16 PCI_PCIRST# 1

P
PCI_AD4 AD3 GNT1# PCI_REQ2# B PCI_RST#
E16 AD4 REQ2# C17 PCI_REQ2# <24> Y 4 PCI_RST# <24>
R173 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT2# 2
AD5 GNT2# PCI_GNT2# <24> A

G
PCI_AD6 E17 E13 PCI_REQ3#
R174 1 PCI_PERR# PCI_AD7 AD6 REQ3#
2 8.2K_0402_5% A17 F13 TC7SH08FU_SSOP5

3
PCI_AD8 AD7 GNT3# PCI_REQ4# R177
A15 AD8 REQ4# / GPIO22 A13
R175 1 2 8.2K_0402_5% PCI_REQ4# PCI_AD9 C14 A14 ICH_GPIO48 0_0402_5%
PCI_AD10 AD9 GNT4# / GPIO48 PCI_REQ5#
E14 AD10 GPIO1 / REQ5# C8 2 1
R176 1 2 8.2K_0402_5% PCI_REQ3# PCI_AD11 D14 D8 GNT5#
PCI_AD12 AD11 GPIO17 / GNT5#
B12 AD12
R2228 1 2 8.2K_0402_5% ICH_GPIO48 PCI_AD13 C13 B15 PCI_CBE#0 +3VS
AD13 C/BE0# PCI_CBE#0 <24>
PCI_AD14 G15 C12 PCI_CBE#1
AD14 C/BE1# PCI_CBE#1 <24>
PCI_AD15 G13 D12 PCI_CBE#2
AD15 C/BE2# PCI_CBE#2 <24>

5
PCI_AD16 E12 C15 PCI_CBE#3 U31 @
AD16 C/BE3# PCI_CBE#3 <24>
PCI_AD17 C11 PCI_PLTRST# 1

P
PCI_AD18 AD17 PCI _IRDY# B PLT_RST#
C
Change to RP before SI phase D11 AD18 IRDY# A7 PCI_IRDY# <24> Y 4 PLT_RST# <7,20,22,24,25,30,31> C
PCI_AD19 A11 E10 PCI_PAR 2
AD19 PAR PCI_PAR <24> A

G
PCI_AD20 A10 B18 PCI_PCIRST#
PCI_AD21 AD20 PCIRST# PCI_DEVSEL# TC7SH08FU_SSOP5
F11 A12 PCI_DEVSEL# <24>

3
+3VS PCI_AD22 AD21 DEVSEL# PCI_PERR#
F10 AD22 PERR# C9 PCI_PERR# <24>
PCI_AD23 E9 E11 PCI_PLOCK# R184
PCI_AD24 AD23 PLOCK# PCI_SERR# 0_0402_5%
D9 AD24 SERR# B10 PCI_SERR# <24,30>
R178 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP# 2 1
AD25 STOP# PCI_STOP# <24>
PCI_AD26 A8 F14 PCI_TRDY#
AD26 TRDY# PCI_TRDY# <24>
R179 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME#
AD27 FRAME# PCI_FRAME# <24>
PCI_AD28 C7
R180 1 PCI_PIRQC# PCI_AD29 AD28 PCI_PLTRST#
2 8.2K_0402_5% B6 AD29 PLTRST# C26
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH <15>
R181 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19
AD31 PME#
R182 1 2 8.2K_0402_5% PCI_PIRQE#

R183 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3

Interrupt I/F G8 PCI_PIRQE#
PCI_PIRQB# PIRQA# GPIO2 / PIRQE# PCI_PIRQF#
B4 PIRQB# GPIO3 / PIRQF# F7
R185 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQC# C5 F8 PCI_PIRQG#
<24> PCI_PIRQC# PIRQC# GPIO4 / PIRQG#
PCI_PIRQD# B5 G7 PCI_PIRQH#
R186 1 PCI_PIRQH# PIRQD# GPIO5 / PIRQH#
2 8.2K_0402_5%

R187 1 2 8.2K_0402_5% PCI_REQ0# AE5

MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R188 1 2 8.2K_0402_5% PCI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R189 1 2 8.2K_0402_5% PCI_REQ2# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# <7>
R190 1 2 8.2K_0402_5% PCI_REQ5#
ICH7_BGA652~D
12/27
B B

Place closely pin A9

CLK_PCI_ICH

2
R191

@ 10_0402_5%

1
GNT5# and GNT4# have internal pull high 20K C219
1
GNT5#
Boot BIOS destination @ 8.2P_0402_50V
2
1

GNT5# GNT4# R1290

1K_0402_5%
0 1 SPI@ (Default)
2

1 0 PCI@
A A

1 1 LPC@
The pad must be placed on PCB easily
contact space for BIOS team setting.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 18 of 47
5 4 3 2 1
 5 4 3 2 1

C220
1 2 ICH_RTCX1
15P_0402_50V8J

1
3

4
R192
Y2
10M_0402_5%
U8A
LPC_AD[0..3] <25,30,31>

2
Change to LAN power plane 12/11 32.768KHZ_12.5P_MC-146

RTC
AB1 AA6 LPC_AD0
C221 ICH_RTCX2 RTXC1 LAD0 LPC_AD1
1 2 AB2 RTCX2 LAD1 AB5
15P_0402_50V8J AC4 LPC_AD2
D R193 1 ICH_RTCRST# AA3 LAD2 LPC_AD3 D
+RTCVCC 2 RTCRST# LAD3 Y6

LPC
20K_0402_5%
R194
ICH_INTVRMENW4 AC3 LPCRQ0# Delete(For SIO Request pin) 11/20
JOPEN1 +3VS +3VALW SM_INTRUDER#Y5 INTVRMEN LDRQ0#
+RTCVCC 1 2 INTRUDER# LDRQ1# / GPIO23 AA5 PAD T15
1 2 1M_0402_5%
U10 AB3 LPC_FRAME#
LFRAME# LPC_FRAME# <25,30,31>
SHORT PADS 8 1 EEP_CS W1
VCC CS EEP_SK EE_CS
7 NC SK 2 Y1 EE_SHCLK 2 1 R195 10K_0402_5% +3VS
1

1
C222 6 3 EEP_DOUT Y2 AE22 GATEA20
NC DI EE_DOUT A20GATE GATEA20 <30>

LAN
1U_0603_10V4Z 5 4 EEP_DIN W3 AH28 H_A20M#
GND DO EE_DIN A20M# H_A20M# <4>

CPU
1 2
AT93C46-10SI-2.7_SO8 LAN_JCLK V3 AG27 H_CPUSLP_R# PAD T16
<23> LAN_JCLK LAN_CLK CPUSLP#
R2230 @
2

R2231 LAN_RSTSYNC U3 AF24 DPRSLP# R196 2 1 0_0402_5%

<23> LAN_RSTSYNC LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# <4,40>
0_0402_5% 0_0402_5% AH25 DPSLP# R197 2 1 0_0402_5%
TP2 / DPSLP# H_DPSLP# <4>
1 <23> LAN_RXD0 LAN_RXD0 U5 R198 2 1 56_0402_5% +VCCP
C223 LAN_RXD1 LAN_RXD0 H_FERR#
<23> LAN_RXD1 V4 LAN_RXD1 FERR# AG26 H_FERR# <4>
<23> LAN_RXD2 LAN_RXD2 T5
0.1U_0402_16V4Z LAN_RXD2 H_PW RGOOD
GPIO49 / CPUPWRGD AG24 H_PWRGOOD <4>
2 LAN_TXD0
<23> LAN_TXD0 U7 LAN_TXD0
LAN_TXD1 V6 AG22 H_IGNNE#
<23> LAN_TXD1 LAN_TXD1 IGNNE# H_IGNNE# <4>
12/26 LAN_TXD2 V7 AG21 FWH_INIT# Delete 11/20
<23> LAN_TXD2 LAN_TXD2 INIT3_3V#
AF22 H_INIT#
INIT# H_INIT# <4> +3VS +VCCP
R2210 H_INTR
EMI 33_0402_5% INTR AF25 H_INTR <4>

AC-97/AZALIA
<26> ACZ_BITCLK AC97_BITCLK 1 2 U1 R200 2 1 10K_0402_5%
AC97_SYNC ACZ_BCLK KB_RST#
<26> ACZ_SYNC R6 ACZ_SYNC RCIN# AG23 KB_RST# <30>
AC97_BITCLK

1
33_0402_5% 2 R201 1 AC97RST# R5 AF23 H_SMI#
<26> ACZ_RST# ACZ_RST# SMI# H_SMI# <4>
2

AH24 H_NMI R202

NMI H_NMI <4>
R199 AC97_SDIN0 T2
<26> ACZ_SDIN0 ACZ_SDIN0
10_0402_5% T3 ACZ_SDIN1 STPCLK# AH22 2 1 H_STPCLK# H_STPCLK# <4>
56_0402_5%
C R203 0_0402_5% C
@ T1

2
ACZ_SDIN2 THRMTRIP_ICH#
AF26 1 2 H_THERMTRIP# <4,7>
1

AC97_SDOUT THERMTRIP# R204 24.9_0402_1%

<26> ACZ_SDOUT 1 2 T4 ACZ_SDOUT
1 R205 33_0402_5%
AH17 PD_A0 Place close to ICH7
DA0 PD_A0 <22>
C224 +3VS R2213 2 1 10K_0402_5% AF18 AE17 PD_A1
SATALED# DA1 PD_A1 <22>
10P_0402_25V8K 12/26 AF17 PD_A2
2 DA2 PD_A2 <22>
@
SATA_RXN0_C AF3 AE16 PD_CS#1
<22> SATA_RXN0_C SATA0RXN DCS1# PD_CS#1 <22>
SATA_RXP0_C AE3 AD16 PD_CS#3
<22> SATA_RXP0_C SATA0RXP DCS3# PD_CS#3 <22>
SATA_TXN0_C AG2
<22> SATA_TXN0_C SATA0TXN

SATA
SATA_TXP0_C AH2
<22> SATA_TXP0_C SATA0TXP
AB15 PD_D0
DD0 PD_D1
AF7 SATA2RXN DD1 AE14
AE7 AG13 PD_D2
SATA2RXP DD2 PD_D3
AG6 SATA2TXN DD3 AF13
AH6 AD14 PD_D4
+3VS SATA2TXP DD4 PD_D5
DD5 AC13
<15> CLK_PCIE_SATA# CLK_PCIE_SATA# AF1 AD12 PD_D6
CLK_PCIE_SATA AE1 SATA_CLKN DD6 PD_D7
<15> CLK_PCIE_SATA SATA_CLKP DD7 AC12
AE12 PD_D8
4.7K_0402_5% 2 DD8
1 R207 PD _IORDY R209 AH10 SATARBIASN DD9 AF12 PD_D9
8.2K_0402_5% 2 1 R208 PD_IRQ 1 2 AG10 AB13 PD_D10
SATARBIASP DD10 PD_D11
DD11 AC14
24.9_0402_1% AF14 PD_D12
DD12 PD_D13
DD13 AH13
PD_D14
+3VALW +RTCVCC PD _IORDY AG16
IDE DD14 AH14
AC15 PD_D15
<22> PD_IORDY IORDY DD15
PD_IRQ AH16
<22> PD_IRQ IDEIRQ
PD_DACK# AF16
<22> PD_DACK# DDACK#
PD_IOW# AH15 AE15 PD_DREQ
<22> PD_IOW# DIOW# DDREQ PD_DREQ <22>
1

PD_IOR# AF15
B <22> PD_IOR# DIOR# B
R210 R211

@ 332K_0402_1% 332K_0402_1% ICH7_BGA652~D

2

ICH_INTVRMEN PD_D[0..15]
PD_D[0..15] <22>
1

R212

@ 0_0402_5%
2

LAN_TXD0
LAN_TXD1 +3VL
LAN_TXD2 +RTCVCC JP8
33_0402_5%
2

R2197 2
33_0402_5%

33_0402_5%

D11
R213
3 + -
R2195

1R2196

1 2 1
1 RTC_R 1
2 2 1 2
C225 R214 W=20mils + -
1

100_0402_5% DAN202U_SC70 1K_0402_5% BATT1 ZZZ1

1 1 1
1U_0603_10V4Z W=20mils
2
C1447

33P_0402_50V8J

C1448

33P_0402_50V8J

C1449

33P_0402_50V8J

A A

2 2 2 SUYIN_060003FA002TX00NL~D

CR2032 RTC BATTERY PCB_MB_rev01

11/21 BATT@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 19 of 47
5 4 3 2 1
 5 4 3 2 1

Place closely pin B2 Place closely pin AC1

CLK_48M_ICH CLK_14M_ICH
+3VALW +3VALW

1
R217,R218 change from 2.2Kohm to R215 R216
10Kohm when Q23,Q24,R206,R204 stuffed.

2
R217 R218 @ 10_0402_5% @ 10_0402_5%
R219 R220

2
4.7K_0402_5% 4.7K_0402_5% U8C
10K_0402_5% 10K_0402_5% @ R221 1 1
ICH_SMBCLK 1 2 0_0402_5% ICH_SMB_CLK C22 AF19 C226 C227

1
D ICH_SMBDATA ICH_SMB_DATA SMBCLK GPIO21 / SATA0GP D
1 2 0_0402_5% B22 SMBDATA GPIO19 / SATA1GP AH18

SMB
SATA
GPIO
@ R222 LINKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
+3VS ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 2
ICH_SMLINK1 A25 R223 100_0402_5%
SMLINK1
+3VALW

1
R226 AC1 CLK_14M_ICH
CLK14 CLK_14M_ICH <15>

Clocks
R224 R225 1 2 I CH_RI# A28 B2 CLK_48M_ICH
RI# CLK48 CLK_48M_ICH <15>
8.2K_0402_5%
2.2K_0402_5% 2.2K_0402_5% SB_SPKR A19
<26> SB_SPKR SPKR
Q10 LPC_PD# A27 C20 ICH_SUSCLK T17 PAD
<30> LPC_PD#
2

2
RHU002N06_SOT323 XDP_DBRESET# SUS_STAT# SUSCLK
<4> XDP_DBRESET# A22 SYS_RST#

SYS
B24 SLP_S3#
SLP_S3# SLP_S3# <30,33,39>
S

D
ICH_SMBDATA 3 1 ICH_SMB_DATA PM_BMBUSY# AB18 D23 SLP_S4#
<4,13,14,15,25> ICH_SMBDATA <7> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S4# <38>
F22 SLP_S5#
SLP_S5# SLP_S5# <33,38>

D
ICH_SMBCLK 3 1 ICH_SMB_CLK OCP# B23 R227 R228
<4,13,14,15,25> ICH_SMBCLK <4,30,42> OCP# GPIO11 / SMBALERT# PM_POK 2 10K_0402_5% 8.2K_0402_5%
G
2 PWROK AA4 1

POWER MGT
Q11 H_STP_PCI# AC20 2 1 +3VALW
<15> H_STP_PCI# GPIO18 / STPPCI#

GPIO
RHU002N06_SOT323 H_STP_CPU# DPRSLPVR
G
<15> H_STP_CPU# AF21 AC22 DPRSLPVR <7,40>
2
GPIO20 / STPCPU# GPIO16 / DPRSLPVR D12
+3VS +3VS
A21 C21 ICH_LOW_BAT# 2 1
GPIO26 TP0 / BATLOW# LOW_BAT# <30>
@ 10K_0402_5% PAD T18 B21 C23 ON/OFFBTN# CH751H-40_SC76
GPIO27 PWRBTN# ON/OFFBTN# <32>
R230 1 2 THERM_SCI# PAD T19 E23 R229
GPIO28 LAN_RST_R# 10K_0402_5%
LAN_RST# C19
10K_0402_5% R231 PM_CLKRUN# AG18 2 1 +3VL
<24,30> PM_CLKRUN# GPIO32 / CLKRUN# PM_RSMRST#
R234 1 2 SIRQ 1K_0402_5% Y4
RSMRST# PM_RSMRST# <24,30>
+3VALW 1 2 AC19 R233 10K_0402_5%
8.2K_0402_5% GPIO33 / AZ_DOCK_EN#
U2 GPIO34 / AZ_DOCK_RST# 1 2
R235 1 2 PM_CLKRUN# LAN_RST_R# 1 2 PLT_RST# <7,18,22,24,25,30,31>
ICH_PCIE_WAKE# F20 E20 T20 PAD R2232 0_0402_5%
<25> ICH_PCIE_WAKE# WAKE# GPIO9
10K_0402_5% SIRQ AH21 A20
C <24,30> SIRQ SERIRQ GPIO10 C
R242 1 2 LID_OUT# <4> THERM_SCI#
THERM_SCI# AF20 THRM# GPIO12 F19 1 2 LAN_RST# <30>
E19 LID_OUT# R2233 @ 0_0402_5%
GPIO13 LID_OUT# <30>
PWROK_ICH7 AD22 R4
VRMPWRGD GPIO14
GPIO15 E22 T21 PAD
12/05 Change to +3VS R3 XMIT_OFF# 12/26
GPIO24 XMIT_OFF# <25,31>
RUNSCI_EC# AC21 D20
+3VALW <30> RUNSCI_EC#
AC18
GPIO6 GPIO GPIO25
AD21
GPIO7 GPIO35 / SATAREQ#
E21 GPIO8 GPIO38 AD20
10K_0402_5% AE20 T22
R237 1 GPIO39
2 LINKALERT#
ICH7_BGA652~D PAD
10K_0402_5%
R238 1 2 XDP_DBRESET# <7,40> VGATE_INTEL R239 1 2 0_0402_5% PWROK_ICH7

10K_0402_5% R240
R232 need be removed when ICH7M ES2 samples used,
<7,30> PM_POK 1 2 @ 0_0402_5%
R241 1 2 OCP# U8D but need be stuffed when ICH7M ES1 samples used.
F26 V26 DMI_RXN0
PERn1 DMI0RXN DMI_RXN0 <7>
F25 V25 DMI_RXP0
PERp1 DMI0RXP DMI_RXP0 <7>

DIRECT MEDIA INTERFACE

E28 U28 DMI_TXN0 DPRSLPVR 2 1
PETn1 DMI0TXN DMI_TXN0 <7>
E27 U27 DMI_TXP0 R232
PETp1 DMI0TXP DMI_TXP0 <7>
@ 100K_0402_5%
PCIE_RXN2 H26 Y26 DMI_RXN1
<25> PCIE_RXN2 PERn2 DMI1RXN DMI_RXN1 <7>
PCIE_RXP2 H25 Y25 DMI_RXP1
<25> PCIE_RXP2 PERp2 DMI1RXP DMI_RXP1 <7>
<25> PCIE_TXN2 WLAN@ 0.1U_0402_16V4Z 2 1 C228 PCIE_C_TXN2 G28 W28 DMI_TXN1
PETn2 DMI1TXN DMI_TXN1 <7>
<25> PCIE_TXP2 WLAN@ 0.1U_0402_16V4Z 2 1 C229 PCIE_C_TXP2 G27 W27 DMI_TXP1
PETp2 DMI1TXP DMI_TXP1 <7>

PCI-EXPRESS
K26 AB26 DMI_RXN2
PERn3 DMI2RXN DMI_RXN2 <7>
12/26 K25 AB25 DMI_RXP2
PERp3 DMI2RXP DMI_RXP2 <7>
J28 AA28 DMI_TXN2
PETn3 DMI2TXN DMI_TXN2 <7>
J27 AA27 DMI_TXP2
PETp3 DMI2TXP DMI_TXP2 <7>
M26 AD25 DMI_RXN3 USB_OC#0 1 2
B PERn4 DMI3RXN DMI_RXN3 <7> USB_OC# <29> B
M25 AD24 DMI_RXP3 R243 @ 0_0402_5%
PERp4 DMI3RXP DMI_RXP3 <7>
L28 AC28 DMI_TXN3 USB_OC#1 1 2
PETn4 DMI3TXN DMI_TXN3 <7>
L27 AC27 DMI_TXP3 R244 @ 0_0402_5%
PETp4 DMI3TXP DMI_TXP3 <7>
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# <15>
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH <15>
N28 PETn5
N27 C25 R245 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 PERn6
R246 should be placed T24 F1 USB20_N0
PERp6 USBP0N USB20_N0 <29>
R28 F2 USB20_P0
less than 100 mils from U8 PETn6 USBP0P USB20_P0 <29>
R27 G4 USB20_N1
PETp6 USBP1N USB20_N1 <29>
47_0402_5% G3 USB20_P1
USBP1P USB20_P1 <29>
<31> SPI_CLK SPI_CLK R246 1 2 R2 H1
SPI_CS# SPI_CLK USBP2N +3VALW
<31> SPI_CS# P6 SPI_CS# SPI USBP2P H2 12/26
P1 SPI_ARB USBP3N J4
47_0402_5% RP33
USBP3P J3
<31> SPI_SI SPI_SI R2219 1 2 P5 K1 USB_OC#1 1 8
SPI_SO SPI_MOSI USBP4N USB_OC#3
<31> SPI_SO P2 SPI_MISO USBP4P K2 2 7
L4 USB_OC#0 3 6
USBP5N USB_OC#5
USBP5P L5 4 5
USB_OC#0 D3 M1
USB_OC#1 OC0# USBP6N 10K_1206_8P4R_5%
C4 OC1# USB USBP6P M2
USB_OC#2 D5 N4
USB_OC#3 OC2# USBP7N RP34
D4 OC3# USBP7P N3
USB_OC#4 E5 USB_OC#2 1 8
+3VALW USB_OC#5 OC4# R248 22.6_0402_1% USB_OC#4
C3 OC5# / GPIO29 2 7
USB_OC#6 A2 D2 USBRBIAS 1 2 USB_OC#6 3 6
USB_OC#7 OC6# / GPIO30 USBRBIAS# USB_OC#7
B3 OC7# / GPIO31 USBRBIAS D1 4 5
1 2SPI_CS# Within 500 mils
R249 10K_0402_5% 10K_1206_8P4R_5%
A ICH7_BGA652~D A
1 2 SPI_SI
R250 10K_0402_5%

1 2 SPI_SO
R251 10K_0402_5%

R249,R250 and R251 should

be placed close to U8.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 20 of 47
5 4 3 2 1
 5 4 3 2 1

+VCCP
U8F U8E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 1 B8 VSS[3] VSS[101] R12
Change 150uF to 220uF 12/04 +1.5VS Vcc1_05[4] L16 1 1
+ +
B11 VSS[4] VSS[102] R13
ICH_V5REF_SUS F6 L17 C232 C233 C231 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z @ 330U_D2E_2.5VM_R9 D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2 2

220U_D2_2VM_R9
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS AB22 P11 C230 B28 R18
1 1 1 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]
+ C235 C236 C237 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z 220U_D2_2VM_R9 VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
1

AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13

2 2 2 2

C234
R252 D13 AC25 U11 12/25 D10 T14
Vcc1_5_B[7] Vcc1_05[13] VSS[13] VSS[111]
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
100_0402_5% CH751H-40_SC76 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VCCSUSHDA R2234 VSS[15] VSS[113]
AD27 V12 1 2 @ 0_0402_5% +3VS D21 T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
ICH_V5REF_RUN Place closely pin D26 V16 R2235 1 2 0_0402_5% E1 U12
Vcc1_5_B[12] Vcc1_05[18] +3VALW VSS[18] VSS[116]
1 1 D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
C238 C239 @ D28,T28,AD28. D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
0.1U_0402_16V4Z 0.1U_0402_16V4Z E25 U6 +3VS E15 U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[23] VSS[120]
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 VCCSUSHDA +VCCP C240 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C241 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VALW H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

K22 AB20 1 C242 G6 V28

R253 D14 Vcc1_5_B[26] Vcc3_3[5] C243 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% CH751H-40_SC76 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C244 VSS[36] VSS[133]
M22 AG12 G21 W26
2

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 VSS[38] VSS[135] Y3
N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C
1 N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
C245 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
0.1U_0402_16V4Z R22 B16 1 1 1 H5 AA24
2 Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C246

C247

C248
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C249 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C252

C253
V23 A24 C250 C251 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VALW M4 VSS[62] VSS[159] AD4
R254 R255 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C254 C255 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0.5_0805_1% 0_0805_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C256

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C257

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C258 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C259

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C260

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

2 C262 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C261 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T23 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD T24 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T25 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3VALW Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C263 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C264 P15 AH3
0.1U_0402_16V4Z C265 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T26 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_ Y7 0.1U_0402_16V4Z
T27 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
0_0402_5% R2236 VCCLAN3_3 VccSus3_3/VccLAN3_3[3]
+3VS 2 1 W7 VccSus3_3/VccLAN3_3[4]
0_0402_5% @ 2 1 R2237 1 ICH7_BGA652~D
+3VALW
C266
A A

12/25 0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 21 of 47
5 4 3 2 1
 A B C D E

JP9

GND 1
2 SATA_TXP0
SATA CONN A+
A- 3 SATA_TXN0
GND 4
5 SATA_RXN0
B- SATA_RXP0
B+ 6
GND 7
1 C267 3900P_0402_50V7K 1
SATA_TXN0_C 1 2 SATA_TXN0 8
<19> SATA_TXN0_C V33
V33 9
C268 3900P_0402_50V7K 10
SATA_TXP0_C SATA_TXP0 V33
<19> SATA_TXP0_C 1 2 GND 11
GND 12
GND 13
V5 14
15
Near ICH7(U26) side. V5
V5 16 +5VS
GND 17
Reserved 18
GND 19 1 1 1 1
20 C269 C270 C271 C1450
V12 + @
V12 21

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V12 22
2 2 2

330U_D2E_2.5VM_R9
C272 3900P_0402_50V7K
SATA_RXN0_C SATA_RXN0 2
<19> SATA_RXN0_C 1 2
CONN@ OCTEK_HDD-22SC1G_44P_RV
C273 3900P_0402_50V7K
SATA_RXP0_C 1 2 SATA_RXP0
<19> SATA_RXP0_C

11/21
Near Device(JP45) side.

2 2

CD-ROM Connector

PD_D[0..15]
PD_D[0..15] <19>

12/26
JP10
1 2
PLT_RST# 3 4 +5VS
<7,18,20,24,25,30,31> PLT_RST# 2 R256 1 33_0402_5% 5 6
PD_D8
PD_D7 PD_D9
PD_D6 7 8 PD_D10
3 PD_D5 9 10 PD_D11
Placea caps. near ODD CONN. 3
PD_D4 11 12 PD_D12
PD_D3 13 14 PD_D13
PD_D2 15 16 PD_D14
PD_D1 17 18 PD_D15
19 20

0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z
PD_D0 PD_DREQ
21 22 PD_DREQ <19>
PD_IOR# 1 1 1 1
23 24 PD_IOR# <19>

C1451
PD_IOW#
<19> PD_IOW# 25 26

C1452

C1453
PD _IORDY PD_DACK# R257 C1454
<19> PD_IORDY 27 28 PD_DACK# <19> 10U_0805_10V4Z
PD_IRQ 100K_0402_5%
<19> PD_IRQ 29 30 2 2 2 2
PD_A1 PDIAG# 1 2
<19> PD_A1 31 32 +5VS
PD_A0 PD_A2
<19> PD_A0 33 34 PD_A2 <19>
PD_CS#1 PD_CS#3
<19> PD_CS#1 35 36 PD_CS#3 <19>
IDE_ACT#
37 38
39 40
+5VS 41 42 +5VS
43 44 2 1
45 46 11/21
PRI_CSEL C274
GND
GND

47 48 0.1U_0402_16V4Z
49 50
2

OCTEK_CDR-50TA1
53
54

R258
470_0402_5%
1

+5VS
R259
IDE_ACT# 1 2
4 4

10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 22 of 47
A B C D E
 5 4 3 2 1

close to U12chip(Intel rule) close to U12chip(Intel rule) close to U13 RJ45

C275
RDP TDP RDP
2 1

2
R261 R262 R260
@ 110_0402_1% 68P_0402_50V8K
110_0402_1% 110_0402_1%

JP11

1
D LAN_RXD0 RDN TDN RDN @ R263 ACTLED# D
12 Amber LED-
LAN_RXD1 300_0603_5%
LAN_RXD2 1 2 11
+3VALW Amber LED+
2 SHLD4 16

2
33P_0402_50V8J 33_0402_5%

33_0402_5%
R267 8
R266 300_0603_5% PR4-
SHLD3 15
R264

R265
33_0402_5% +3VS 1 2 7 PR4+
MDO1- 6
1

1
PR2-
1 1 1
33P_0402_50V8J
Support wake on LAN R263,R269 5 PR3-
C276

C277

C278 Don't Support wake on LAN R267、R268

33P_0402_50V8J 4 PR3+
2 2 2
MDO1+ 3 PR2+
R268 MDO0- 2
300_0603_5% PR1-
SHLD2 14
+3VS 1 2 MDO0+ 1
+3VLAN PR1+
SHLD1 13
@ R269 LINK_LED100# 10
300_0603_5% Green LED-
2 1 15 mil 1 2 9
+3VS +3VALW Green LED+
L11
FBMA-L11-160808-601LMT 0603 SUYIN_100073FR012S100ZL
C281
CONN@
1 2
+3VALW 2 1
@ L20
FBMA-L11-160808-601LMT 0603 68P_0402_50V8K

C +3VLAN C
+3VLAN
12/28

2
U12 R271
@ 0_0402_5%
U13
1 10 TDP

1
VCC TDP TDN TDN MDO0- R272 C282
25 VCC TDN 11 8 TD- TX- 9
10U_0805_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 1 36 15 RDP TDP 7 10 MDO0+ 75_0402_5%

VCCP RDP RDN TD+ TX+ MCT0 RJ45_GND 2
40 VCCP RDN 16 6 CT CT 11 2 1 1
C1470

C1471

C1472

C1473

C1474

C1475

2 VCCA
+3VLAN 7 31 1000P_1206_2KV7K
2 2 2 2 2 2 VCCA2 SPDLED# R2208 1 ACTLED# MCT1
9 VCCT ACTLED# 32 2 0_0603_5% 3 CT CT 14 2 1
12 27 R2207 1 2 0_0603_5% LINK_LED100# RDN 2 15 MDO1- R273
VCCT LILED# RD- RX-
1

14 RDP 1 16 MDO1+ 75_0402_5%

VCCT RD+ RX+

2
680P_0402_50V7K

680P_0402_50V7K
C1459

0.1U_0402_16V4Z

0.1U_0402_16V4Z
17 VCCT 1 1

C1458
R2254 37 LAN_RXD2
JRXD2 LAN_RXD2 <19>

C283

C284
0_0603_5% 35 LAN_RXD1 NS0013_16P
LAN_RXD1 <19>

1
JRXD1 LAN_RXD0
19 34 LAN_RXD0 <19>
2

+3V_LAN VCCR JRXD0 LAN_RSTSYNC @ 2 2

23 VCCR JRSTSYNC 42 LAN_RSTSYNC <19>
8 45 LAN_TXD2 LAN_TXD2 <19>
VSS JTXD2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V4Z

1 1 1 13 44 LAN_TXD1 LAN_TXD1 <19>

VSS JTXD1 LAN_TXD0
18 VSS JTXD0 43 LAN_TXD0 <19>
C1476

C1477

C1478

24 39 LANJCLK 2 1 LAN_JCLK LAN_JCLK <19>

VSS JCLK R270 47_0402_5%
48 VSS
2 2 2
33 VSSP TOUT 26
38 VSSP
3 5 R274 1 2 649_0402_1%
VSSA RBIAS100
6 VSSA2
20 4 R275 1 2 619_0402_1%
B VSSR RBIAS10 B
22 VSSR
02/07 Follow 82562GT design guide

C279
28 46 LAN1_XO 1 2
ISOL_TI X1 JP12
30 ISOL_TCK
2

29 22P_0402_50V8J TIP 1
1
R277
2
200_0402_5%
21
ISOL_EXEC
TESTEN Y3
RI NG 2
1
2 RJ11
25MHZ_20P_1BG25000CK1A 1 C293 1 C294 3
470P_1808_3KV 470P_1808_3KV GND1
41 ADV10 X2 47 4 GND2
C280
1

LAN1_XI 1 2 FOX_JM74613-P2002-7F~D
82562GT_SSOP48 2 2
CONN@
22P_0402_50V8J

8/18 for EMI

JP13
RI NG
TIP 1
2
A ACES_85205-0200 A
RJ11 CABLE
@ CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
82562EZ LAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 23 of 47
5 4 3 2 1
 A B C D E

S1_VCC

1
U14
13 C295
VCC 4.7U_0805_10V4Z
VCC 12
2
6/02 9 12V VCC 11
S1_VPP S1_VCC
S1_VPP
+5V_CB

4.7U_0805_10V4Z
0.1U_0402_16V7K
1 1 1
1
10 +3V_CB +3V_CB 1
VPP 1 1
1 C296 C297 C298
5 0.1U_0402_16V7K 0.1U_0402_16V7K @ L21 C299 C300
5V 2 2 2

680P_0402_50V7K

C303
C301 4.7U_1206_25VFZ 0.1U_0402_16V4Z
0.1U_0402_16V7K
6/02 6 5V
1 1
1 2 +3VALW 2 2

1
2 VCCD0# 0_0805_5%
VCCD0 1
2 VCCD1# C304
+3V_CB VCCD1 VPPD0 L12
15

2
VPPD0 2 2

C302
14 VPPD1 1 2
VPPD1 +3VS
0.1U_0402_16V7K
3 0_0805_5% S1_VCC
3.3V +3V_CB
1 4 3.3V
SHDN
OC 8 C306 Don't Support wake on LAN L12, L13
VPPD0 Support wake on LAN L?, L?
GND

C305 VPPD1 1 2 1 1
0.1U_0402_16V7K VCCD0#
1

2 CP-2211_SSOP16 VCCD1# +5V_CB 10U_1206_16V4Z C307 C308

7

16

R278 680P_0402_50V7K 0.1U_0402_16V7K

10K_0603_1% @ L22 2 2

126

138
122
102
74
73

72
71

44
18

90

86
50
30
14

63
1 2 +5VALW
U15
2

PCI_AD[0..31] 0_0805_5%

VCCD1#
VCCD0#

VPPD1
VPPD0

VCCP0
VCCP1

VCCSK0
VCCSK1

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

VCCI
<18> PCI_AD[0..31]
L13
1 2 S1_VCC
+5VS
PCI_AD31 3 144 S1_D10 0_0805_5% 1 2 S1_A23
PCI_AD30 AD31 CAD31/D10 S1_D9 R279 22K_0402
4 AD30 CAD30/D9 142
PCI_AD29 5 141 S1_D1 12/27 1 2 S1_WP
PCI_AD28 AD29 CAD29/D1 S1_D8 R280 22K_0402
7 AD28 CAD28/D8 140
PCI_AD27 8 139 S1_D0
PCI_AD26 AD27 CAD27/D0 S1_A0
9 AD26 CAD26/A0 129
PCI_AD25 10 128 S1_A1
2 PCI_AD24 AD25 CAD25/A1 S1_A2 2
11 AD24 CAD24/A2 127
PCI_AD23 15 124 S1_A3 S1_VCC
PCI_AD22 AD23 CAD23/A3 S1_A4
16 AD22 CAD22/A4 121
PCI_AD21 17 120 S1_A5
PCI_AD20 AD21 CAD21/A5 S1_A6
19 AD20 CAD20/A6 118

1
PCI_AD19 23 116 S1_A25
PCI_AD18 AD19 CAD19/A25 S1_A7
24 AD18 CAD18/A7 115
PCI_AD17 25 113 S1_A24 R281
+5VALW +5VALW +5VALW +5VALW +5VALW +5VALW PCI_AD16 AD17 CAD17/A24 S1_A17 47K_0402_5%
26 AD16 CAD16/A17 98
PCI_AD15 38 96 S1_IOWR#

2
AD15 CAD15/IOWR#
0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.047U_0402_16V4Z

0.047U_0402_16V4Z

PCI_AD14 39 97 S1_A9 JP14

PCI_AD13 AD14 CAD14/A9 S1_IORD#
1 2 40 AD13 CAD13/IORD# 93
PCI_AD12 41 95 S1_A11 1 35
PCI_AD11 AD12 CAD12/A11 S1_OE# S1_D3 GND GND S1_CD1#
43 AD11 CAD11/OE# 92 2 S1_D3 S1_CD1# 36
PCI_AD10 45 91 S1_CE2# S1_D4 3 37 S1_D11
2 1 AD10 CAD10/CE2# S1_D4 S1_D11
C1463

C1464

C1465

C1466

C1467

C1468

PCI_AD9 46 89 S1_A10 S1_D5 4 38 S1_D12

PCI_AD8 AD9 CAD9/A10 S1_D15 S1_D6 S1_D5 S1_D12 S1_D13
47 AD8 CAD8/D15 87 5 S1_D6 S1_D13 39
PCI_AD7 49 85 S1_D7 S1_D7 6 40 S1_D14
PCI_AD6 AD7 CAD7/D7 S1_D13 S1_CE1# S1_D7 S1_D14 S1_D15
51 AD6 CAD6/D13 82 7 S1_CE1# S1_D15 41
PCI_AD5 52 83 S1_D6 S1_A10 8 42 S1_CE2#
PCI_AD4 AD5 CAD5/D6 S1_D12 S1_OE# S1_A10 S1_CE2# S1_VS1
12/05 Follow IAT00 EMI Request 53 AD4 CAD4/D12 80 9 S1_OE# S1_VS1 43
PCI_AD3 54 81 S1_D5 S1_A11 10 44 S1_IORD#
PCI_AD2 AD3 CAD3/D5 S1_D11 S1_A9 S1_A11 S1_IORD# S1_IOWR#
55 AD2 CAD2/D11 77 11 S1_A9 S1_IOWR# 45
PCI_AD1 S1_D4 S1_A8 S1_A17
PCI_AD0
56
57
AD1 PQFP 144 CAD1/D4 79
76 S1_D3 S1_A13
12
13
S1_A8 S1_A17 46
47 S1_A18
AD0 CAD0/D3 S1_A13 S1_A18
PCI_CBE3# 12
22.2 X 22.2 X 1.60 125 S1_REG#
S1_A14
S1_WE#
14
15
S1_A14 S1_A19 48
49
S1_A19
S1_A20
<18> PCI_CBE#3 C/BE3# CC/BE3#/REG# S1_WE# S1_A20
PCI_CBE2# 27 112 S1_A12 S1_RDY# 16 50 S1_A21
<18> PCI_CBE#2 C/BE2# CC/BE2#/A12 S1_RDY# S1_A21
PCI_CBE1# 37 99 S1_A8 17 51 S1_VCC
<18> PCI_CBE#1 C/BE1# CC/BE1#/A8 S1_VCC S1_VCC S1_VCC
PCI_CBE0# 48 88 S1_CE1# 18 52
<18> PCI_CBE#0 C/BE0# CC/BE0#/CE1# S1_VPP S1_VPP S1_VPP S1_VPP
S1_A16 19 53 S1_A22
S1_RST S1_A15 S1_A16 S1_A22 S1_A23
<18> PCI_RST# 20 RST# CRST#/RESET 119 20 S1_A15 S1_A23 54
3 S1_A23 S1_A12 S1_A24 3
<18> PCI_FRAME# 28 FRAME# CFRAME#/A23 111 21 S1_A12 S1_A24 55
<18> PCI_IRDY# 29 110 S1_A15 S1_A7 22 56 S1_A25
IRDY# CIRDY#/A15 S1_A22 S1_A6 S1_A7 S1_A25 S1_VS2
<18> PCI_TRDY# 31 TRDY# CTRDY#/A22 109 23 S1_A6 S1_VS2 57
32 107 S1_A21 S1_A5 24 58 S1_RST
<18> PCI_DEVSEL# DEVSEL# CDEVSEL#/A21 S1_A5 S1_RST
33 105 S1_A20 S1_A4 25 59 S1_WAIT#
<18> PCI_STOP# STOP# CSTOP#/A20 S1_A4 S1_WAIT#
34 104 S1_A14 S1_A3 26 60 S1_INPACK#
<18> PCI_PERR# PERR# CPERR#/A14 S1_A3 S1_INPACK#
35 133 S1_WAIT# S1_A2 27 61 S1_REG#
<18,30> PCI_SERR# SERR# CSERR#/WAIT# S1_A2 S1_REG#
<18> PCI_PAR 36 101 S1_A13 S1_A1 28 62 S1_BVD2
PAR CPAR/A13 S1_INPACK# S1_A0 S1_A1 S1_BVD2 S1_BVD1
<18> PCI_REQ2# 1 REQ# CREQ#/INPACK# 123 29 S1_A0 S1_BVD1 63
2 106 S1_WE# S1_D0 30 64 S1_D8
<18> PCI_GNT2# GNT# CGNT#/WE# S1_D0 S1_D8
CLK_33M_CBS 21 108 1 2 S1_A16 S1_D1 31 65 S1_D9
<15> CLK_33M_CBS PCLK CCLK/A16 S1_D1 S1_D9
R282 33_0402_5% S1_D2 32 66 S1_D10
S1_BVD1 S1_WP S1_D2 S1_D10 S1_CD2#
59 RI_OUT#/PME# CSTSCHG/BVD1 135 33 S1_WP S1_CD2# 67
+3V_CB 70 136 S1_WP 34 68
R283 43K_0402_5% SUSPEND# CCLKRUN#/WP GND GND
69 GND GND 70
Change to DAU00 PCI Devices ID PCI_AD22 1 2 13 103 S1_A19 71 72
R284 100_0402_5% IDSEL CBLOCK#/A19 GND GND
73 GND GND 74
Cardbus ---->AD22 60 132 S1_RDY# 75 76
<18> PCI_PIRQC# MFUNC0 CINT#/READY GND GND
61 MFUNC1 77 GND GND 78
64 MFUNC2 SPKOUT 62 CBS_SPK# <26> 79 GND GND 80
65 134 S1_BVD2 81 82
<20,30> SIRQ MFUNC3 CAUDIO/BVD2 GND GND
CLK_33M_CBS 67 83 84
MFUNC4 S1_CD2# GND GND
68 MFUNC5 CCD2#/CD2# 137
1

RSVD/D14

S1_CD1#
RSVD/A18

69 75
RSVD/D2

R285 <20,30> PM_CLKRUN# MFUNC6 CCD1#/CD1# S1_VS2 FOX_WZ21131-G2-P4_LT

CVS2/VS2# 117
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

10_0402_5% PLT_RST# 1 2 66 131 S1_VS1 CONN@

<7,18,20,22,25,30,31> PLT_RST# R287 0_0402_5% VCC/GRST# CVS1/VS1#
@
2

1 PM_RSMRST# 1 2 CB1410_LQFP144
6
22
42
58
78
94
114
130

84
100
143

C309@ <20,30> PM_RSMRST# @ R2250 0_0402_5% 2 2

15P_0402_50V8J S1_D2 C310 C311
4 2 S1_A18 1000P_0402_50V7K 4
S1_D14 1 1

1000P_0402_50V7K

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CardBus CTRL CB714
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-3491P 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 24 of 47
A B C D E
 A B C D E

1 1

+3VS +1.5VS +3VALW

1 1 1 1 1 1
C312 C313 C314 C315 C316 C317
WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@
0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

Mini-Express Card---WLAN DEBUG@0_0402_5%

DEBUG@0_0402_5%
+1.5VS +3V_MINI +3VS

DEBUG@0_0402_5%
DEBUG@0_0402_5%
2 DEBUG@0_0402_5% 2
JP15 L14
ICH_PCIE_WAKE# 1 2 1 2
<20> ICH_PCIE_WAKE# 1 2
12/25 3 4 FBMA-L11-201209-102LMA10T
3 4 WLAN@
5 5 6 6
<15> CLKREQD# WLAN@ R288 1 2 CLKREQD#_MC 7 7 8 8 R289 1 2 LPC_FRAME# <19,30,31>
0_0402_5% 9 10 R290 1 2 LPC_AD3
CLK_PCIE_MCARD# 9 10 R291 LPC_AD2
<15> CLK_PCIE_MCARD# 11 11 12 12 1 2
CLK_PCIE_MCARD 13 14 R292 1 2 LPC_AD1
<15> CLK_PCIE_MCARD 13 14
15 16 R293 1 2 LPC_AD0
PLT_RST# 15 16
1 2 17 17 18 18 LPC_AD[0..3] <19,30,31>
R294 DEBUG@0_0402_5% 19 20 XMIT_OFF#
<15> CLK_DEBUG_PORT 19 20 XMIT_OFF# <20,31>
R295 0_0402_5% 21 22
PCIE_RXN2 21 22 PLT_RST# <7,18,20,22,24,30,31>
<20> PCIE_RXN2 1 2 WLAN@ PCIE_C_RXN2 23 23 24 24 +3VALW
<20> PCIE_RXP2 PCIE_RXP2 1 2 PCIE_C_RXP2 25 26 12/26
R297 0_0402_5% 25 26
27 27 28 28
WLAN@ 29 30
29 30 ICH_SMBCLK <4,13,14,15,20>
PCIE_TXN2 31 32
<20> PCIE_TXN2 31 32 ICH_SMBDATA <4,13,14,15,20>
PCIE_TXP2 33 34
<20> PCIE_TXP2 33 34
35 35 36 36
37 38 R2270
37 38
12/26 39 39 40 40 2 1WLAN@ +3VS
41 42 10K_0402_5%
41 42 @ R2263 1
43 43 44 44 2 0_0402_5% WL_LED# <31,32>
+3VL R299 1 2 DEBUG@ 0_0402_5% 45 46 R2271 1 2 0_0402_5%
45 46 WL_LED_EC# <30>
R300 1 2 DEBUG@ 0_0402_5% 47 48 WLAN@
<30,31,32> STB_LED# R301 DEBUG@ 0_0402_5% 47 48
<30,31> NUM_LED# 1 2 49 49 50 50
R302 2 DEBUG@ 0_0402_5%
<30,31> CAPS_LED# 1 51 51 52 52 Mini Card STANDOFF
53 GND1GND2 54 02/26 Add R2270 for WL_LED_EC# PU
H27 H28
MOLEX 67910-0002 52P 02/26 Add R2271 for use EC detect WLAN active HOLEA HOLEA
3 CONN@ 3

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 25 of 47
A B C D E
 A B C D E

CODEC POWER
+VDDA_CODEC

+5VS +VDDA_CODEC
U16

1
1 2 1 5 R307
1 C318 0.1U_0402_16V4Z VIN OUT
1
1
2 GND C319 10K_0402_1%
C321

2
3 4 0.1U_0402_16V4Z
SHDN# BP 2
1 2 1
APE8805A-33Y5P_SOT23-5

1
C320
0.1U_0402_16V4Z R308 1U_0603_10V4Z
11/30 Change to +5VS 2
10K_0402_1%
AUDIO CODEC C326

2
MONO_IN 1 2 MONO_IN1 2 1 MONO_INR
1U_0603_10V4Z R309 20K_0402_5%
@ R310
In order for the modem wake on ring feature to function, 1U_0603_10V4Z
C327 1 2

1
the CODEC must be powered by a rail that is not R311 C Q15
removed when the system is in standby. <24> CBS_SPK# 2 1 1 2 2 10K_0402_5%
1 B

0.1U_0402_16V4Z
560_0402_5% E 2SC2411K_SOT23 2/09 Fine tune PC Beep,

3
0.1U_0402_16V4Z
1 Delete R310

@C328
+3VS DVDD_20549 AVDD_20549 08/ 10 +VDDA_CODEC 2 C1479

1
08/ 10 L16 C Q43
2
1 2 0_0603_5% 1 2 2
L15 2 1 1 2 0_0603_5% B

2
C322 C323 C324 E 2SC2411K_SOT23

3
C325 R2256
1U_0402_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K
1 2 2 1 1K_0402_5%

1
2 2

03/10 Delete CBS de-pop circuit

45 03/20 Add CBS de-pop circuit,Change

20
31
37
3

8
U17
Q43 from FET to BJT

AVDDHP
DVDD
VDDIO

AVDD_20
AVDD_31
DVDDM

C331
R317
<20> SB_SPKR 2 1 1 2
<19> ACZ_RST# 10 29 R314 1 2 2.2K_0402_5%
RESET# MIC_BIAS_L R315 1
MIC_BIAS_R 30 2 2.2K_0402_5% 560_0402_5%
5 21 MIC_INL C329 1 2 10U_0805_10V4Z 1U_0603_10V4Z
<19> ACZ_BITCLK BIT_CLK MIC_L MIC_L <28>

1
9 22 MIC_INR C330 1 2 10U_0805_10V4Z D15
<19> ACZ_SYNC SYNC MIC_R MIC_R <28>
<19> ACZ_SDIN0 7 SDI
R316 33_0402_5% 4 35 LINEOUT_L LINE_OUTL <28>
<19> ACZ_SDOUT SDO LINEOUT_L
36 LINEOUT_R LINE_OUTR <28> @ R320 RB751V_SOD323
LINEOUT_R 10K_0402_5%

2
PORT-A_BIAS_L 33
<27> DIB_P 2 1 DIBP_C 44 DIBP PORT-A_BIAS_R 34
R318 0_0402_5% 38 PORT_A_L HP_L <28>
PORT-A_L PORT_A_R
PORT-A_R 39 HP_R <28>
<27> DIB_N 2 1 D IBN_C 43 DIBN
R319 0_0402_5% 14
PORT-B_BIAS_L
PORT-B_BIAS_R 15
PORT-B_L 23
MONO_INR 11 24
PCBEEP PORT-B_R

CD_L 17
CD_GND 18
48 SPDIF CD_R 19

ACZ_BITCLK 13 SENSE 2 1 AVDD_20549

3 EAPD# SENSE R3212 5.11K_0402_5% 3
<28,30> EAPD# 1 2 47 EAPD 1 HP_SENSE <28>
1 L17 0_0603_5% R3221 5.11K_0402_5%
2 MIC_SENSE <28>
1

C332 R323 20K_0402_5% 1 2

R325 08/ 10 1 For Vista @ R324 0_0402_5%
NC_1 VREF_HI
2 NC_2 VREF_HI 26
2
@ 100_0402_5% @ 100P_0402_25V8K 16 NC_16 VREF_LO 27 VREF_LO 1 2
28 VC_REFA R326 0_0402_5%
C333
2

RCOSC VC_REFA
VSSIO_42
VSSIO_46

DVDD_20549 2 1 41
AVSS_12
AVSS_25
AVSS_32

RCOSC
AVSSHP

1 R327 237K_0402_1% 2 1 2 1 2
DVSS

C335 @ R328 0_0402_5%

C334
1U_0402_6.3V6K 1U_0402_6.3V6K
1 2
2 1
@ 100P_0402_25V8K CX20549-12Z_LQFP48_9X9 @ R329 0_0402_5%
42
46

12
25
32
40

1 2
@ R330 0_0402_5%

08/ 10 1 2
R331 0_1206_5%

1 2
@ R332 0_1206_5%

1 2
R333 0_1206_5%
DIGITAL ANALOG
1 2
@ R334 0_1206_5%

GNDA <28>

4 4

GND GNDA

Security Classification Compal Secret Data

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
CODEC CX20468-31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 26 of 47
A B C D E
 5 4 3 2 1

RAC1_RING 5335R13-005 RING_1

MU1
CX20548 MMBD3004S MFB2
MBR1

MR3 6.81M
4 RAC1 2
RAC AGND_LSD 1 2 1
D 12 TEST
D
4 3

MRV1
@ ML1 MJ2 CONN@
MR1 6.81M Optional
5 TAC1 2
TAC
1
res_0805_681m MBR2 @
MMBD3004S MJ1
TAC1_TIP 5335R13-005 TIP_1
2
DIBN 16 11 EIC MC11 0.1uF MFB1 1
DIBN EIC cap_0402_01uf MC8 @ MC7 MC9 @ @
470 pF Omit 470 pF MJ3
MC10 0.01uF @
AGND_LSD Note: MC8 and MC9 can be optionally
populated here or behind the RJ-11
cap_0603_001uf connector.
PWR+ 15 R810 and C810 must be placed near pin 6 (RXI)
PWR and there should be no vias on the(RXI)net. AGND_LSD
<26> DIB_P GND
<26> DIB_N AVdd
MC5
0.1uF MR2
cap_0402_01uf 2 6 RXI RX1_1 MC1 0.047uF BRIDGE_CC
MC12 AVDD RXI 100.0V
GND MC3 237K
C C
150pF 0.1uF MR9 MR5 MR6 MR10
MJ4 CAP_0402_150PF
MT1 cap_0402_01uf 280 280 280 280
2 DIBN_HS 2 3 RES_1206_280RES_1206_280
RES_1206_280 RES_1206_280
1 DIBP_HS MC6
47pF BRIDGE_CC2
@ CAP_0402_47PF AGND_LSD
1 4
MODEM-SMAR DIBP 14 10 MR13 100 MQ1
DIBP EIO MMBTA42
MC13 RES_0402_100
QBASE MQ3 MQ4
150pF 9 EIF MMBTA42 MMBTA42
CAP_0402_150PF EIF @
MR8
DVdd 1 8 TXO MQ2 56 MR11 MR12
DVDD TXO MMBTA42 5% 3.01 3.01
GND
RES_0603_56 res_0402_301 res_0402_301
MC4 7 TXF
0.1uF TXF
MJ5 cap_0402_01uf 13
GPIO MR4
1
110

VC

EP
2
AGND_LSD 5% MR7
@ 9.1

17
B res_1206_91 B

VC_LSD
GND
<BOM Structure>
AGND_LSD

MC2
Revision History 0.1uF
cap_0402_01uf
REV Description Date
0 Initial Release April 26, 2005 AGND_LSD

No changes to schematic. PCB updated to -003.

1 Updated footprints and corrected via spacing errors. August 18, 2005

Changed MC8 and MC9 pads. No schematic changes.

2 PCB updated to -005. November 3, 2005

3 Added MR11 and MR12. PCB updated to -007. November 18, 2005
A A

4 Added MR13. PCB updated to -009. January 3, 2006

4.01 AVL update only. April 20, 2006

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMOM-CX20548
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 27 of 47
5 4 3 2 1
 A B C D E

+5VAMP R335 +5VS

0.1U_0402_16V4Z 0_1206_5% JP16
1 2 SPKR-
SPKR+ 1
1 1
2

47P_0402_50V8J

47P_0402_50V8J
1 1 1
1 1 ACES_85205-0200
C336 C337 C338 CONN@

2
C339

C340
10U_0805_10V4Z
2 2 2
2 2 D16
0.1U_0402_16V4Z @ @
10 dB @ SM05_SOT23
+5VS

1
1

1
16
15
6
U18 R336 @ R337
100K_0402_5% 100K_0402_5%

PVDD1
PVDD2
VDD

2
02/07 Change to 1K Ohm C341 1 2 0.47U_0603_16V7K 7 2
RIN+ GAIN0
R2264 C342 3
1K_0402_5% 0.47U_0603_16V7K GAIN1

1
2 1 LINE_C_OUTR 1 2 17
<26> LINE_OUTR R2265 RIN- SPKR+ @ R338 R339
ROUT+ 18
1K_0402_5% 100K_0402_5% 100K_0402_5%
<26> LINE_OUTL 2 1
14 SPKR-

2
C344 1 ROUT-
2 0.47U_0603_16V7K 9 LIN+
4 MIC_SENSE
LOUT+ <26> MIC_SENSE
2 2
C345 1 2 0.47U_0603_16V7K 5 LIN-
MIC IN
8 08/ 10
LOUT-
2 JP17
5
C346
12 L18 47P_0402_50V8J 4 10
NC FBM-11-160808-601-T_0603 1
9

THERMAL PAD
10 Keep 10 mil width MIC_R 1 2 3 8
BYPASS <26> MIC_R
+3VALW 1 2 19 SHUTDOWN 6 7
R340 @ 10K_0402_5% 2 MIC_L 1 2 2
<26> MIC_L

47P_0402_50V8J
L19 1
GND1
GND2
GND3
GND4

C347 FBM-11-160808-601-T_0603 1
1U_0603_10V4Z FOX_JA6333L-B3S0-7F~N

2
1 CONN@
2 1 08/ 09
20
13
11
1

21

C348
@ R2198 0_0402_5%
TPA6017A2_TSSOP20
1

D @ SM05_SOT23

1
2 Q16 09/03 D17
<26,30> EAPD#
G @ 02/14 Change to AGND
2N7002LT1G_SOT23 S
HP OUT
3

HP_SENSE
<26> HP_SENSE

3 C349 R341 3
<30> A_SD# 2 1 02/07 Change to 60 Ohm 0603 JP18
R2255 0_0402_5% HP_R 2INTSPK_CR+ R342 2

+
<26> HP_R 1 2 1 1 5
0_0402_5%
60_0603_1% 4 10
100U_6.3V_M
9
PR 3 8
C350 R343
6 7
HP_L 2INTSPK_CL+ 1 R344 PL

+
<26> HP_L 1 2 1 2 2
1
60_0603_1% 0_0402_5% C352
100U_6.3V_M C351 FOX_JA6333L-B3S0-7F~N

2
47P_0402_50V8J CONN@

2
+3VALW R2269 08/ 09
0_0402_5% R345 R346
5

U33 2 1 A_SD
1K_0402_5% 1K_0402_5% 47P_0402_50V8J
P

2 4 @ SM05_SOT23

1
A Y D18
2 1
G

NC7SZ04P5X_SC70-5 @ D35
1

1
Q44 D Q45 D
3

CH751H-40_SC76 A_SD 2 A_SD 2

G G 02/14 Change to AGND
0.1U_0402_16V4Z 1 2N7002_SOT23 S 2N7002_SOT23 S
3

3
@ C1484

2
02/26 add HP de-pop circuit
4 4

Security Classification Compal Secret Data

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
AMP and Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 28 of 47
A B C D E
 5 4 3 2 1

+USB_VCCA
14" USB Port
1
1 1

100U_6.3V_M
+ C354 C355

C353
1000P_0402_50V7K
2 2 2
D D
0.1U_0402_16V4Z
@
JP20
1 VCC
<20> USB20_N1 2 D-
<20> USB20_P1 3 D+
1 1 4 GND
3

D19 C356 C357 5

@ PSOT24C_SOT23 @ 10P_0402_50V8J @10P_0402_50V8J GND1
6 GND2
2 2
1

For ESD SUYIN_020173MR004G552ZR

+USB_VCCA CONN@

1
1 1
100U_6.3V_M

+ C359 C360
C358

1000P_0402_50V7K
2 2 2

0.1U_0402_16V4Z

JP21
1 VCC
<20> USB20_N0 2 D-
<20> USB20_P0 3 D+
1 1 4 GND
3

C C
D21 C365 C366 5
@ PSOT24C_SOT23 @ 10P_0402_50V8J @10P_0402_50V8J6 GND1
2 2 GND2
1

SUYIN_020173MR004G552ZR
CONN@

+5VALW

+USB_VCCA
U19
1 GND OUT 8
C368 0.1U_0402_16V4Z 2 7
IN OUT
2 1 3 IN OUT 6
<33,38> SLP_S5 4 EN# FLG 5 USB_OC# <20>
G528_SO8

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 29 of 47
5 4 3 2 1
 5 4 3 2 1

+3VL +3VS
03/10 Add Keyboard scan input PU resistor
BIOS debug port
RP29 +3VL
1 8 KSI0 1 1 1 1
Place under KB area
2 7 KSI3 C374 C375 C376 C377
3 6 KSI2 +3VL
4 5 KSI1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2 2 2 JP22
1 1 1 1 1 1
10K_1206_8P4R_5% C369 C370 C371 C372 C373 C1446 02/14 Reserve R2268 for OCP#
0.1U_0402_16V4Z VCC1_PW RGD 1
RP30 2 C1460 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 10U_0805_10V4Z R2238 1 2 0_0402_5% WLAN@
KSI7 2 2 2 2 2 2 R2268 1 0_0402_5% WL_BTN# <31,32> EC_GPIO9 3
1 8 2 OCP# <4,20,42> 4
2 7 KSI6 EC_GPIO8
1 WL_LED_EC# <25> 5
3 6 KSI5 R2239 1 2 0_0402_5%
D KSI4 +3VL R2240 1 0_0402_5% 4C#_6C8C <42> 6 D
4 5 2
LID_OUT# <20> ACES_85201-0602

1
10K_1206_8P4R_5% +3VL CONN@

127
128

106

119

100
126
RP35

94
95
96
97

39
58
84

14

49

15

93
98
99
02/07 Delete KSI PU, 1 8 KSO6 U20 R2220

1
2 7 KSO3 10K_0402_5%

CAP
NC
NC
NC
NC
NC
NC

VCC1
VCC1
VCC1
VCC1
VCC1

VCC1

VCC2

GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
+5VS 1070 had internal PU 3 6 KSO12 R353

2
4 5 KSO13 KSO0 21 124 KBC_PWR_ON
KSO0 OUT0 KBC_PWR_ON <37>
R354 KSO1 20 125 GREEN_BATLED# 10K_0402_5%
TP_CLK @ 10K_1206_8P4R_5% KSO2 KSO1 OUT1/IRQ8# GREEN_BATLED# <31>
1 2 19

2
KSO3 KSO2 LAN_RST# D22
18 KSO3 OUT7/SMI# 123 LAN_RST# <20>
10K_0402_5% RP36 KSO4 KBRST#
17 KSO4 OUT8/KBRST 122 1 2 KB_RST# <19>

General Purpose I/O Interface

R355 1 8 KSO9 KSO5 16 121 INV_PWM INV_PWM <17>
KSO5 OUT9/PWM2

Keyboard/Mouse Interface
1 2 TP_DATA 2 7 KSO0 KSO6 13 KSO6 OUT10/PWM0 120 FAN_PWM
FAN_PWM <4>
CH751H-40_SC76
3 6 KSO5 KSO7 12 118 CHGCTRL
10K_0402_5% KSO1 KSO8 KSO7 OUT11/PWM1 CHGCTRL <36>
4 5 10 KSO8
KSO9 9 107 FWP# Pin82 250 -- nFWP
RP31 @ 10K_1206_8P4R_5% KSO10 KSO9 GPIO01 ON/OFFBTN_KBC# +3VS
8 KSO10 GPIO02 79 ON/OFFBTN_KBC# <32> R2253
KBD_CLK +3VL KSO11 LOW_BAT#
1 8 7 KSO11 GPIO03 80 LOW_BAT# <20>
2 7 KBD_DATA Pin3 250 : KSO12/OUT8/KBRST KSO12 6 81 KSO14 LID_SW# 1 2
PS2_CLK KSO13 KSO12/GPIO00/KBRST GPIO04/KSO14 KSO15 10K_0402_5%
3 6 5 KSO13/GPIO18 GPIO05/KSO15 83
PS2_DATA RP37
4 5
1 8 KSO2 85 PM_RSMRST# PM_RSMRST# <20,24>R2245 10_0402_5%
10K_1206_8P4R_5% KSO4 KSI0 GPIO07/PWM3 EC_GPIO8 +3VL
2 7 29 KSI0 GPIO08/RXD 86 1 2 ENABLT <9,17>
3 6 KSO7 KSI1 28 87 EC_GPIO9
KSO8 KSI2 KSI1 GPIO09/TXD D23
4 5 27 KSI2
KSI3 26 88 BATCON 2 1
KSI3 GPIO11/AB2A_DATA BATCON <36> ADP_PRES <36,37,42>
Note: R94 must be removed when @ 10K_1206_8P4R_5% KSI4 25 89
KSI5 KSI4 GPIO12/AB2A_CLK EC_GPIO13 CH751H-40_SC76
24 KSI5 GPIO13/AB2B_DATA 90
R1354 stuff and R87 remove. RP38

SMSC_1070_TQFP-128P
KSI6 23 91 2 R359 1 +3VL EC_GPIO13 1 R357 2
+3VS KSI6 GPIO14/AB2B_CLK LID_SW# <17,32>
1 8 KSO14 KSI7 22 92 PCI_SERR# 10K_0402_5% 100K_0402_5%
KSI7 GPIO15/FAN_TACH1 PCI_SERR# <18,24>
2 7 KSO11 101 THM_MAIN# D24 02/07 Delete THM_MAIN# double PU
C GPIO16/FAN_TACH2 THM_MAIN# <41> C
R360 3 6 KSO10 102 A20M 1 2
LPCPD# KSO15 TP_CLK GPIO17/A20M CH751H-40_SC76 GATEA20 <19> +3VL
1 2 4 5 <32> TP_CLK 35 IMCLK
TP_DATA 36 103 NUM_LED#
<32> TP_DATA IMDAT GPIO20/PS2CLK NUM_LED# <25,31>
10K_0402_5% @ 10K_1206_8P4R_5% KBD_CLK 38 105 SLP_S3# RP32
KCLK GPIO21/PS2DAT SLP_S3# <20,33,39>
R361 KBD_DATA 40 4 1 2 DISPLAYOFF# <17> SMB_EC_CK1 1 8
KDAT GPIO24/KSO16
1 2 RUNSCI_EC# PS2_CLK 41 EMCLK GPIO27 74 MODE R2246
1 0_0402_5%
2 EAPD#
Pin1 250 -- TEST Pin ( NC !! )
<26,28> Pin57 250 -- MODE
SMB_EC_DA1 2 7
PS2_DATA 42 R362 0_0402_5% AB1B_DATA 3 6
10K_0402_5% EMDAT AB1B_CLK
02/26 Reserve KSO PU resistor 4 5

111 SMB_EC_DA1 SMB_EC_DA1 <41> 4.7K_1206_8P4R_5%

CLK_PCI_EC AB1A_DATA SMB_EC_CK1
AB1A_CLK 112 SMB_EC_CK1 <41>
Access Bus Interface
1

PM_CLKRUN# 55 109 AB1B_DATA

<20,24> PM_CLKRUN# CLKRUN# AB1B_DATA
R363 SIRQ 57 110 AB1B_CLK
<20,24> SIRQ SER_IRQ Power Mgmt/SIRQ AB1B_CLK
CLK_PCI_EC 54
<15> CLK_PCI_EC PCI_CLK
@ 10_0402_5% RUNSCI_EC# 76 73 PGM R364 1 2 0_0402_5%
<20> RUNSCI_EC# EC_SCI# PGM Strap/GPIO25 A_SD# <28>
R365 C378
2

2 108 EA# Pin83 250 -- nEA ( pull up !! ) @ @

C379 LPC_AD3 EA Strap#/GPIO26/KSO17 CLK_14M_KBC Pin56 250 -- PGM CLK_14M_KBC1
<19,25,31> LPC_AD3 51 LAD[3] CLOCKI 59 CLK_14M_KBC <15> 2 1 2

Miscellaneous
LPC_AD2 50 75 32K_CLK Pin58 250 -- 32KHz_OUT
<19,25,31> LPC_AD2 LAD[2] 32KHZ_OUT/GPIO22
@ 10P_0402_25V8K LPC_AD1 48 60 PM_POK Pin49 250 -- Reset Out
1 <19,25,31> LPC_AD1 LAD[1] RESET_OUT#/GPIO06 PM_POK <7,20> 10P_0402_25V8K
LPC_AD0 46 LPC 78 PWR_GD 10_0402_5%
<19,25,31> LPC_AD0 LAD[0] PWRGD PWR_GD <33,34,40,42>
77 VCC1_PW RGD
LPC_FRAME# 52
Bus VCC1_PWRGD
61 EC_GPIO19
VCC1_PWRGD <31,34>
<19,25,31> LPC_FRAME# LFRAME# 24MHZ_OUT/GPIO19/WINDMON
PLT_RST# 53
Pin34 250 -- LPCPD# <7,18,20,22,24,25,31> PLT_RST# LRESET#
45 69 TEST 1 2
R367 1 LPCPD#/GPIO23 TEST PIN Pin52 250 -- XOSEL
<20> LPC_PD# 2 @ 0_0402_5% LPCPD# R366 300_0402_5% @ R369
Pin91 250 -- nDMS_LED FWP# 1 2 PM_POK
C RY1 70 116 EC_WL_LED#
XTAL1 DMS_LED#/GPIO10 EC_WL_LED# <31>
1 2 C RY2 71 113 AMBER_BATLED# 10K_0402_5%
XTAL2 BAT_LED# AMBER_BATLED# <31>
115 STB_LED#
CP1
EMI Add R370 +RTCVCC +3VL PWR_LED#/8051TX
114 CAPS_LED#
STB_LED# <25,31,32>
B FDD_LED#/8051RX CAPS_LED# <25,31> B
KSO14 1 8 @ 2M_0402_5% R371 68 VCC0
AGND

KSO11 2 7 2 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KSO10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
3 6
2

KSO15 4 5 120K_0402_5% R372 R62 250@ +3VL

@ R2277 @ R2266 KBC1070_VTQFP128 MODE 1 2 JP23
1
2
3
30
31
32
33
34
43
44

72

11
37
47
56
104
82
117

62
63
64
65
66
67
1

@ 100P_1206_8P4C_50V8 0_0402_5% 0_0402_5% 2/08 Delete NUM_LED# Double PU

Y4 @ 10K_0402_5% VCC1_PW RGD 1
CP2
IN

OUT

KSO6 1 NUM_LED# 2
8 1 1
1

KSO3 2 18P_0402_50V8J 18P_0402_50V8J R375 3

7 +3VL R374 1 2 100K_0402_5% STB_LED# 4
KSO12 3 6 C380 C381 PGM 1 2 R376 1 2 100K_0402_5% CAPS_LED#
KSO13 4 5
NC

NC

5 6
2 2 @ 1K_0402_5%
2
2

@ 100P_1206_8P4C_50V8 @ C382
2

R2267 02/07 Reserve VCC0 to +3VL R377 ACES_85201-0602

CP3 1U_0603_10V4Z 0_0402_5% FWP# 1 2 CONN@
KSO2 1 8 32.768KHZ_12.5P_Q13MC30610018 1 , Add R2267 to GND 03/10 BOM delete
KSO4 2 7 03/19 Reserve VCC0 to +RTCVCC @ 1K_0402_5% For KBC debugging used.
R2273、 R2274(SMSC
1

KSO7 3 6
KSO8 4 5 leakage issue)
@ +3VL
@ 100P_1206_8P4C_50V8 32K_CLK R378 1 0_0402_5% ADP_EN J4 R379
2 1. For normal operation:
CP4 PGM 1 2 1 2 EC_GPIO8 2 1
KSI3 1 8 KSO15 Un-install R377,R379 @ R2273
KSO5 KSO10 1 NO SHORT PADS 1K_0402_5% 4.7K_0402_5%
2 7
KSO1
KSI0
3
4
6
5 INT_KBD CONN. KSO11
KSO14
KSO13
2
3
4 FWP# 2
R380
1
2. For KBC internal ROM flash:
Install R377,R379
32K_CLK 2
@ R2274
1

4.7K_0402_5%
@ 100P_1206_8P4C_50V8 KSO12
KSO3
KSO6
5
6
7
AGND FILTER @ 1K_0402_5%
EC_GPIO192
@ R2275
1
INT_KBD CONN. KSO8 8 C384 R381 4.7K_0402_5%
ACES_85201-2405 KSO7 9 TEST
CP5 1 2 2 1
A KSI4 CONN@ KSO4 10 @ 1K_0402_5% EC_GPIO9 2 A
1 8 11 1
KSI5 2 7 KSO2 0.1U_0402_16V4Z @ R2276
KSO0 KSI0 12 R382 4.7K_0402_5%
3 6 13
KSI2 4 5 KSO1 EA# 2 1
KSO5 14 1K_0402_5%
15 250@ 1021@ 02/27 Add PD resister
@ 100P_1206_8P4C_50V8 KSI3
CP6 KSI2 16
KSI1 1 8 KSO0 17 R127 R129
KSI7
KSI6
2 7 KSI5
KSI4
18
19 R128 R131
Security Classification Compal Secret Data Compal Electronics, Inc.
3 6 20 Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
KSO9 4 5 KSO9
KSI6 21 R977 R78 LPC47N1021
22 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@ 100P_1206_8P4C_50V8 KSI7 Size Document Number Rev
KSI1 23 R62 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
24
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JP24 Date: Tuesday, March 20, 2007 Sheet 30 of 47
5 4 3 2 1
 5 4 3 2 1

BIOS ROM
If use System SPI ROM, R2217 should be placed If use LPC Debug +3VALW
Port , R2217 should be delete, and R2216 must pull high

+3VALW
1
C385 +3VS
+3VALW
D R384 0.1U_0402_16V4Z D
1 2 SPI_WP#
2 Wireless LED

2
3.3K_0402_5% U21
BLUE

2
R385 8 4
VCC VSS
1 2 SPI_HOLD# R2216 R383
3.3K_0402_5% 1K_0402_5% SPI_WP# 3 27_0402_5%
W WLAN14@
@

1
SPI_HOLD# 7

1
R2217 HOLD

2
SPI_CS# 1 2 1 02/06 change XMIT_OFF#
<20> SPI_CS# S
0_0402_5% WLAN14@ D25
SPI_CLK 6 S LED HT-170NBQA 0805 BLUE
<20> SPI_CLK C R386
SPI_SI 5 2 SPI_SO_L 1 2 SPI_SO SPI_SO <20>
XMIT_OFF# LED
<20> SPI_SI D Q 47_0402_5%

1
SST25LF080A_SO8-200mil
R1291 place cloe to U66
0 1
WL_LED# <25,32>

1 0 R2272
1 2 EC_WL_LED# <30>
0_0402_5%

1
D
LPC Debug Port <20,25> XMIT_OFF#
XMIT_OFF# 2
G
@ Q47
RHU002N06_SOT323
+3VL S
Change from +3VL to +3VS. 6/9

3
2
02/26 Add R2272 for EC
Add in 7/24.
Removed +3VS. 6/13 @ R388
output and driver WLAN LED
100K_0402_5%

100K_0402_5%
1

C B+ C

1
R741
2

NUM_LED# JP27 *WLAN LED Control note

1 Ground
<15> CLK_33M_LPC 2 LPC_PCI_CLK WLAN have 3 ways control , the table list
3
4
Ground componet must be stuff
<19,25,30> LPC_FRAME# LPC_FRAME#
5 +V3S
<7,18,20,22,24,25,30> PLT_RST# 6 LPC_RESET#
7 WLAN Card R2263
<19,25,30> LPC_AD0 8
+V3S
LPC_AD0
1 CAP LED
<19,25,30> LPC_AD1 9 LPC_AD1
10 R388 BQ47 +3VS
<19,25,30> LPC_AD2
11
LPC_AD2 2 XMIT_OFF#
<19,25,30> LPC_AD3 LPC_AD3
12 VCC_3VA
13 EC control R2270、R2271、R2272
<25,30,32> STB_LED#
<25,30> CAPS_LED# 14
PWR_LED#
CAPS_LED#
3 D26 R389
NUM_LED# 15
<25,30> NUM_LED# NUM_LED# CAPS_LED#
<30,34> VCC1_PWRGD 16 VCC1_PWRGD 1 2 1 2
SPI_CLK 17
SPI_CS# SPI_CLK 17-21SYGC/S530-E1/TR8_GRN
18 SPI_CS# 200_0402_5%
SPI_SI 19
SPI_SO SPI_SI
SPI_HOLD#
20
21
SPI_SO GREEN
SPI_HOLD#
22 Reserved
23 Reserved
24 Reserved
B B
Connect pin3 & 23
ACES_87216-2404_24P
together and pin 24 CONN@
to GND in 6/29.
+3VALW

WL ON/OFF POWER LED

1
R392
200_0402_5%
Charge LED +3VS
14@

2
02/06 change Battery LED to +3VL +3VL +3VL

2
WLAN14@
R735 WLAN14@
SW1
10K_0402_5%
1BT002-01210_4P 17-21SYGC/S530-E1/TR8_GRN
GREEN
3 1 14@ D28

1
1

WL_BTN# 4 2
<30,32> WL_BTN#
R390 R391 1
200_0402_5% 200_0402_5%

5
6
D34 STB_LED#
@ SF10402ML080C_0402
2

2
2

A D27 A
Battery LED
19-22UYSYGC/S530-A2/TR8_ G/Y
AMBER GREEN
1

AMBER_BATLED#
<30> AMBER_BATLED# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
GREEN_BATLED#
<30> GREEN_BATLED#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM/PS2/LED/SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 31 of 47
5 4 3 2 1
 LID_SW
POWER SWITCH

2
D29
SF10402ML080C_0402 SPPB530600_4P
@
SW3 14@ 3 1 LID_SW#
1BT002-01210_4P 1
3 1 4 2

4 2 @ SW2
ON/OFF#

5
6
SPPB530600_4P

3 1 LID_SW#

4 2

SW4
14@
TP_DATA
2/16 Co lay for 14" assembly issue TP_CLK

2
D30
@ PSOT24C_SOT23

Power button T/P Board

+3VL

1
+5VS
+3VL +3VL

1
R393 1
1

C386
R394 100K_0402_5%
JP25
0.1U_0402_16V4Z

2
100K_0402_5% U22A ON/OFFBTN_KBC# 2
14

ON/OFFBTN_KBC# <30> 6
SN74LVC14APWLE_TSSOP14
2

5
1
R395 D
P

+3VALW 4 TP_DATA <30>

ON/OFF# 1 I O 2 1 2 2
G R396 3 TP_CLK <30>
2
G

1 100K_0402_5% 1 S 1 2
3

C387 C388 100K_0402_5% 1

7

1U_0603_10V4Z 1U_0603_10V4Z 1 2 ON/OFFBTN# ACES_87151-06051 1 1 EMI

2 2 ON/OFFBTN# <20> CONN@
Q21 @ C389 C390 @
RHU002N06_SOT323 D31 100P_0603_50V8J 100P_0603_50V8J
CH751H-40_SOD323 2 2

12/25

+3VS +3VALW

JP26
1
ON/OFF# 2
STB_LED# 3
<25,30,31> STB_LED# 4
WL_LED#
<25,31> WL_LED# 5
WL_BTN#
<30,31> WL_BTN# 6
LID_SW#1 2 LID_SW#_R
<17,30> LID_SW# 7
R397 1K_0402_5%
8
ACES_85201-0805_8P
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ON_OFF/LID/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 32 of 47
 A B C D E

1 1
+5VALW

1
C394
R398
+VCC_CORE 1 2 +VCCP
100K_0402_5%

2
0.1U_0402_16V4Z

<29,38> SLP_S5 SLP_S5

C395

+VCCP 1 2 +1.5VS

1
D
SLP_S5# 2
0.1U_0402_16V4Z <20,38> SLP_S5#
G
Q22 S
C396

3
RHU002N06_SOT323
+1.5VS 1 2 +1.8V

0.1U_0402_16V4Z

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

+3VALW +3VS
+5VALW +5VS B+
2 U24 2
U25 8 1 10U_0805_10V4Z
D S

1
8 1 7 2 +3VL
D S R399 D S
7 D S 2 1 6 D S 3
1 6 3 C397 5 4 1 1
D S D G

1
C398 5 4 1 1 330K_0402_5% C399 C400
D G C401 C402 AO4422_SO8 R400

2
AO4422_SO8 2 10U_0805_10V4Z
2 10U_0805_10V4Z 10U_0805_10V4Z 2 2 100K_0402_5%
2 2 RUNON

2
RUNON

1
J5 0.1U_0402_16V4Z
0.1U_0402_16V4Z R401 <38> SLP_S3 SLP_S3
SHORT PADS
1 2
470_0402_5%

1
D D

2
SLP_S3 2 1 SLP_S3# 2
<20,30,39> SLP_S3#
G C403 G
Q23 S Q24 S
3

3
RHU002N06_SOT323 0.01U_0402_25V7Z RHU002N06_SOT323
2

3 3

Discharge circuit PWR_GD <30,34,40,42>

+3VS
+0.9V +1.8V +2.5VS +5VS +1.5VS

1
1

1
R402
R403 R404 R406 R407 R408
470_0402_5%
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
2
1 2

1 2

1 2

1 2

1 2
1

D D D D D D
SLP_S5 1 2 2 SLP_S5 2 SLP_S3 2 SLP_S3 2 SLP_S3 2 SLP_S3 2
R409 @ 0_0402_5% G G G G G G
S Q26 S Q28 S Q29 S Q30 S Q31 S
3

3
SLP_S3 1 2 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
0_0402_5%
R410 Q25
RHU002N06_SOT323

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 33 of 47
A B C D E
 +3VL

+VCCP

1
+3VS +3VS +3VL +3VL +3VL
R414

+3VL 10K_0402_5%

2
2
R2241 R413 R416
R2242

14

14
VCC1_PWRGD <30,31>
1K_0402_5% 330_0402_5% U22B U22C D32 100K_0402_5%

14
330_0402_5% R415 CH751H-40_SOD323 U22D

P
1

1
D
3 4 1 2 5 6 1 2

P
1
I O 47K_0402_5% I O
9 I O 8 2

G
G Q33

G
C SN74LVC14APWLE_TSSOP14 1 SN74LVC14APWLE_TSSOP14 1 S RHU002N06_SOT323

3
2 Q40 C404 C405 SN74LVC14APWLE_TSSOP14

7
B MMBT3904_SOT23 +3VS
E 0.1U_0402_16V4Z 0.1U_0402_16V4Z

3
2 2
1

C
2 Q41

1
B MMBT3904_SOT23
E +5VS +3VL R417 @
3

10K_0402_5%
1 @

2
C406 U32

1
J6 TCM809TENB_SOT23-3
R418 0.1U_0402_16V4Z 1 2 PWR_GD
2 PWR_GD <30,33,40,42>
+3VL 1 3 VCC1_PW RGD
180K_0402_5% SHORT PADS VDD RESET#

GND
14
2 U22E

1
D

2
11 I O 10 2
G Q35

G
S RHU002N06_SOT323

3
1

1 SN74LVC14APWLE_TSSOP14

7
R419 C407

560K_0402_5% 0.1U_0402_16V4Z
2
2

02/07 Reserve RESET IC U32 for VCC1_PWRGD

+1.5VS +2.5VS +2.5VS +3VL

2

R420 R421 R422

14

1K_0402_5% 330_0402_5% 330_0402_5% U22F

1
D
P
1

13 I O 12 2
G Q36
1

C S RHU002N06_SOT323
3

2 Q37 SN74LVC14APWLE_TSSOP14
7

B CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10
1

C E PMST3904_SOT323 +3VS
3

<39> VCCP_POK 1 2 2 Q38

@ R2243 B

1
0_0402_5% E PMST3904_SOT323 1
3

R2244
12/27 FM1 FM2 FM3 FM4 FM5 FM6
10K_0402_5% 1 1 1 1 1 1
2

VCCP_ON <39>
1

D
2 H1 H2 H3 H4 H5 H6 H7 H8 H9 H14
G Q42 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
S RHU002N06_SOT323
3

1
12/27

H15 H16 H17 H18 H19 H20 H21 H23 H24 H25 H26
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
12/27

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POK CKT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 34 of 47
 A B C D

1 1

2
VIN 2

PL1
5

SMB3025500YA_2P
3 1
3 1 ADPIN 1 2

4 2

1000P_0402_50V7K

1
100P_0402_50V8J
4 2
1

1
PC5
PR3
PC4

PCN1 15K_0402_5%
SINGATRON_2DC_S736I201 PC3
2

2
1000P_0402_50V7K

2
PC2
100P_0402_50V8J

3 3

4 4

Security Classification Compal Secret Data

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
DC CONN Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 35 of 47
A B C D
 A B C D

B+ P5
PR256
PQ2
FDS4435BZ_SO8
BATT
0.015_2512_1% 3 8
1 2 2 7
P2
1 6
VIN P4
5
PQ3 PQ4
FDS4435BZ_SO8 FDS4435BZ_SO8 PR6

4
8 3 3 8 1 2 VIN
1 1
7 2 2 7 47K_0402_5%
6 1 1 6
5 5
PR5

0.1U_0603_16V7K
47K_0402_5%

4
2 1

1
47P_0402_50V8J
2

1
PC8
PR7 PR9 PL2

PC7
200K_0402_5% 0.015_2512_1% FBM-L11-322513-151LMAT_1210
2 1 2 1 2

2
1

2
PQ5 PR153

1
CHG_B+ 100K_0402_5% D
PR10
47K_0402_1% DTA144EUA_SC70-3 +3VLP 2 1 2 PQ32

10U_1206_25V6M

4.7U_1206_25V6K
1 2 2 G RHU002N06_SOT323-3

1
PR11 PR12 PR13 S

3
1

1
D PQ6 0_0402_5% D
100_0402_1% 100_0402_1%

PC9

PC10
2 DTC115EUA_SC70-3 2 1 ADP_PRES2
G PR14 G

1U_0805_25V4Z
S PQ8 150K_0402_5% PQ31 S

3
1
RHU002N06_SOT323-3 1 2 RHU002N06_SOT323-3

PC12
1
PC11 PD3

2
1U_0603_6.3V6M RLZ16B_LL34

1
2
3
PU1

1
D PR16 SE_ConPWR- 8
PR15 ACN ACDRV# 25
ADP_PRES 1 2 2 PQ10 0_0402_5% SE_ConPWR+ 9 22
G RHU002N06_SOT323-3
ADP_PRES2 ACP VCC D H_CHG
3K_0402_5% 1 26 ACDET PWM# 21 4
S 16 SE_CHG+

3
SRP

1
5 15 SE_CHG-
PR31 ENABLE SRN PQ9
28 ACSEL BATP 12
2 @0_0402_5% 19 ALARM BATDRV# 24 FDS4435BZ_SO8
BATT 2

2 SRSET
3 18 PR19

5
6
7
8
ACSET VS
+3VLP 2 PR18 1 27 ACPRES VHSP 20 0.015_2512_1%
100K_0402_5% 13 29 LX_CHG 1 2 1 2
BQ24703VREF IBAT GND PL3
4 VREF BATSET 6

100K_0402_1%

4.7U_1206_25V6K

10U_1206_25V6M
PR17 1 16UH_SIL104R-160PF_3.6A_30%
BATDEP

1
CHGCTRL 1 2 7 17
COMP GND

1
PR21

PC14

PC15
3K_0402_1%

3K_0402_1%
191K_0402_1% 10 23
NC1 NC4

1
+3VL
11 14

2
+3VL NC2 NC3

PR22

PR23
137K_0402_1%
2
1U_0603_10V6K

4.7U_0805_6.3V6K
BQ24703_QFN28 PD5

2
5

PR20
PU19 EC31QS04

2
1

1
P

NC
PC18

2
PC13

PC17
32.4K_0402_1%
2 A Y 4

1
BATCON <30>
0.047U_0402_16V7K

1 2

2
G

PR24
1U_0603_6.3V6M
2

+3VL

PC19
470K_0402_5%

3 SN74LVC1G14DCKR_SC70-5 0.1U_0402_16V7K
1

+3VL
PC158

PR250

1
CV=16.8V (4/8 CELLS LI-ION)
2

PU17 PR251 PR25

1

1K_0402_5% PU18 150_0402_1% =12.6V (6 CELLS LI-ION)

P

NC

1
2 4 1 2 2
P

A Y A

4.7U_0805_10V6K
4 PC20 CC=1.54A (4 CELLS LI-ION)

1 2
Y
G

1 150P_0402_50V8J

2
B
G

SN74LVC1G14DCKR_SC70-5 =3A (6/8 CELLS LI-ION)

3

+3VLP BATT

PC21
CHGCTRL 74LVC1G86GW_SOT353-5
PC157 PR248
3
1

2
1 2 1 2 2 PQ45

1
G
PR26

100K_0402_5%
1000P_0402_50V7K 1K_0402_5% S RHU002N06_SOT323-3 ADP_PRES 1 2 PR27
3

1
470K_0402_5%

3 1M_0402_5% 604K_0603_0.1% 3
1

PR28
PD18
PR249

1 2
P2 VIN
RLS4148_LLDS2 VIN

2
PR32
2

+3VALW
47_1206_5%

10K_0603_0.1%
PR60
133K_0603_1%

2
1
PR30

PC107 PR29
2

1
0.1U_0603_25V7K 10K_0402_1% PR37

1
1 2 47K_0603_0.1% PR155

2
PR33 PR154 47K_0402_5%
2

2.15K_0402_1% PR35 100K_0402_5%

PU2A @75K_0402_1%
1 2 3 3.2V
P

2
+

1
0.047U_0402_16V7K

470P_0402_50V7K
@100P_0402_50V8J
1 ADP_PRES

2
O
1

ADP_PRES <30,37,42>
10K_0603_0.1%

2 -
1

G
PC22

PR34

2
1

1
LM393DG_SO8 D PQ33
4

PR36 2 Batt_Det <41>

2

PC23

PC24
PD6 10K_0402_5% PR39 G
2

1
PR156 D
S RHU002N06_SOT323-3
"Lo": 4/8 CELLS LI-ION

3
P2 RLZ4.3B_LL34 @15K_0402_1% 17.4K_0603_0.1% 2
2

2
G
S PQ34
"Hi": 6 CELLS LI-ION
PR38

3
1 2 RHU002N06_SOT323-3
@10U_0805_6.3V6M

22P_0402_50V8J

60.4K_0402_1%
1

1
PC168

PC25

PU3
1.24VREF
2

4
4 REF CATHODE 3 4

NC 2

5 ANODE NC 1

LMV431ACM5X_SOT23-5
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 36 of 47
A B C D
 A B C D E

PC26 PC27
PL4 0.1U_0603_50V4Z 0.1U_0603_50V4Z
B++
1 1 2 BST_5V_B BST_3.3V_B 1 2 1
FBM-L11-322513-151LMAT_1210

2
B+ 2 1

2200P_0402_50V7K

10U_1206_25V6M
PD7
PR40 CHP202UPT_SOT323-3
PQ11

1
0_0402_5% VL B++
1 8DH_5V_B 1 2

1
D2 G2

PC28

PC29
2 7 PQ12

2
D2 D1/S2/K

2200P_0402_50V7K
3 G1 D1/S2/K 6 1 D2 G2 8

4.7U_1206_25V6K
4 S1/A D1/S2/K 5 2 D2 D1/S2/K 7

47_0402_5%
B++ 3 6
G1 D1/S2/K

1
SP8K10S-FD5_SO8 4 5
S1/A D1/S2/K

PR41

PC31

PC32
PC30

0.1U_0603_50V4Z
PR42 0.1U_0603_16V7K SP8K10S-FD5_SO8

2
0_0402_5%

2
PR43

1
0_0402_5%
VL 2VREF_1999
<42> LX_5V

4.7U_0805_10V4Z
DH_3.3V_B

1
1

2
1U_0805_16V7K
1

1
0_0402_5%

PC33

PC34
1
PR45

2
PR44

PC35
PL5

2
10U_LF919AS-100M-P3_4.5A_20% 0_0402_5%

1
2

0_0402_5%
2
@499K_0402_1%

@499K_0402_1%
18

20

13

17
2

2
PU4

PR46
2 BST_5V 14 2

PR47
V+
LD05

TON

VCC
BST5

PR48
ILIM3 5
DH_5V 16

1
DH5

1
+5VALWP

1
LX_5V 15
DL_5V LX5
19 DL5 ILIM5 11
@10.2K_0402_1%

21 PL6
OUT5 BST_3.3V 10U_LF919AS-100M-P3_4.5A_20%
9 FB5 BST3 28
2

1 26 DH_3.3V

2
B++ PR50 N.C. DH3
PR49

2VREF_1999 1 2 24 DL_3.3V
0_0402_5% DL3 LX_3.3V
6 SHDN# LX3 27
PC36 1 PR51 4 22
ON5 OUT3
1
47K_0402_5%

2VREF_1999 1 2 3
1

ON3
150U_D2_6.3VM

+ @0_0402_5% 7
FB3
PR52

1 2 12 SKIP# PGOOD 2 +3VALWP

2

0_0402_5%

PR53
2

PRO#
PR54

@3.57K_0402_1%
LDO3
@10K_0402_5% 8

GND
2

REF

2
2VREF_1999
0.1U_0603_25V7K

PR55
MAX8734AEEI+_QSOP28
1

23

25

10
1

0.22U_0603_10V7K
VL +3VLP 1

4.7U_0805_10V4Z
MAINPWON MAINPWON <41>

1
1
PC37

PC39
+
1
2

2
PC38
PR56

2
PC40
300K_0402_5%
2 1 PR57 220U_6.3VM_R15

2
2

PR244
0_0402_5%
499K_0603_1% 2

PR58
0_0402_5%
1

1
1

1
3 PC41 3
2

0.047U_0603_16V7K
VL

1
PR59
PQ13 100K_0402_5%
1

D
2

2
G
S RHU002N06_SOT323-3
3

1
D D
2 ADP_PRES <30,36,42> 2 KBC_PWR_ON <30>
G G
S PQ14 S PQ15
3

3
RHU002N06_SOT323-3 RHU002N06_SOT323-3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP / 5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 37 of 47
A B C D E
 5 4 3 2 1

PL15
FBMA-L11-322513-151LMA50T_1210
B+ 2 1 1.8V_B+

+5VALW +1.8VP

2200P_0402_50V7K

10U_1206_25V6M

220U_V_4VM_R25M

0.1U_0402_16V7K

0.1U_0402_16V7K
1

1
1

1
PC43

PC42

PC45

PC46
+

5
6
7
8
PC44

10_0402_5%
PC116

2
680P_0402_50V7K PQ16 2

1
FDS8884_SO8

PR157
PR158
D 1M_0402_5% D

2
4
PD14

2
1
PR159

1
470K_0402_5% PC118 1SS355_SOD323-2

BOOT_1.8V 1

3
2
1
1000P_0402_50V7K

2
<20,33> SLP_S5# 1 2
PR161 UG_1.8V

1
PR246 PR245 1 2 BOOT1_1.8V 1 2 PL7

1
0_0402_5% 100K_0402_5% 0_0402_5% 3.3UH_PCMC063T-3R3MN_6A_20%
PC120 PC119 1 2
@2200P_0402_25V7K 0.1U_0402_16V7K

16

15

14

13
2
PU11

2
1 2

EN/PSV
TON

NC

BST
<20> SLP_S4#

5
6
7
8

1
PR247 1 12 PQ17
VOUT DH

1
@0_0402_5% FDS6690AS_NL_SO8 PR252
PC121 2 11 LX_1.8V @4.7_1206_5%
1U_0603_10V6K VCCA LX PR162

2
3 10 1 2 4

2
FB ILIM 16.9K_0402_1%
4 PGD VDDP 9

1
PGND
VSSA
PC159

1
@680P_0603_50V7K

NC
TP

DL

3
2
1
PC122

2
SC411MLTRT_MLPQ16_4X4 1U_0603_10V6K

17

2
C C

LG_1.8V

PR163
1 2
27K_0603_0.1%
(500mA,40mils ,Via NO.= 1)
1 2 PU6
APL5508-25DC-TRL_SOT89-3 +2.5VSP
PC123 +3VS
33P_0402_50V8J 2 3
IN OUT

4.7U_0805_6.3V6K
1U_0603_10V6K
PR164

1
10K_0603_0.1% GND

PC50

PC51
PR260
1
@150_1206_5%

2
B B

+1.8V

PU7
1 VIN VCNTL 6 +5VALW

@10U_0805_10V4Z
2 GND NC 5

PC56

1
PC55 3 7
VREF NC

1
10U_0805_10V4Z

2
PR73 PC57
4 VOUT NC 8
PJP1 PJP2 1K_0402_1% 1U_0603_16V6K

2
+5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9) +2.5VSP 1 2 +2.5VS (500mA,40mils ,Via NO.= 1) 9

2
TP
PAD-OPEN 3x3m G2992F1U_SO8
PAD-OPEN 4x4m
PJP3
<29,33> SLP_S5 1 2

0.1U_0402_16V7K
1 2 +3VALW (3A,120mils ,Via NO.= 6) PJP8 PR255
+3VALWP +0.9VP

1
+3VLP 2 1 +3VL (100mA,20mils ,Via NO.= 1) @0_0402_5%
PQ18
PAD-OPEN 4x4m
PAD-OPEN 2x2m RHU002N06_SOT323-3 PR74

1
PJP4 D
1K_0402_1%
1 2 +1.8V (7A,280mils ,Via NO.= 14) 1 2 2 PC59
+1.8VP <33> SLP_S3

2
PJP9

PC58
PR75 G 10U_1206_6.3V7K

2
PAD-OPEN 4x4m 1 2 P5 0_0402_5% S
B+

3
1
PJP5
PAD-OPEN 4x4m
1 2 +VCCP (6A,240mils ,Via NO.=12) PC60
+1.05V_VCCP

2
@0.1U_0402_16V7K
A PAD-OPEN 4x4m A

PJP6
+1.5VSP 1 2 +1.5VS (4A,160mils ,Via NO.=8)
PAD-OPEN 4x4m
PJP7

+0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title
PAD-OPEN 3x3m
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP/0.9VSP/2.5VSP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3491P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 38 of 47
5 4 3 2 1
 5 4 3 2 1

D D

PL8 B+++
FBMA-L11-322513-151LMA50T_1210
B+ 1 2

@2200P_0402_50V7K
1

1
PR167 PR168
PC63

PC64 PR165 PR166 75K_0402_1% 29.4K_0402_1%

@2200P_0402_50V7K
4.7U_1206_25V6K 73.2K_0402_1% 75K_0402_1%
2

10U_1206_25V6M
1 2 1 2 1 2 1 2

1
PC61

PC62
2

2
2
PR169

5
6
7
8
0_0402_5%
PQ20
FDS8884_SO8

1
VCCP_POK <34>4
C C

1
PU12 PC163
@0.022U_0603_25V7K

VO2

VFB2

TONSEL

GND

VFB1

VO1
25

3
2
1
PR170 P PAD
0_0402_5% 12/29 PR173
PQ19 PR171 0_0402_5%
1 2 1 2 7 PGOOD2 PGOOD1 24
1 8 UG1_1.5V 0_0402_5% 1 2UG1_1.05V
D2 G2 PR174 PL9
2 7 PC124 8 23
3
D2 D1/S2/K
6 0_0402_5% EN2 EN1 PR175 2.2UH_PCMC063T-2R2MN_8A_20% +1.05V_VCCP
G1 D1/S2/K PC125
4 5 2 1 1 2 BST_1.5V 9 22 BST_1.05V 0_0402_5%
S1/A D1/S2/K VBST2 VBST1
1 2 1 2 1 2
+1.5VSP SP8K10S FD5 2N SOP8 UG_1.5V 10 21 UG_1.05V
0.1U_0603_25V7K DR VH2 DR VH1

220U_6.3VM_R15
0.1U_0603_25V7K
PL10
11 LL2 LL1 20
2 1 LX_1.5V LX_1.05V 1

5
6
7
8
12 DR VL2 DR VL1 19

PC71
3.3UH_SIQB74-3R3RF_4.8A_30% LG_1.5V LG_1.05V +
PC72

PGND2

PGND1
V5FILT
TRIP2

TRIP1
4.7U_0805_6.3V6K

V5IN

2
2
1
220U_6.3VM_R15

4
2
PC73

+ TPS51124RGER_QFN24_4x4 PQ35

13

14

15

16

17

18
PC74 FDS6690AS_NL_SO8
4.7U_0805_6.3V6K
1

3
2
1
1
PR176
PR178 15K_0402_1% PR177
10K_0402_5% 1 2 18K_0402_1%
B B
<20,30,33> SLP_S3# 2 1

2
1

PC126

1
0.1U_0402_16V7K
2

1
PR179
PC127 3.3_0402_5%
1U_0603_10V6K VCCP_ON <34>
2

2
+5VALWP

1
PC128 1 2 SLP_S3#
4.7U_0805_10V6K
@0_0402_5%
2 PR180

1
12/29
PC129

2
@1000P_0402_50V7K

A A

Security Classification Compal Secret Data

2006/10/26 Title
Issued Date Deciphered Date 1.05VSP/1.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 39 of 47
5 4 3 2 1
 5 4 3 2 1

+5VS CPU_B+ B+
PL16
FBM-L11-322513-151LMAT_1210

2 1

2200P_0402_50V7K

1000P_0402_50V7K
0.01U_0402_25V7K

47U 25V M 6.3X6 ESR0.44 CE-LX

1

PC130
1

1
10U_1206_25V6M

10U_1206_25V6M
PC131
+
PR181

PC132

PC133

PC134

PC162
10_0402_5%

2
PC135

2
2
2.2U_0603_6.3V6K

1
1U_0603_16V6K

200K_0402_5%
D D

PR182
PC136
PR183

1
13K_0402_5% BSTM1 CPU

2
2

0.22U_0603_16V7K

5
6
7
8
PU13
@470KB_0402_5%_ERTJ0EV474J

D
D
D
D
2
PC137
PH2 V CC 19 25 PQ36
Vcc VDD SI4684DY-T1-E3_SO8
2 1
6 8

1
THRM TON

G
S
S
S
2 1 31 30 BST1_CPU 2 1

4
3
2
1
<5> CPU_VID0 PR184 0_0402_5% D0 BST1 PR185 0_0402_5% PL17
+VCC_CORE
2 1 32 29 PR187 2.2_0402_5%
<5> CPU_VID1 PR186 0_0402_5% D1 DH1 DH11_CPU 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
2 1 33 28 LX1_CPU
<5> CPU_VID2 PR188 0_0402_5% D2 LX1 +VCC_CORE
1 2
2 1 34 26 DL1_CPU
<5> CPU_VID3 D3 DL1

2
PR189 0_0402_5%

4.7_1206_5%
2 1 35 27 PR191
<5> CPU_VID4 D4 PGND1

D 5
D 6
D 7
D 8

5
6
7
8
FDS6676AS_SO8

FDS6676AS_SO8
PR190 0_0402_5% 2.1K_0603_1%

1
2 1 36 18

D
D
D
D
<5> CPU_VID5 D5 GND

PQ37

PQ38

PR253
PR192 0_0402_5% NTC

DL1_CPU

1
2 1 37 17 CSP1_CPU PH3
<5> CPU_VID6 PR193 0_0402_5% D6 CSP1

4 G

G
3 S
2 S
1 S

S
S
S
2 1 7 16 CSN1_CPU 1 2 1 2

2
TIME CSN1

680P_0603_50V7K
PR194 71.5K_0402_1% PR195

4
3
2
1
1 2 9 12 FB1_CPU 3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J
CCV FB

PC160
PC138 470P_0402_50V8J
C CC1_CPU C
1 2 11 REF CCI 10 1 2
PC139 0.22U_0603_16V7K

2
1 2 39 21 DH2_CPU PC140
<7,20> DPRSLPVR PR196 499_0402_1% DPRSLPVR DH2 0.22U_0603_16V7K
1 2 40 20 BST2_CPU
<4,19> H_DPRSTP# PR197 0_0402_5% DPRSTP BST2
1 2 3 22 LX2_CPU
<5> H_PSI# PSI LX2

0_0402_5%
PR198 0_0402_5%
2 24 DL2_CPU
PWRGD DL2
+3VS
1 CLKEN PGND2 23

2
1 2 1 2 VCCSENSE
38 14 CSP2_CPU PR200 @3K_0603_1% PC141 @0.022U_0402_16V7K VCCSENSE <5>
SHDN CSP2
5 15 CSN2_CPU 1 2 1 2
VRHOT CSN2
1

PR201
PR202 3.65K_0402_1% PR203 100_0402_5%

1
2

1
PR204 4 13 PC142
PR205 POUT GNDS
2K_0402_1%
1.91K_0402_1% 1 2 1 2 4700P_0402_25V7K

2
TP

BSTM2 CPU
2

NTC PR206 PR207

1

1000P_0402_50V7K
1 2 MAX8770GTL+_TQFN40 @3K_0603_1% @3K_0603_1%
41

<7,20> VGATE_INTEL PR208 0_0402_5% 1 2 1 2

1

PC144
1 2 CPU_B+
<15> CLK_ENABLE# PR210 0_0402_5% PR209 PC143
1 2 20K_0402_1% 470P_0402_50V8J
<30,33,34,42> PWR_GD
2
1

PR211

0.22U_0603_16V7K
12/29 0_0402_5%

2
PR212

2200P_0402_50V7K
@10K_0402_5%
2

1
10U_1206_25V6M

10U_1206_25V6M
2

1
PC145

PC146

PC147
B PR213 B

5
6
7
8

PC148
100_0402_5%

2
D
D
D
D

2
1 2 PQ39
1

<4> H_PROCHOT# PR214 @0_0402_5% SI4684DY-T1-E3_SO8

G
S
S
S
POUT 1 2 VSSSENSE PL18
PR215 10K_0402_5% <5> VSSSENSE

4
3
2
1
2

PR216 2.2_0402_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%

PC149 1 2
0.1U_0402_16V7K 1 2
1

4.7_1206_5%
1
D 5
D 6
D 7
D 8

5
6
7
8

2
FDS6676AS_SO8

FDS6676AS_SO8

PR254
PR217

D
D
D
D
PQ40

PQ41
2.1K_0603_1%

680P_0603_50V7K
DL2_CPU

1
4 G

G
3 S
2 S
1 S

S
S
S
NTC

PC161
PH4

4
3
2
1
1 2 1 2

2
PR218
3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J

1 2
A PC150 0.22U_0603_16V7K A

Compal Electronics, Inc.

Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, March 20, 2007 Sheet 40 of 47
5 4 3 2 1
 A B C D

VMB PL14 BATT

PCN2
HCB4532KF-800T90_1812
BATT+ 6 1 2
1 1

5 EC_SMD
SMD EC_SMC Batt_Det <36>
SMC 4 PR136
RES 3 2 1

1
TS 2 @1K_0402_5%

2
1 PC105 PC106

2
GND PD10 @SM05_SOT23 1000P_0402_50V7K 0.01U_0402_50V4Z
3
TYCO_C-1746706_6P 1
2

PR137 PD11

1
210K_0402_1% @SM24.TC_SOT23-3
1 2 +3VL
1
1

PR138
1K_0402_5%
PR139
2

PR140
100_0402_5% 100_0402_5%
THM_MAIN# <30>
2

SMB_EC_DA1 SMB_EC_DA1 <30>

SMB_EC_CK1 SMB_EC_CK1 <30>

2 2

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

PR141
+5VS 47K_0402_1%
1 2

+5VS
3 3

CPU
1

2
PR146
PH1 10K_0402_5%
2

10K_TH11-3H103FT_0603_1%

1
MAINPWON <37>
PR142
8

15K_0603_1% PU2B

1
D
1 2 5
P

+ PQ29
O 7 2
+5VS 1 2 6 G RHU002N06_SOT323-3
-
G

PR143 S

3
150K_0402_1% LM393DG_SO8
4
1

PR144
1

2.55K_0603_1%
PC108 PC109
0.22U_0603_10V7K PR145 1000P_0402_50V7K
2

150K_0402_1%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3491P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 41 of 47
A B C D
 5 4 3 2 1

+5VS
+5VS
+3VS PD15 PD16
1 2 1 2
+5VS
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
PR221

1
8

1U_0805_16V7K
PU14A PR223 PR220 1 2

PC151
3 330K_0402_5% PR222 133K_0402_1%

P
D D
+ 10K_0402_5% 100K_0402_5% PR224
1 0 2 1
P5
2

2
-
G

8
PU15B PU15A 10K_0402_5%
PR226

2
2

8
0_0402_5%

LM358ADR_SO8 PU14B 5 3

P
4

2
+ +
PR225

1 2 5 7 1

P
+ O O

1
6.81K_0402_1% 7 6 2
0 - -

G
1 2 1 2 6 PR229
-

G
PR227 PR228 LM393DG_SO8 LM393DG_SO8 10_0402_5%
1

4
1
10K_0402_1% 100K_0603_0.5% LM358ADR_SO8 PR231

1
PR230

0_0402_5%

2K_0402_5%
1 2

2
PR232
0_0402_5% 1 2

1
1U_0805_50V4Z

80.6K_0402_1%
PR233
1

0.027U_0402_16V7K
PC153

1 2 604K_0603_1% LX_5V <37>

2

PR234
2
PC152
2

1
PC154
0.22U_0603_16V7K PQ42

2
3
7.32K_0402_1%
E

1
B
2

2
PR235
PR236
C
MMBT3906_SOT23-3 3.9K_0402_5%

1
6.98K_0402_1%
PU16 PD17

2
1
PR257
4 3 @CH751H-40PT_SOD323-2
REF CATHODE

1
1M_0402_5%
1 2 PR238
2.2U_0603_6.3V6K

PR237

110_0603_1%

PR258
NC 2
PWR_GD <30,33,34,40> 1 2 OCP# <4,20,30>

2
1
PC155

5 1 0_0402_5%
C
ANODE NC C

2
2

1
LMV431ACM5X_SOT23-5 D

470K_0402_5%
<BOM Structure> 2 PQ43
G RHU002N06_SOT323-3
1

PR239
S

3
PR240

1
D
0_0402_5%

1
B+

3.9K_0402_5%

3900P_0402_50V7K
PQ46 2

1
RHU002N06_SOT323-3 G 1
2

PR241
S

3
1

1
1M_0402_5%

PC156
C

PR259
2 PQ44
<30,36,37> ADP_PRES B @MMBT3904W_SOT323-3 2

2
PR242 E
3

@124K_0402_1%

2
1 2

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B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADP_OCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 42 of 47
5 4 3 2 1
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Version change list (P.I.R. List) HW section Page 1 of 3

Item Reason for change PG# Modify List Date Phase

Add R2221、R2 222、R2223、R2224、R2225 for Disable
D Reserve Disable TV-out power plane resistor Page 10 TV-out power plane 01/02 DB2 D
1

2 R2211、R2212 Change to 10k follow datasheet Page 9 Change R2211、R2212 to 10K_0402_5% 01/02 DB2

Add resistor to +1.5VS power

3
Disable TV-out follow datasheet Page 9 TVDAC_A(R2172)、TVDAC_B(R2173)、TVDAC_C(R2174)、 01/02 DB2
TV_IREF(R57) BTVIRTNA、TVIRTNB、TVIRTNC(R2251)

4 Change CPU and NB BCLK follow heavenly2.0 Page 15 CPU --->CPUCLKT0/C0 01/02 DB2
NB --->CPUCLKT1/C1

5 Change Mini card CLK From SRC3 to SRC7 Page 15 Change to SRC7 01/02 DB2

Change JP6 PCB Footprint form

6 CRT connector PCB footprint error Page 16 01/02 DB2
C
SUYIN_070912FR015S207CR_15P to ALLTO_C10510-115A5-L_15P C

7 +ENAVDD add a 100k Pull low follow datasheet Page 17 Add R2247 to GND 01/02 DB2

8 LCDVDD enable timing Page 17 Change R159 to 47k、C213 to 0.1u 01/02 DB2

9 Change AND gate that one gate one chip Page 18 Change U28(4 in 1) to U30、 U31 01/02 DB2

10 Reserve R2230 for don't support wake up LAN

Reserve EE PROM power plane +3VS Page 19 01/02 DB2
Reserve R2231 for support wake up LAN

11 Add R2213 and verify need or not？ Page 19 Add R2213 01/02 DB2

Page 20
12 Change PCIE from port 1 to port 2 follow caymus Change MINI Card PCIE from Port 1to Port2 01/02 DB2
B Page 25 B

Page 20
13 Reserve LAN_RST# that can fine tune from EC Reserve R2233 for fine tune LAN_RST# timing 01/02 DB2
Page 30

14 Change R to RP , keep original design Page 20 Change to RP33、 RP34 01/02 DB2

If R2237 --->support wake up LAN

15 Reserve +3VS power plane for don't support wake up LAN Page 21 01/02 DB2
If R2236 --->Don't support wake up LAN

If R2234 --->AC97 codec

16 Reserve +3VALW power plane to verify HDA codec Page 21 01/02 DB2
If R2235 --->HD Codec

If L11 --->Don't support wake up LAN

17 Reserve +3VALW power plane support wake up LAN Page 23 01/02 DB2
If L20 --->Support wake up LAN

If L12、L13 --->Don't support wake up LAN

A 18 Reserve +3VALW power plane support wake up LAN Page 24 01/02 DB2 A
If L21、L2 2 --->Support wake up LAN

01/02 DB2
19 Reserve 0 ohm resistor for SMSC1070 Page 30 Reserve R2238、R2239、R2240
Compal Electronics, Inc.
Title
HW PIR (1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) HW section Page 2 of 3

Item Reason for change PG# Modify List Date Phase

D 20 Wireless LED design issue Page 31 Delete Q20 01/02 DB2 D

21 Change POK circuit form PGOOD to VCCP_ON Page 34 Add R2244 、Q42, and reserve R2243 01/02 DB2

22 LID_SW# add 10k pull high Page 30 Add R2253 for LID_SW# pull high 01/16 SI

23 Change use EAPD# to control Amp Shutdown Page 28 Reserve R2198 and add R2252 pull high 01/16 SI

24 Change Battery LED power from +3VALW to +3VL Page 31 Change Battery LED power from +3VALW to +3VL 02/06 PV

25 XMIT_OFF# control error Page 31 Delete Q46 02/06 PV

C
26 Delete KSI PU, 1070 had internal PU Page 30 Delete RP29、RP30 02/07 PV C

27 Reserve SMSC 1070 VCC0 to +3VL,Add R2267 to GND Page 30 Reserve R2266 to +3VL,Add R2267 to GND 02/07 PV

28 Change Codec Mix Resistor from 20k to 1k Page 28 Change R2264、R2265 to 1K 02/07 PV

29 Change LAN82562GT RBIAS resistor to 649 ohm Page 23 Change R274 to 649 ohm 02/07 PV

30 Reserve RESET IC for VCC1_PWRGD Page 34 Reserve RESET IC U32 for VCC1_PWRGD 02/07 PV

31 THM_MAIN# Double pull high Page 30 Delete R356 02/07 PV

B B
32 Fine tune PC Beep Page 26 BOM delete R310 02/09 PV

33 Change Hp series resistor to 60 ohm 0603 Page 28 Change R341、R343 to 60 ohm 0603 02/14 PV

34 Reserve OCP# to EC GPIO29(pin 98) Page 30 Reserve R2268 to EC GPIO29(pin98) 02/14 PV

35 HP、MIC E SD Diode change to AGND Page 28 HP、 MIC E SD Diode change to AGND 02/14 PV

36 HP de pop when boot Page 28 Add inverter to prevent HP pop noise 02/26 PV

Change CPU core decoupling capacitor height limit

37 C43、 C44 、C45 impact ME parts Page 06 1.9mm for short term solution(SGA19331D00) 02/26 PV

A A
Page 25 02/26 Add R2270 for WL_LED_EC# PU
38 WLAN LED use XMIT_OFF# have error beheive Page 30 02/26 Add R2271 for use EC detect WLAN active 02/26 PV
Page 31 02/26 Add R2272 for EC output and driver WLAN LED
Compal Electronics, Inc.
Title
HW PIR (2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 44 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) HW section Page 3 of 3

Item Reason for change PG# Modify List Date Phase

D 39 SMSC leakage current issue Page 30 Reserve R2273 、R2274、R2275、R2276 EC dummy pin 02/27 PV D

40 Reserve KSO PU resistor prevent SMSC chip issue Page 30 Reserve RP35 、RP36、RP37、RP38 for SMSC KSO 02/27 PV

41 BOM change (Delete CBS de-pop circuit) Page 26 BOM delete C1479 、 R2256 、Q43 03/10 MV

42 BOM add Keyboard matrix error issue Page 30 BOM Add Keyboard scan input PU resistor RP29、RP30 03/10 MV

43 BOM delete (SMSC leakage issue fail) Page 30 BOM Delete R2273、R2274 03/10 MV

44 Reserve +RTCVCC for SMSC VCC0 Page 30 Add R2277 03/19 MV

C C
45 Add CBS SPK depop circuit , change Q43 from FET to BJT Page 26 BOM add C1479、 R2256、Q43 03/19 MV

B B

A A

Compal Electronics, Inc.

Title
HW PIR (3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 45 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 1

Item Reason for change PG# Modify List Date Phase

D D
1 The PR172 changes to HW side 39 Remove PR172 2006/12/29 DB2

2 Change the +1.05V_VCCP power sequence 2006/12/29

39 Remove PR180 DB2

3 The +1.05V_VCCP dynamic range is over spec. 39 Change PL9 from 3.3UH to 2.2UH 2007/01/03 DB2

4 Adjust +1.5VSP voltage range 2007/01/03

39 Change PR165 from 75K_ohm to 73.2K_ohm DB2

5 Change the PD18 diode 2007/01/16 SI

C
36 Change PD18 from 1SS355 to RLS4148 C

6 Change the +3VALWP output capacitor. 2007/01/16 SI

37 Change PC38 from 150U_D2_6.3VM to 220U_6.3V_R15

7 Change the +0.9VP output capacitor. 38 2007/01/16

Change PC59 from 22U to 10U SI

8
Change the +1.05V_VCCP output capacitor. 39 Change PC71 from 220U_V_4VM_R25M to 220U_6.3V_R15 2007/01/16 SI

B 9 Change PC73 from 220U_6.3VM_R15 to 220U_6.3V_R15 2007/01/16 SI B

Change the +1.5VSP output capacitor. 39

Change PL11 from 3.3UH_PCMC063T-3R3MN_6A_20% SI

10 Change the +1.5VSP choke size. 39 2007/01/16
to 3.3UH_SIQB74-3R3RF_4.8A_30%

11 Change PD14 diode 38 Change PD14 from CH751H-40PT to 1SS355 2007/02/05 PV

12 Adjust PU3 operation current 36 Change PR38 from 75K_ohm to 60.4K_ohm 2007/02/05 PV

13 36 PV
Change PC25 capacitor. Change PC25 form .022U to 22P 2007/02/05

Change the +1.5VSP power sequence 39 1. Change PR178 form 0_ohm to 10K_ohm PV
A 14 2007/02/05 A
2. Add PC126 0.1U

Compal Electronics, Inc.

Title
PWR PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 46 of 47
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 1

Item Reason for change PG# Modify List Date Phase

D
15 40 1. add PR253, PR254 4.7_ohm PV D
Add CPU CORE snubber circuit 2007/02/05
2. add PC160, PC161 680P

16 Change PC155 capacitor. Change PC155 form 0.1U to 2.2U 2007/02/05

42 PV

17 40 Change PR187, PR216 form 0_ohm to 2.2_ohm PV

for EMI 2007/02/08

18 Remove PR187 and PR219. Remove PR187 and PR219. 2007/02/09 PV

40

19 Add PR60 36 Add PR60 47_ohm 2007/03/13 MV

C C

B B

A A

Compal Electronics, Inc.

Title
PWR PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2007 Sheet 47 of 47
5 4 3 2 1
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