On the Design of New Low-Power CMOS Standard
Ternary Logic Gates
Akbar Doostaregan, Mohammad Hossein Moaiyeri, Keivan Navi and Omid Hashemipour
Department of Electrical and Computer Engineering
Shahid Beheshti University, G. C.
Tehran, Iran
a.doustaregan@sbu.ac.ir; h_moaiyeri@sbu.ac.ir; navi@sbu.ac.ir; hashemipour@sbu.ac.ir
Abstract— A novel low-power and high-performance Standard
Ternary Inverter (STI) for CMOS technology is proposed in this
paper. This inverter could be used as a fundamental block for
designing other ternary basic logic gates. This circuit consists of
only MOS transistors and capacitors without any area consuming
resistors in its structure. Another great advantage of this design
in comparison with the other designs, introduced before, is the
elimination of the static power dissipation, which is very
important in nano scale CMOS and leads to less power
consumption. The proposed design has been simulated, using
Synopsys HSPICE tool with 90nm CMOS technology. The
simulation results demonstrate the superiority of the presented
design with respect to other conventional designs in terms of
power consumption and performance.
Keywords-Multiple-Valued Logic; STI; low power ternary
inverter
I. INTRODUCTION
The intrinsic switching behavior of many electronic devices
makes them appropriate for implementing binary digital
integrated circuits. Powerful arithmetic components and tools
have supported binary logic over the last two decades to obtain
the present status [1]. However, the main disadvantages of the
binary integrated circuits, which are the interconnection and
pin-out problems, cause limitations on the number of
connections inside and outside of the circuit [2]. One of the
most effective solutions is to incorporate analog logic
advantages in digital logic and consequently to deal with more
data levels instead of just two, “0” or “1”. This leads to use of
higher radices and consequently Multiple-Valued Logic (MVL)
instead of binary logic, which results in decreasing the number
of interconnections and pin-outs on a given chip.
Using natural base (e=2.718…) leads to the most efficient
implementation of the switching systems among all MVL
systems [3]. However, limitations of hardware implementation
lead designers to use natural radix 3, which reduce complexity
and product cost compared to radix-2 [1].
Inverter is the most fundamental part in any logic and most
of the other basic operators such as NOR and NAND are
realized according to its structure. This fact is valid even for
higher radices especially for radix-3 (ternary). Hence,
designing an efficient ternary inverter cell leads to
978-1-4244-6268-1/10/$26.00 ©2010 IEEE
enhancement of overall system performance. In addition to the
inversion operation, the inverter is also a great driver and its
driving capability is very important. Unlike binary logic, in
ternary logic there are three ways to define the inverter.
Ternary Inverters are defined as follows:
(1)
By choosing the values 0, 1, 2 for i, the ternary inverter can
be Negative (NTI), Standard (STI) and Positive (PTI),
respectively. In this paper, logics "0" and "2" are equivalent to
0 and VDD voltages and logics "0.5", "1", "1.5" are equivalent
to "1/4Vdd", "1/2Vdd" and "3/4Vdd" voltages, respectively.
PTI and NTI inherently are binary inverters because they
produce just two levels, “0” and “2”, at the output. However,
STI is the most efficient inverter, which generates real ternary
logic at the output.
Despite of the large potential of MVL design, it has been
rarely a circuit designer’s choice. However, in this paper, a
novel efficient design for STI is proposed, which has zero static
power consumption and its main structure could be also
extended for realizing higher radix inverters.
The rest of this paper is organized as follows: In section II,
a review of the main previously designs for STI is presented. In
section III, the novel structure is proposed. Section IV includes
experimental results and finally, section V concludes the paper.
II. REVIEW OF THE PREVIOUS CMOS STI DESIGNS
Several types of CMOS STIs have been presented since the
emerging of CMOS technology. However, they utilize large
off-chip resistors and depletion transistors, which are not
suitable in recent technologies. Some other newer designs have
been also presented in the literature [4-7]. However, they have
not presented different hardware structures for STI, compared
to the previous designs. In addition, some new structures for
CMOS analog inverter have been presented, which could be
considered as inverters for any arbitrary radix, including radix-
3 [8-10]. However, an analog inverter may not be really used as
a traditional STI, because of losing the noise immunity in
comparison with real STI.
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 Fig. 1 shows three conventional structures for STI in
CMOS technology [11-13]. In the first design (Fig. 1.a) [11]
two MOS transistors and two resistors implement an inverter
with three outputs, which generates PTI, STI and NTI. If the
input logic becomes “0”, the MP1 transistor becomes turned on
and MN1 becomes turned off. As a result, no current flows in
the resistors and consequently all the outputs go up to logic
“2”. Contrariwise, if the input logic becomes “2”, the MP1
becomes turned off and MN1 becomes turned on. Hence, no
current flows in the resistors and consequently all the outputs
go down to logic “0”. Finally, if the input logic becomes “1”,
which is equivalent to VDD/2 voltage level, both MP1 and MN1
becomes turned on and consequently current could flows in the
resistors. "R" resistors are chosen much larger than the
resistance of the turned on transistors in this condition, so
"Out,PTI" goes up to logic “2”, "Out,NTI" goes down to logic
“0” and "Out,STI" stands in the middle logic between “2” and
“0”, i.e. logic “1”.
In this design, three ternary inverted signals are generated
without need to additional VDD/2 power supply. However, the
static power consumption, almost equal to VDD2/2R, when the
input logic is “1” and using large resistors are the main
disadvantages of this design.
To reduce the number of resistors, another design has been
proposed in [2], which is shown in Fig. 1.b. In this design,
transistors are connected together as the same manner as for
binary inverter but the threshold voltages (Vt) are chosen to be
“1.5” and -“1.5” for NMOS and PMOS, respectively. The
output of the inverter is connected to a VDD/2 power supply by
means of a resistor, which is considerably larger in comparison
with the resistance of the turned on transistors. If the input
logic becomes “0”, MP2 becomes turned on and MN2 becomes
turned off. Hence, the output goes up to logic “2”.
Contrariwise, if the input logic becomes “2”, MP2 becomes
turned off and MN2 becomes turned on. Hence, the output goes
down to logic “0”. Notwithstanding one of the resistors is
removed, needing VDD/2 power supply and static power
consumption, equals to VDD2/2R, when the input logic is “0” or
Figure 1. Different designs for STI. a) With two resistors. b) With one resistor. c) With depletion MOSFET. (Vt (MP1) = -“0.5” (-VDD/4), Vt (MN1) =
“0.5”, Vt (MP2) = -“1.5” (3VDD/4), Vt (MN2) = “1.5”, Vt (MP3) = -“1.5”, Vt (MN3) =“1.5”, Vt (MPD3) = “0.5”, Vt (MND3) = -“0.5”, R >>RON of the MOS
transistors.)
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“2” are the disadvantages of this design.
For eliminating the static power consumption, another
structure has been proposed in [13], which is shown in Fig. 1.c.
In this structure the resistor is replaced with two depletion
transistors. Threshold voltages of the transistors are “0.5”
(VDD/4) for depletion PMOS (DPMOS) and -“0.5” (-VDD/4) for
depletion NMOS (DNMOS). Therefore, the output can only
accede to VDD/2 voltage when the input is between “0.5” and
“1.5” (3VDD/4).
Hence, no static power consumption exists, but needing
VDD/2 power supply still exists. Furthermore, implementing
depletion transistors in standard CMOS process is not feasible
and has been obsolete.
III. PROPOSED DESIGN
All of the previously presented designs have some major
disadvantages such as static power dissipation, using large
resistors, which are hard to implement and occupy large chip
area and unfeasibility of implementation in standard CMOS
technology.
To overcome these disadvantages, a new design for STI is
proposed, which is shown in Fig. 2. The main idea of this
design is based on weighting method, which adds output values
of a PTI and a NTI cell by means of a capacitor divider. Two
pairs of MOSFETs, which implement NTI and PTI, together
with two capacitors, are the materials of this design. For saving
chip area and reaching better performance, transition points of
PTI and NTI are adjusted by setting proper threshold voltages
for MOSFETs instead of changing the aspect ratio of the
transistors.
As a result, low-Vt PMOS and high- Vt NMOS transistors
are utilized for implementing PTI and high-Vt PMOS and low-
Vt NMOS transistors are utilized for implementing NTI.
The outputs of PTI and NTI gates are then connected
together by means of two capacitors which could make a
weighting sum of the relevant inputs. The voltage of the
connection node of capacitors is as follows: Writing a KVL on the main major results in:

VCp,0 + Vinp0 = VCn,0 + Vinn0 (4)

(2)
By applying differential voltage ΔVp on one of inputs as
To have same weighting factor for two Cn and Cp Fig. 3.b, the capacitors of Fig. 3.a will be recharged as follows:
capacitors, they should be identical. Hence the output voltage is
as follows: Qp = Qn (5)

Rewriting a KVL on the main major of Fig. 3.b results in:

(3)

Thus, the output voltage of STI will be the mean value of (6)
the NTI and PTI output voltages.
Now, if the input is in logic “0”, the outputs of PTI and By solving (4) to (6):
NTI will be in logic “2” and the output of STI will be also in
logic “2”. In the same manner, if the input is in logic “2” the
outputs of PTI and NTI will be in logic “0” and the output of (7)
STI will be also in logic “0”.
Finally, if the input is in logic “1” the output of PTI will be
in logic “2” and the output of NTI will be in logic “0” and And finally:
consequently according to (3) the output of STI will be in logic
“1”. No static power consumption, not requiring VDD/2 power (8)
supply, compatibility with standard CMOS technology and
producing three ternary outputs concurrently, are the major
advantages of the proposed design. Equation (8) proves the authenticity of the divider.
Capacitors of the proposed design perform voltage dividing
by charging and discharging the electric load. Therefore, it may
be conceivable that the residue charges may affect the output
voltage, when inputs change.
We do some surveying to investigate authenticity of
capacitance voltage divider. Fig. 3.a shows a capacitance
divider, whose input voltage and charge are taken apart from
capacitors and shown separately as a voltage source.

Figure 2. Schematic of Proposed Design for STI. (Vt (PMOS, PTI) = Figure 3. Capacitance voltage divider with separated input voltage
–“0.5”, Vt (NMOS, PTI) = “1.5”, Vt (PMOS, PTI) = –“1.5”, Vt and capacitor charge. a) Before applying ΔVp voltage. b) After
(PMOS, NTI) = “0.5”) applying ΔVp voltage.

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 Figure 4. Two basic gates. a) Ternary NAND. b) Ternary NOR.
By utilizing the main structure, it is also possible to
implement two other basic ternary gates, NAND and NOR.
Fig. 4.a shows the ternary NAND gate and Fig. 4.b shows the
ternary NOR gate. In Fig. 4.a the four upper transistors
implement Positive Ternary NAND gate (PTNAND).
By utilizing low-Vt PMOS transistors and high-Vt NMOS
transistors, the output of PTNAND goes down to “0” just when
both inputs are in state “2”. Otherwise, output is in state “2”.
Contrariwise, four downer transistors make Negative Ternary
NAND gate (NTNAND). By utilizing high-Vt PMOS
transistors and low-Vt NMOS transistors, the output of
NTNAND goes up to “2” just when both inputs are in state “0”.
Otherwise, output is in state “0”. Finally, connecting these local
outputs by means of two capacitors make a Ternary NAND
gate. In the same manner as for TNAND, the four upper
transistors in Fig. 4.b implement Positive Ternary NOR gate
(PTNOR). By utilizing low-Vt PMOS transistors and high-Vt
NMOS transistors, the output of PTNOR goes up to “2” just
when both inputs are in state “0”. Otherwise, output is in state
“2”.
Contrariwise four downer transistors make Negative
Ternary NOR gate (NTNOR). By using high-Vt PMOS
transistors and low-Vt NMOS transistors, the output of
NTNOR goes down to “2” just when both inputs are in state
“0”. Otherwise, output is in state “2”. At last, connecting these
local outputs by means of two capacitors makes a Ternary
NOR gate.
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IV. SIMULATION RESULTS
In this section the operation and performance of the
proposed design are examined. Simulations have been done
using Synopsys HSPICE tool with standard 90nm CMOS
technology at 0.8V supply voltage. As the power supply
voltage is 0.8V, valid voltage levels are 0V, 0.4V and 0.8V.
The Voltage Transfer Characteristic (VTC) curve of the
proposed STI is shown in Fig. 5, which demonstrates that the
proposed design has good noise margins.
The input and output signals of the proposed STI and also
the proposed TNAND and TNOR gates are shown in Fig. 6 and
Fig. 7 respectively. The output signals prove the authenticity of
the proposed designing method.
The proposed design is compared with the other
conventional and well-known designs in terms of performance
and power consumption. Therefore, simulations are performed
for all designs with the same 90nm CMOS technology. The
resistors of the designs with one and two resistors are adjusted
such that leads to the best simulation results at the outputs.
Furthermore, the widths of the transistors are sized with the
aim of reaching the best power delay product, which is the
product of critical path delay and the average power
consumption [14]. For realizing the capacitors some methods
exist in CMOS technology such as metal-insulator-metal
capacitor (MIMcap) and Metal-Oxide-Semiconductor capacitor
(MOScap) [15]. However, MIMcap consumes an enormous
 The average power consumption is composed of dynamic,
short-circuit and static components [14]. Among all, the static
part is becoming very important specifically in recent
technologies. However, for measuring static power
consumption, as the proposed design omits this part of power,
it has been measured including Leakage power (particularly for
proposed design). Measuring is done at 0.8V power supply
voltage and Wn and Wp the same as values in Table 1. the
results are listed in Table 2. According to the measured results,
the proposed design has very lower static and leakage power
consumption, in comparison with the other introduced before
ternary designs.

Figure. 5. The Voltage Transfer Characteristic of the proposed STI V. CONCLUSION

A novel low-power design for Standard Ternary Inverter is
proposed. This inverter structurally is capable of being used for
implementing other standard ternary functions.
Some of the main advantages of the proposed design
compared with the previously proposed designs are as follows:
1. Containing no ohmic resistors and hence simpler
implementation and very smaller area.
2. Having no static power consumption.
3. Being suitable for low voltage applications.
4. Having low PDP.
5. Capability of being implemented in standard CMOS
Figure 6. The output and input signals of the proposed ternary inverter gat
technology.
6. Generation of all the possible ternary inverted outputs
(Negative, Positive and Standard).

TABLE 1. SIMULATION RESULTS.

L = 90nm VDD = 0.8V

Delay Average Power
Wn=120nm PDP
(50%-50%) Consumption
Wp=120nm (×10-17J)
(×10-12S) (×10-7W)

[11] (R=150kΩ) 52 13.40 6.97

[12] (R=250kΩ) 92 4.50 4.14

The Proposed Design
Cp,n = 1 fF
155 2.25 3.49
Wp = 120nm
Figure 7. The output and input signals of TNAND and TNOR gates. Cp,n = 1 fF
105 3.02 3.17
Wp = 240nm
Cp,n = 1 fF
chip area and is not efficient. Therefore, MOScap is utilized for Wp = 300nm
83 3.50 2.90
realizing the capacitors of the proposed design, which is
available in 90nm CMOS process. Different capacitance values TABLE 2. STATIC POWER DISSIPATION (INCLUDING LEAKAGE) (×10-7W).
can be realized just by changing the length of the MOScap.
[11] (R=150kΩ) , Wn=Wp=120nm 11.71
Table 1 shows the output measured values. By comparing
the values, it is clear that the proposed design has the best [12] (R=250kΩ) , Wn=Wp=120nm 3.02
results among all. The Proposed Design
According to Table 1, simulation results demonstrate the Cp,n = 1 fF , Wn = Wp = 120nm 0.11
superiority of the proposed design in comparison with the
others in terms of power consumption and PDP. Cp,n = 1 fF , Wn = 120nm , Wp = 240nm 0.14

Cp,n = 1 fF , Wn = 120nm , Wp = 300nm 0.15

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