Analog Integrated Circuits & Systems

Phase Locked Loop (PLL)

ELC401A – Fall 2017
Dr. Ahmed Nader

Department of Electronics and Communications Engineering

Faculty of Engineering – Cairo University
 Ripples on VCO Control
• Assume a sinusoidal control voltage
VCONT = Vmcos(ωmt)

• Determine the output waveform and its spectrum

• Variation of the control voltage results in unwanted

components at the output. VCO offers rejection for
high frequency components.
 Phase Alignment using VCO

 Alignment of VCO output phase by changing its frequency

 PLL Waveforms in Locked Condition

 The phase error varies as the

input frequency varies.
 To minimize this error, the gain
KPDKVCO has to be maximized.
Small Transients around Locked Condition
Case I: PLL response to a phase step
Small Transients around Locked Condition
PLL response to a small phase step at the input:

1. The loop tracks the change in the input phase

2. After the loop settles (returns to lock), all of the
parameters return to their original values (except
the total input and output phases)
3. The phase error also returns to its original value (Φ0)
4. The variation in the VCO frequency satisfies:

5. The control voltage of the VCO can be used as a

suitable PLL test point (settling behavior)
Small Transients around Locked Condition
Case II: PLL response to a frequency step
LPF
KPD KVCO

𝜔1 = 𝜔0 + 𝐾𝑉𝐶𝑂 𝑉𝐶1
𝜔2 = 𝜔0 + 𝐾𝑉𝐶𝑂 𝑉𝐶2

Settling time t2 depends on the PLL Bandwidth

Small Transients around Locked Condition

PLL response to a small frequency step at the input:

1. The loop tracks the change in the input frequency

2. After the loop settles (returns to lock), there is a
permanent change in the control voltage and
phase error
Φ2=Φ0+
3. At t=t1, the control voltage reaches its final value
but it continues the transient because the static
phase error has not reached its proper value. Both
frequency and phase “acquisition” has to be
completed.
Example: PLL Response to a voltage step at
VCO input control
𝑉𝑐𝑜𝑛𝑡 = 𝑉𝐿𝑃𝐹 + 𝑉𝑒𝑥
Example: PLL Response to a voltage step at
VCO input control
1. When the loop returns back to lock, the output
frequency ωout has to return to ωin (control voltage
has to stay the same)
2. The change in the output phase (change in phase
error) is given by:

3. This can be used in Frequency Modulation (FM)

 Applications: Frequency Modulation (FM)
Modulation
Signal xBB(t)
modulated
output

Reference
Input PD LPF VCO

Modulation modulated
VCO
Signal xBB(t) output

Why do we need the loop?

- To have a stable frequency at the output
- To reduce excess phase (phase noise) of the VCO
 Effect of VCO Jitter (Phase Noise)

• Jitter manifests as variation of the period (random

phase variations) with time modeled by φn(t)
• Spectrum of φn(t) is called “phase noise”
 VCO Phase Noise

Output Spectrum: Ideal Noisy

PN Specification (dBc/Hz)
 Effect of Phase Noise (PN)

• “Reciprocal Mixing” critical in RX sensing large interferers

• User#1 TX transmitting high power signal

 Applications: Frequency Demodulation
Loop Filter

Vin(t) Freq. Mod. Demodulated

PD LPF
Input output

Vout(t) VCO

Limited PLL Bandwidth

 Applications: Skew Cancellation
 Finds application in very high-frequency/large die size
chips (e.g. microprocessors/DSPs)
 Skew in clock distribution (relative to data) reduces time
budget (setup/hold) for on-chip operations. A PLL is used
to eliminate skew between clock and buffered clock
 Applications: Clock and Data
Recovery (CDR)

Typical High Speed Serial Data Link

Applications:
• Inter/Intra-chip communications: CPU-Memory data BUS, etc.
• Networks: Ethernet, SONNET, SDH, ATM, etc...
• PC I/Os: USB, etc.
Clock and Data Recovery (CDR)
• Due to TX and channel non-idealities signal
integrity is compromised at the RX input

• Non-idealities in data transition time is defined as

excess phase (or jitter).
• The clock and data recovery (CDR) system is
responsible for dealing with jitter
Clock and Data Recovery (CDR)

• The CDR recovers the exact timing of the incoming data.

• The recovered timing is utilized to sample the data at the
optimum time.
• CDR minimizes jitter of the input signal.