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VTU 7th Sem ECE VLSI LAB MANUAL VLSI Lab PDF
VTU 7th Sem ECE VLSI LAB MANUAL VLSI Lab PDF
Prepared by:
BEARYS
P.A. INSTITUTE
COLLEGE OF TECHNOLOGY
OF ENGINEERING
Innoli,
(Affiliated to BoliyarbyVillage
VTU, Recognized AICTE, NBA Accredited)
LABORATORY CERTIFICATE
Part A
Sl.no. Programs Page Remarks
No.
1 Timing verification with gate level simulation of an Inverter
(Sample program)
2 Timing verification with gate level simulation of a Buffer
Part B
Sl.No. Programs PageNo. Remarks
1. Design of an inverter using analog design flow
PART-A
DIGITAL DESIGN BASIC-DIGITAL
DESIGN FLOW
Procedure:
1)Simulation
“Welcome to cadence_tools”
cd dirname
nclaunch
send to waveform
run simulation
2) Synthesis
rc
read_hdl dirname/filename.v
elaborate
gui_show
report timing
report gates
report area
report summary
The writing of the program can be done after activating the insert mode by pressing I in the
program window
Module Program
module inv(a,y);
input a;
output y;
assign y=~a;
endmodule
To save and quit the module program press ESC and type :wq
To quit without saving press ESC and type :q!
Test bench file is used for simulation
Testbench Program
module inv_test;
reg a;
wire y;
inv abc(a,y);
initial
begin
$monitor($time,"y=%d",y);
a=1'b0;
#10 a=1'b1;
#10 a=1'b0;
#10 $finish;
end
endmodule
To save and quit the module program press ESC and type :wq
To quit without saving press ESC and type :q!
Compilation of the module and the testbench program can be
done using the commands
ncvlog invertr.v –mess {Press Enter}
ncvlog invertr_test.v –mess {Press Enter}
To elaborate the program to the libraries
ncelab inv_test –mess {Press Enter}
Simulation can be done by
ncsim inv_test {Press Enter}
To launch the simulation window the command is
nclaunch {Press Enter}
Simulation window :
When the copying is done correctly check whether the file is present in the rtl directory by
following the below given steps
List the files within the directory and check whether the files have been copied properly, if not
repeat the copying procedure again
ls
Return back to the rclabs directory using the below given command
cd ..
Create a log file for the inverter file using the command:
rc –gui –logfile invertr.log
When the inverter log file is executed a new screen will open displaying rc:\> on the screen
The below given command is used to generate the template script from the compiler by
entering:
rc:\>write_template –outfile template.tcl
rc:\>set_attr hdl_search_path {../rtl} /
rc:\>set_attr lib_search_path {../library} /
rc:\>set_attr script_search_path {../tcl} /
rc:\>include setup.g
For Synthesis
Synthesis succeeded
Module Program
Testbench program
Module Program
module transgate(s,x,y);
input x,s;
output y;
reg y;
always@(x or s)
begin
if(x==0 && s==1)
y=1’b0;
if (x==1 && s==1)
y=1’b1;
else
y=1’bz;
end
endmodule
Testbench program
module transgate_test;
reg x,s;
wire y;
transgate al(s,x,y);
initial
begin
$monitor($time,”y=%d”,y);
x=1’b0;
s=1’b0;
#10 x=1’b1;
s=1’b0;
#10 $finish;
end
endmodule
Testbench program
Module Program
Testbench program
Module Program
Testbench Program
Module Program
Testbench Program
Module Program
module nand1(a,b,c);
input a,b;
output c;
assign c=~(a&b);
endmodule
Testbench Program
module nand1_test;
reg a,b;
wire c;
nand1 g1(a,b,c);
initial
begin
$monitor($time,"c=%d",c);
a=1'b0; b=1'b0;
#10 a=1'b0; b=1'b1;
#10 a=1'b1; b=1'b0;
#10 a=1'b1; b=1'b1;
#10 $finish;
end
endmodule
Module Program
module nor1(a,b,c);
input a,b;
output c;
assign c=~(a|b);
endmodule
Testbench program
module nor1_test;
reg a,b;
wire c;
nor1 abc(a,b,c);
initial
begin
$monitor ($time,"c=%d",c);
a=1'b0; b=1'b0;
#10 a=1'b0; b=1'b1;
#10 a=1'b1; b=1'b0;
#10 a=1'b1; b=1'b1;
#10 $finish;
end
endmodule
Module program
module srff2(s,r,clk,q,qb);
input s,r,clk;
inout q,qb;
wire d,e;
nand1 g0(s,clk,d);
nand1 g1(r,clk,e);
nand1 g2(d,qb,q);
nand1 g3(e,q,qb);
endmodule
module nand1(a,b,y);
input a,b;
output y;
assign y=~(a&b);
endmodule
Testbench Program
module srff2_test;
reg s,r,clk;
wire q,qb;
srff2 abc(s,r,clk,q,qb);
initial
clk=1’b0;
always
#10 clk= ~clk;
Initial
begin
$monitor($time, “q=%d”,”qb=%d”,q, qb);
#20 s=1’b0; r=1’b0;
#20 s=1’b0; r=1’b1;
#20 s=1’b1; r=1’b0;
#20 s=1’b1; r=1’b1;
#20 $finish;
end
endmodule
Module Program
module dff1(d,q,qb,clk);
input d,clk;
output q,qb;
reg q,qb;
initial
begin
q=0;
end
always@(posedge clk)
begin
if(d==0)
q=0;
else
q=1;
qb=~q;
end
endmodule
Testbench Program
module dff1_test;
reg d,clk;
wire q,qb;
dff1 al(d,q,qb,clk);
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
$monitor($time,"q=%d","qb=%d",q,qb);
d=1'b0;
#30 d=1'b1;
#30 d=1'b0;
#30 $finish;
end
endmodule
Module Program
module jkff1(jk,clk,q,qb);
input [1:0]jk;
input clk;
output q,qb;
reg q,qb;
initial
begin
q=0;
qb=1;
end
always@(posedge clk)
begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule
Testbench Program
module jkff1_test;
reg clk;
reg [1:0]jk;
wire q,qb;
jkff1 abc(jk,clk,q,qb);
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
$monitor($time,"q=%d","qb=%d",q,qb);
jk=2'b00;
#30 jk=2'b01;
#30 jk=2'b10;
#30 jk=2'b11;
#30 $finish;
end
endmodule
Module Program
module msff(j,k,clk,q,qb);
input j,k,clk;
output q,qb;
reg q,qb,tq;
initial
begin
q=1'b0;
qb=1'b1;
end
always @(clk)
begin
if(clk)
begin
if(j==1'b0 && k==1'b0)
tq=tq;
else if(j==1'b0 && k==1'b1)
tq=1'b0;
else if(j==1'b1 && k==1'b0)
tq=1'b1;
else if(j==1'b1 && k==1'b1)
tq=~tq;
end
if(!clk)
begin
q=tq;
qb=~tq;
end
end
endmodule
Testbench Program
module msff_test;
reg j,k,clk;
wire q,qb,tq;
msff abc(j,k,clk,q,qb);
initial
clk=1'b0;
always
#10 clk=!clk;
initial
begin
$monitor($time,"q=%d","qb=%d",q,qb);
j=1'b0; k=1'b0;
#30 j=1'b0; k=1'b1;
#30 j=1'b1; k=1'b0;
#30 j=1'b1; k=1'b1;
#30 $finish;
end
endmodule
Module program
module tff(tin,rst,clk,q,qbar);
input tin,rst,clk;
output q,qbar;
reg tq;
always@(posedge clk or negedge rst)
begin
if(!rst)
tq=0;
else
begin
if(tin)
tq=~tq;
end
end
assign q=tq;
assign qbar=~q;
endmodule
Testbench Program
Module Program
module par(cin,x,y,sum,cout);
input cin;
input [3:0]x,y;
output [3:0]sum;
output cout;
fulladd g0(cin,x[0],y[0],sum[0],c0);
fulladd g1(c0,x[1],y[1],sum[1],c1);
fulladd g2(c1,x[2],y[2],sum[2],c2);
fulladd g3(c2, x[3],y[3],sum[3],cout);
endmodule
module fulladd(cin,x,y,sum,cout);
input cin,x,y;
output sum,cout;
assign sum=x^y^cin;
assign cout=((x&y)||(x&cin)||(y&cin));
endmodule
Testbench Program
module par_test;
reg [3:0] x,y;
reg cin;
wire [3:0] sum;
wire cout;
par al (cin,x,y,sum,cout);
initial
begin
$monitor($time, "sum=%d",sum);
x=4'b0000; y=4'b0000; cin=1'b0;
#20 x=4'b1111; y=4'b1010;
#40 x=4'b1011; y=4'b0110;
#40 x=4'b1111; y=4'b1111;
#50 $finish;
end
endmodule
Module program
Testbench Program
module syncount_test;
reg cnt,e;
wire [3:0]q;
syncount zzz(cnt,e,q);
initial
begin
cnt=0;
e=1;
end
always #100 cnt=~cnt;
endmodule
Module program
module acount(cnt,e,q);
input cnt,e;
output [3:0]q;
wire q1,q2,q3,q4;
tff aaa(e,cnt,q[0],q1);
tff bbb(e,q1,q[1],q2);
tff ccc(e,q2,q[2],q3);
tff ddd(e,q3,q[3],q4);
endmodule
module tff(t,clk,q,qb);
input t,clk;
output q,qb;
reg q,qb;
initial
begin
q=1’b0;
qb=1’b1;
end
always@(posedge clk)
begin
if(t==0)
q=q;
else
q=~q;
qb=~q;
end
endmodule
Testbench Program
module syncount_test;
reg cnt,e;
wire [3:0]q;
syncount zzz(cnt,e,q);
initial
begin
cnt=0;
e=1;
end
always #100 cnt=~cnt;
endmodule
Module program
module sar(R,L,E,W,clk,q);
parameter n=8;
input[n-1:0] r
input L,E,W,clk;
output [n-1:0] q
reg [n-1:0] q;
integer k;
always@(posedge(clk))
begin
if(L)
q=R;
else if(R)
begin
for(k=n-1;k>0;k=k-1)
q[k-1]<=q[k];
q[n-1]<=W;
end
end
endmodule
Testbench Program
module syncount_test;
reg [7:0]r;
reg l,e,w,clk;
wire [7:0]q;
sar bbb( R(r),L(l),E(e),W(w),clk(clk),q(q));
initial
begin
l=1’b1;
e=1’b0;
r=8’b11110000;
clk=1’b0;
#10 w=1’b1;
l=1’b0;
e=1’b1;
#10 w=1’b0;
end
always #5 clk=~clk;
endmodule
PART-B
ANALOG DESIGN FLOW
The home directory has a cshrc file with paths to the Cadence installation.
2. In a terminal window, type csh at the command prompt to invoke the C shell.
>csh
>source cshrc
Use the installed database to do your work and the steps are as follows:
> cd ~/cadence_DB/cadence_ms_labs_614
> virtuoso
The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the screen.
3. If the “What’s New ...” window appears, close it with the File— Close command.
Lab 1: AN INVERTER
Schematic Capture
Execute Tools – Library Manager in the CIW or Virtuoso window to open Library Manager.
1. In the Library Manager, execute File - New – Library. The new library form appears.
2. In the “New Library” form, type “myDesignLib (arbitrary name)” in the Name section.
4. In the field of Directory section, verify that the path to the library is set
5. In the next “Technology File for New library” form, select option Attach to an existing
techfile and click OK.
6. In the “Attach Design Library to Technology File” form, select gpdk180 from the cyclic
field and click OK.
7. After creating a new library you can verify it from the library manager.
8. If you right click on the “myDesignLib” and select properties, you will find that gpdk180
library is attached as techlib to “myDesignLib”.
In this section we will learn how to open new schematic window in the new “myDesignLib”
library and build the inverter schematic as shown in the figure at the start of this lab.
Do not edit the Library path file and the one above might be different from the path shown in
your form.
3. Click OK when done the above settings. A blank schematic window for the Inverter design
appears.
2. Click on the Browse button. This opens up a Library browser from which you
You will update the Library Name, Cell Name, and the property values
given in the table on the next page as you place each component.
3. After you complete the Add Instance form, move your cursor to the
If you
gpdk180 pmos For M0: Model name = pmos1, W= wp,
place a
L=180n
wrong location.
You can rotate components at the time you place them, or use the
2. Type the following in the Add pin form in the exact order leaving space
vin Input
vout Output
Make sure that the direction field is set to input/output/inputOutput when placing
theinput/output/inout pins respectively and the Usage field is set to schematic.
3. Select Cancel from the Add – pin form after placing the pins.
You can also press the w key, or execute Create — Wire (narrow).
2. In the schematic window, click on a pin of one of your components as the first
point for your wiring. A diamond shape appears over the starting point of this wire.
3. Follow the prompts at the bottom of the design window and click left on the destination point
for your wire. A wire is routed between the source and destination points.
4. Complete the wiring as shown in figure and when done wiring press ESC key in the schematic
window to cancel wiring.
1. Click the Check and Save icon in the schematic editor window.
Symbol Creation
The Cellview From Cellview form appears. With the Edit Options
function active, you can control the appearance of the symbol to generate.
2. Verify that the From View Name field is set to schematic, and the
To View Name field is set to symbol, with the Tool/Data Type set as SchematicSymboL
as shown here
Editing a Symbol
In this section we will modify the inverter symbol to look like a Inverter gate symbol.
1. Move the cursor over the automatically generated symbol, until the green rectangle
2. Click Delete icon in the symbol window, similarly select the red rectangle and
Delete that.
7. Execute Create — Selection Box. In the Add Selection Box form, click Automatic.
8. After creating symbol, click on the save icon in the symbol editor window to save the symbol.
In the symbol editor, execute File — Close to close the symbol view window.
3. Click OK when done. A blank schematic window for the Inverter_Test design appears.
Note: Remember to set the values for VDD and VSS. Otherwise, your circuit will have no
power.
4. Click Create — Wire Name or press L to name the input (Vin) and output (Vout) wires as
6. Leave your Inverter_Test schematic window open for the next section.
Launch – ADE L
Choosing Analyses
This section demonstrates how to view and select the different types of analyses to
The Choosing Analysis form appears. This is a dynamic form, the bottom of the form
c. Click at the moderate or Enabled button at the bottom, and then click Apply.
d. Double click the Select Component, Which takes you to the schematic window.
f. Select “DC Voltage” in the Select Component Parameter form and click OK.
f. In the analysis form type start and stop voltages as 0 to 1.8 respectively.
Set the values of any design variables in the circuit before simulating.
The design is scanned and all variables found in the design are listed.
In a few moments, the wp variable appears in the Table of Design variables section.
Value(Expr) 2u
Click Change and notice the update in the Table of Design Variables.
2. Follow the prompt at the bottom of the schematic window, Click on output net Vout, input net
Vin of the Inverter. Press ESC with the cursor in the schematic after selecting it.
1. Execute Simulation – Netlist and Run in the simulation window to start the
Simulation or the icon, this will create the netlist as well as run the simulation.
2. When simulation finishes, the Transient, DC plots automatically will be popped up along with
log file.
We can save the simulator state, which stores information such as model library file,
outputs, analysis, variable etc. This information restores the simulation environment
2. Set the Save as field to state1_inv and make sure all options are selected under
2. In the Loading State window, set the State name to state1_inv as shown
2. Select Create New option. This gives a New Cell View Form
4. Click OK from the New Cellview form.LSW and a blank layout window appear along with
schematic window.
1. Execute Connectivity – Generate – All from Source or click the icon in the layout
editor window, Generate Layout form appears. Click OK which imports the schematic
components in to the Layout window automatically.
3. To rotate a component, Select the component and execute Edit –Properties. Now select the
degree of rotation from the property edit form.
4. To Move a component, Select the component and execute Edit -Move command.
Making interconnection
2. Move the mouse pointer over the device and click LMB to get the connectivity information,
which shows the guide lines (or flight lines) for the inter connections of the components.
3. From the layout window execute Create – Shape – Path/ Create wire or Create – Shape –
Rectangle (for vdd and gnd bar) and select the appropriate Layers from the LSW window and
Vias for making the inter connections
Creating Contacts/Vias
You will use the contacts or vias to make connections between two different layers.
1. Save your design by selecting File — Save or click to save the layout, and layout
should appear as below.
1. Open the Inverter layout form the CIW or library manger if you have closed that.
The DRC form appears. The Library and Cellname are taken from the current
design window, but rule file may be missing. Select the Technology as gpdk180. This
automatically loads the rule file.
4. A Progress form will appears. You can click on the watch log file to see the log
file.
5. When DRC finishes, a dialog box appears asking you if you want to view your
DRC results, and then click Yes to view the results of this run.
6. If there any DRC error exists in the design View Layer Window (VLW) and Error
Layer Window (ELW) appears. Also the errors highlight in the design itself.
8. You can refer to rule file also for more information, correct all the DRC errors and
9. If there are no errors in the layout then a dialog box appears with No DRC errors
ASSURA LVS
Running LVS
The Assura Run LVS form appears. It will automatically load both the schematic and layout
view of the cell.
4. If the schematic and layout matches completely, you will get the form displaying Schematic
and Layout Match.
5. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this run.
LVS debug form appears, and you are directed into LVS debug environment.
7. In the LVS debug form you can find the details of mismatches and you need to
correct all those mismatches and Re – run the LVS till you will be able to match the
Assura RCX
Running RCX
2. Change the following in the Assura parasitic extraction form. Select output type under Setup
tab of the form.
3. In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode and specify the
Reference node for extraction.
4. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter Ground Nets as
gnd
The RCX progress form appears, in the progress form click Watch log file to see
5. When RCX completes, a dialog box appears, informs you that Assura RCX run
Completed successfully.
6. You can open the av_extracted view from the library manager and view the parasitic.
In this section we will create a config view and with this config view we will run the
The Hierarchy Editor form opens and a New Configuration form opens in front of it.
4. Click Use template at the bottom of the New Configuration form and select
5. Change the Top Cell View to schematic and remove the default entry from the
The hierarchy editor displays the hierarchy for this design using table format.
7. Click the Tree View tab. The design hierarchy changes to tree format. The form should look
like this:
2. In the form, turn on the both cyclic buttons to Yes and click OK.
The Inverter_Test schematic and Inverter_Test config window appears. Notice the
4. Now you need to follow the same procedure for running the simulation. Executing Session–
Load state, the Analog Design Environment window loads the previous state
The simulation takes a few seconds and then waveform window appears.
6. In the CIW, note the netlisting statistics in the Circuit inventory section. This
list includes all nets, designed devices, source and loads. There are no
2. From the functions select delay, this will open the delay data panel.
3. Place the cursor in the text box for Signal1, select the wave button and select
4. Repeat the same for Signal2, and select the output waveform.
5. Set the Threshold value 1 and Threshold value 2 to 0.9, this directs the
7. Click on Evaluate the buffer icon to perform the calculation, note down the value
returned after execution.
In this exercise, we will change the configuration to direct simulation of the av_extracted view
which contains the parasites.
1. Open the same Hierarchy Editor form, which is already set for Inverter_Test config.
2. Select the Tree View icon: this will show the design hierarchy in the tree format.
A pull down menu appears. Select av_extracted view from the Set Instance view menu, the
View to use column now shows av_extracted view.
4. Click on the Recompute the hierarchy icon, the configuration is now updated from
schematic to av_extracted view.
6. From the Analog Design Environment window click Netlist and Run to
7. When simulation completes, note the Circuit inventory conditions, this time the list shows
all nets, designed devices, sources and parasitic devices as well.
8. Calculate the delay again and match with the previous one. Now you can conclude how much
delay is introduced by these parasites, now our main aim should to minimize the delay due to
these parasites so number of iteration takes place for making an optimize layout.
1. Select File – Export – Stream from the CIW menu and Virtuoso Xstream out form appears
change the following in the form.
3. In the StreamOut-Options form select under Layers tab and click OK.
4. In the Virtuoso XStream Out form, click Translate button to start the stream translator.
1. Select File – Import – Stream from the CIW menu and change the following
in the form.
You need to specify the gpdk180_oa22.tf file. This is the entire technology file that
3. In the StreamOut-Options form select under Layers tab and click OK.
4. In the Virtuoso XStream Out form, click Translate button to start the stream translator.
5. From the Library Manager open the Inverter cellview from the GDS_LIB
6. Close all the windows except CIW window, which is needed for the next lab.
Schematic Capture
Simulation
Now, open the ADE L, from LAUNCH ADE L , choose the analysis set the ac response and
run the simulation, from Simulation Run. Next go to ResultsDirect plot select AC dB20
and output from the schematic and press escape.
Schematic Capture
Test Circuit
Layout Capture
Schematic Capture
Frequency= 1K
Test Circuit
Schematic Capture
Frequency= 1K
Note: Remember to set the values for vdd and vss. Otherwise your circuit will have no power.
Test Circuit
Layout Capture
cadence .
What are the other alternative software apart from cadence used for VLSI design?
What is RTL ?
RTL stands for Register Transfer Level. It is a high-level hardware description language (HDL)
used for defining digital circuits. The most popular RTL languages are VHDL and Verilog.
Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study of
ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study
including estimated delays, verify setup, hold and other timing requirements of devices like flip
flops are met
Synthesis: One of the foremost in back end steps where by synthesizing is nothing but converting
VHDL or VERILOG description to a set of primitives or components(as in FPGA'S)to fit into
the target technology. Basically the synthesis tools convert the design description into equations
or components.
Virtuoso
Encounter
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Because we can't get full voltage swing with only NMOS or PMOS .We have to use both of
them together for that purpose.
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for pass
transistor, both voltage levels need to be passed and hence both nmos and pmos need to be used.
What are set up time & hold time constraints? What do they signify?
Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the
signal changes state during this interval, the output of that flip-flop cannot be predictable (called
metastable).
Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If the
signal changes during this interval, the output of that flip-flop cannot be predictable (called
metastable).
clock skew is the time difference between the arrival of active clock edge to different flip-flops’
of the same chip.
Why is not NAND gate preferred over NOR gate for fabrication?
NAND is a better gate for design than NOR because at the transistor level the mobility of
electrons is normally three times that of holes compared to NOR and thus the NAND is a faster
gate. Additionally, the gate-leakage in NAND structures is much lower.
In general multiple MOS devices are made on a common substrate. As a result, the substrate
voltage of all devices is normally equal. However while connecting the devices serially this may
result in an increase in source-to-substrate voltage as we proceed vertically along the series chain
(Vsb1=0, Vsb2 0).Which results Vth2>Vth1.
we try to reverse bias not the channel and the substrate but we try to maintain the drain, source
junctions reverse biased with respect to the substrate so that we don’t loose our current into the
substrate.
In MOSFET, current flow is either due to electrons (n-channel MOS) or due to holes(p-channel
MOS) - In BJT, we see current due to both the carriers..Electrons and holes. BJT is a current
controlled device and MOSFET is a voltage controlled device
In CMOS technology, in digital design, why do we design the size of pmos to be higher than
the nmos. What determines the size of pmos wrt nmos. Though this is a simple question try
to list all the reasons possible?
In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the
carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos
helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd. If the
sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output
node. If we have a larger PMOS than there will be more carriers to charge the node quickly and
overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for
the output node.
In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's
the reason why we need not size them like in CMOS. In CMOS design we have NMOS and
PMOS competing which is the reason we try to size them proportional to their mobility.
What happens when the PMOS and NMOS are interchanged with one another in an
inverter?
If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1
O/P will be degraded 1 Similarly degraded 0
Why are pMOS transistor networks generally used to produce high signals, while nMOS
networks are used to product low signals?
This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS
can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in
pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing.
Testing: A manufacturing step that ensures that the physical device , manufactured from the
synthesized design, has no manufacturing defect.
Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will
perform the given I/O function
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you
avoid Latch Up?
A latch up is the inadvertent creation of a low-impedance path between the power supply rails of
an electronic component, triggering a parasitic structure(The parasitic structure is usually
equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning
of the part. Depending on the circuits involved, the amount of current flow produced by this
mechanism can be large enough to result in permanent destruction of the device due to electrical
over stress - EOS
What is slack?
The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a
particular path. Slack may be +ve or -ve.
What is the Need for DRC? And explain the design rules.
Why germanium is not used generally for nmos and pmos manufacturing
Moores law