E5-471quanta Da0zq0mb6e0 MB PDF

5 4 3 2 1
ZQ0_GDDR3 BWD ULT SYSTEM BLOCK DIAGRAM IV@

EV@
BOM
: iGPU
: Optimus
01
EVG@ : GC6
Dual Channel DDR III VRAM KBL@ : Keyboard backlight
DDR3L-SODIMM CHA 1066/1333/1600 MHZ GPU DDR3 TPM@ : TPM
P14 BRODWELL ULT 15W PCIE-5
N15S-GT P20 8M@ :8M FLASH ROM
N15V-GM 4M@ :4M FLASH ROM
D MCP 1168pins PCI-E x4
N15V-GL D
TX/RX GS@ :G-SENSOR
DDR3L-SODIMM CHB IMC
DC+GT3 X'TAL 27MHz
TDI@ :TOUCH PAD I2C
P15
40 mm X 24 mm
CLK TSU@ :TOUCH SCREEN USB
SATA0 P16~P19 TSI@ :TOUCH SCREEN I2C
SATA - HDD EDP
P27 SATA eDP Conn. P22
eDP
SATA ODD SATA1
P27
DDI2 ITE6513
VGA Conn. P22
P21
DP
DDI1
HDMI Conn. P23
Cardreader USB2-7 Integrated PCH
CONN. 2in 1 GL843L USB3-1
P27 (cardreader) P27
USB3.0/2.0
USB2-6 USB2-0 USB3 Port
CCD(Camera) MB side
P22 P27
C
USB2.0 C
USB2-5 CLK
Touch Screen
P22
PCI-E x1 PCIE-4
USB2-4
Blue Tooth MINI CARD
P24 WLAN+BT
X'TAL P24
32.768KHz
USB2-2
Fingerprint(Option)
P21 PCIE-3
RTL8111 RJ45
P26
I/O board X'TAL 24MHz
USB2-2,3 10/100/1G P26
USB2 IO*2 I/O Board Conn. CLK
P27 P8 BATTERY RTC
P2~P13 X'TAL 25MHz
Azalia IHDA
SPI SPI ROM
LPC
8M+4M P8
EC
B Int. D-MIC ALC283 TPM(option) B
D-MIC BQ24737RGRR TPS51216RUKR Thermal Protection
AUDIO CODEC IT8587 P21 Batery Charger P31 +1.35V_SUS P35 P36
P28 P28 P32
Discharger
TPS51225RUKR TPS54318RTER
+3V/+5V P32 +1.5V P36
TPS51624RSM UP1658RQKF
+VCCIN P33 +VGPU_CORE P37
Universal HP Speaker*2 Power board Touch PAD Fan Driver TPS51211DSCR PS51211DSCR
P28 P28
K/B Con. HALL SENSOR (Fan signal) +1.05V_S5/+1.05V +1.5V_GFX/1.05V_GFX/3V_GFX
P29 (Option) P29 P29 P29 P34 P38
BACKLIGHT
(OPTION) P29
A A
Quanta Computer Inc.

PROJECT : ZQ0
5 4 3
www.china.com 2
Size
Date:
Document Number
Block Diagram
Monday, April 07, 2014
1
Sheet 1 of 46
Rev
3A
5 4 3 2 1
Haswell ULT (DISPLAY,eDP)

U25A HSW_ULT_DDR3L
02
eDP Panel
[23] INT_HDMITX0N C54 C45 EDP_TXN0 EDP_TXN0 [22]
C55 DDI1_TXN0 EDP_TXN0 B46 EDP_TXP0
D [23] INT_HDMITX0P EDP_TXP0 [22] D
B58 DDI1_TXP0 EDP_TXP0 A47 EDP_TXN1
HDMI
[23] INT_HDMITX1N DDI1_TXN1 EDP_TXN1 EDP_TXN1 [22]

[23] INT_HDMITX1P C58 B47 EDP_TXP1 EDP_TXP1 [22]
B55 DDI1_TXP1 EDP_TXP1
[23] INT_HDMITX2N DDI1_TXN2
[23] INT_HDMITX2P A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
[23] INT_HDMICLK- DDI1_TXN3 EDP_TXP2
[23] INT_HDMICLK+ B57 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
[21] CRT_TXN0 DDI2_TXN0
C50 A45 EDP_AUXN
CRT
[21] CRT_TXP0 DDI2_TXP0 EDP_AUXN EDP_AUXN [22]

[21] CRT_TXN1 C53 B45 EDP_AUXP EDP_AUXP [22]
B54 DDI2_TXN1 EDP_AUXP
[21] CRT_TXP1 DDI2_TXP1
C49 D20 EDP_RCOMP R149 24.9/F_4 +VCCIOA_OUT
B50 DDI2_TXN2 EDP_RCOMP A43 DP_UTIL R466 *0_4 PCH_BRIGHT
ITE FAE suggest CAP DDI2_TXP2 EDP_DISP_UTIL
should be at PCH side. A53
B53 DDI2_TXN3
DDI2_TXP3
eDP_RCOMP
R66 *0_4
Trace length < 100 mils
Trace width = 20 mils
1 OF 19 Trace spacing = 25 mils
C C
+3V
HSW_ULT_DDR3L
U25I
PCI_PIRQA# R93 10K_4
PCI_PIRQB# R501 10K_4
PCI_PIRQC# R80 10K_4
PCI_PIRQD# R495 10K_4
[22] PCH_BRIGHT PCH_BRIGHT B8 B9 HDMI_DDCCLK_SW [23] DGPU_SELECT# R485 10K_4
PCH_BLON A9 EDP_BKLCTL DDPB_CTRLCLK C9 CRT_CLK R60 2.2K_4
[22] PCH_BLON EDP_BKLEN DDPB_CTRLDATA HDMI_DDCDATA_SW [23]
PCH_VDDEN C6 eDP SIDEBAND D9 CRT_CLK CRT_DATA R52 2.2K_4
[22] EDP_VDD_EN EDP_VDDEN DDPC_CTRLCLK D11 CRT_DATA TPD_INT#_D R75 TPD@100K_4
DDPC_CTRLDATA
PCI_PIRQA# U6 +3V
PCI_PIRQB# P4 PIRQA/GPIO77 C5
PIRQB/GPIO78 +3V DDPB_AUXN
PCI_PIRQC# N4 +3V B6 CRT_AUX#_C C447 *short_4 CRT_AUXN [21]
PCI_PIRQD# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5
PIRQD/GPIO80 +3V DDPB_AUXP +3V
PCI_PME# AD4 +3V_S5 A6 CRT_AUX_C C446 *short_4 CRT_AUXP [21]
TP110 PME PCIE DDPC_AUXP
TPD_INT#_D U7 +3V
DGPU_SELECT# L1 GPIO55 CRT_AUXN R433 *100K_4
GPIO52 +3V
BOARD_ID4 L3 +3V C8 INT_HDMI_HPD [23]
[10] BOARD_ID4 GPIO54 DDPB_HPD
BOARD_ID1 R5 +3V A8 CRT_HPD [21] CRT_AUXP *100K_4 R432
[10] BOARD_ID1 GPIO51 DDPC_HPD
BOARD_ID2 L4 +3V D6
[10] BOARD_ID2 GPIO53 EDP_HPD EDP_HPD [22]
B B
R61 R454
4.7K_4
9 OF 19 100K_4
1A-13 2013/10/30 move Q42 to page02

+3V change U24.U7 net name.
2
3 1 TPD_INT#_D
[29,30] TPD_INT#
Q46
2N7002K
A A

PROJECT :ZQ0
Size Document Number Rev
3A
Haswell 3/5 (DDI/eDP)
Date: Monday, April 07, 2014 Sheet 2 of 46
5 4 3 2 1
5 4 3 2 1
Change Data and DQS to interleave.
Haswell ULT
U25C HSW_ULT_DDR3L
(DDR3L)
U25D
Haswell Processor (DDR3)
HSW_ULT_DDR3L
03
[14] M_A_DQ0 M_A_DQ0 AH63 AU37 M_A_CLK0# [14]
M_A_DQ1 AH62 SA_DQ0 SA_CLK#0 AV37 M_A_DQ32 AY31 AM38
[14] M_A_DQ1 SA_DQ1 SA_CLK0 M_A_CLK0 [14] [14] M_A_DQ32 SB_DQ0 SB_CK#0 M_B_CLK0# [15]
[14] M_A_DQ2 M_A_DQ2 AK63 AW36 M_A_CLK1# [14] [14] M_A_DQ33 M_A_DQ33 AW31 AN38 M_B_CLK0 [15]
M_A_DQ3 AK62 SA_DQ2 SA_CLK#1 AY36 M_A_DQ34 AY29 SB_DQ1 SB_CK0 AK38
[14] M_A_DQ3 SA_DQ3 SA_CLK1 M_A_CLK1 [14] [14] M_A_DQ34 SB_DQ2 SB_CK#1 M_B_CLK1# [15]
[14] M_A_DQ4 M_A_DQ4 AH61 [14] M_A_DQ35 M_A_DQ35 AW29 AL38 M_B_CLK1 [15]
M_A_DQ5 AH60 SA_DQ4 AU43 M_A_DQ36 AV31 SB_DQ3 SB_CK1
D
[14] M_A_DQ5 SA_DQ5 SA_CKE0 M_A_CKE0 [14] [14] M_A_DQ36 SB_DQ4 D
[14] M_A_DQ6 M_A_DQ6 AK61 AW43 M_A_CKE1 [14] [14] M_A_DQ37 M_A_DQ37 AU31 AY49 M_B_CKE0 [15]
M_A_DQ7 AK60 SA_DQ6 SA_CKE1 AY42 M_A_DQ38 AV29 SB_DQ5 SB_CKE0 AU50
[14] M_A_DQ7 SA_DQ7 SA_CKE2 [14] M_A_DQ38 SB_DQ6 SB_CKE1 M_B_CKE1 [15]
[14] M_A_DQ8 M_A_DQ8 AM63 AY43 [14] M_A_DQ39 M_A_DQ39 AU29 AW49
M_A_DQ9 AM62 SA_DQ8 SA_CKE3 M_A_DQ40 AY27 SB_DQ7 SB_CKE2 AV50
[14] M_A_DQ9 SA_DQ9 [14] M_A_DQ40 SB_DQ8 SB_CKE3
[14] M_A_DQ10 M_A_DQ10 AP63 AP33 M_A_CS#0 [14] [14] M_A_DQ41 M_A_DQ41 AW27
M_A_DQ11 AP62 SA_DQ10 SA_CS#0 AR32 M_A_DQ42 AY25 SB_DQ9 AM32
[14] M_A_DQ11 SA_DQ11 SA_CS#1 M_A_CS#1 [14] [14] M_A_DQ42 SB_DQ10 SB_CS#0 M_B_CS#0 [15]
[14] M_A_DQ12 M_A_DQ12 AM61 [14] M_A_DQ43 M_A_DQ43 AW25 AK32 M_B_CS#1 [15]
M_A_DQ13 AM60 SA_DQ12 AP32 M_A_DQ44 AV27 SB_DQ11 SB_CS#1
[14] M_A_DQ13 SA_DQ13 SA_ODT0 TP38 [14] M_A_DQ44 SB_DQ12
[14] M_A_DQ14 M_A_DQ14 AP61 [14] M_A_DQ45 M_A_DQ45 AU27 AL32 M_B_ODT0
SA_DQ14 SB_DQ13 SB_ODT0 TP43
[14] M_A_DQ15 M_A_DQ15 AP60 AY34 M_A_RAS# [14] [14] M_A_DQ46 M_A_DQ46 AV25
M_B_DQ0 AP58 SA_DQ15 SA_RAS AW34 M_A_DQ47 AU25 SB_DQ14 AM35
[15] M_B_DQ0 SA_DQ16 SA_WE M_A_WE# [14] [14] M_A_DQ47 SB_DQ15 SB_RAS M_B_RAS# [15]
[15] M_B_DQ1 M_B_DQ1 AR58 AU34 M_A_CAS# [14] [15] M_B_DQ32 M_B_DQ32 AM29 AK35 M_B_WE# [15]
M_B_DQ2 AM57 SA_DQ17 SA_CAS M_B_DQ33 AK29 SB_DQ16 SB_WE AM33
[15] M_B_DQ2 SA_DQ18 [15] M_B_DQ33 SB_DQ17 SB_CAS M_B_CAS# [15]
[15] M_B_DQ3 M_B_DQ3 AK57 AU35 M_A_BS#0 [14] [15] M_B_DQ34 M_B_DQ34 AL28
M_B_DQ4 AL58 SA_DQ19 SA_BA0 AV35 M_B_DQ35 AK28 SB_DQ18 AL35
[15] M_B_DQ4 SA_DQ20 SA_BA1 M_A_BS#1 [14] [15] M_B_DQ35 SB_DQ19 SB_BA0 M_B_BS#0 [15]
[15] M_B_DQ5 M_B_DQ5 AK58 AY41 M_A_BS#2 [14] [15] M_B_DQ36 M_B_DQ36 AR29 AM36 M_B_BS#1 [15]
M_B_DQ6 AR57 SA_DQ21 SA_BA2 M_B_DQ37 AN29 SB_DQ20 SB_BA1 AU49
[15] M_B_DQ6 SA_DQ22 M_A_A[15:0] [14] [15] M_B_DQ37 SB_DQ21 SB_BA2 M_B_BS#2 [15]
[15] M_B_DQ7 M_B_DQ7 AN57 AU36 M_A_A0 [15] M_B_DQ38 M_B_DQ38 AR28 M_B_A[15:0] [15]
M_B_DQ8 AP55 SA_DQ23 SA_MA0 AY37 M_A_A1 M_B_DQ39 AP28 SB_DQ22 AP40 M_B_A0
[15] M_B_DQ8 SA_DQ24 SA_MA1 [15] M_B_DQ39 SB_DQ23 SB_MA0
[15] M_B_DQ9 M_B_DQ9 AR55 AR38 M_A_A2 [15] M_B_DQ40 M_B_DQ40 AN26 AR40 M_B_A1
M_B_DQ10 AM54 SA_DQ25 SA_MA2 AP36 M_A_A3 M_B_DQ41 AR26 SB_DQ24 SB_MA1 AP42 M_B_A2
[15] M_B_DQ11 M_B_DQ11 AK54 AU39 M_A_A4 [15] M_B_DQ42 M_B_DQ42 AR25 AR42 M_B_A3
M_B_DQ12 AL55 SA_DQ27 SA_MA4 AR36 M_A_A5 M_B_DQ43 AP25 SB_DQ26 SB_MA3 AR45 M_B_A4
[15] M_B_DQ13 M_B_DQ13 AK55 AV40 M_A_A6 [15] M_B_DQ44 M_B_DQ44 AK26 AP45 M_B_A5
M_B_DQ14 AR54 SA_DQ29 SA_MA6 AW39M_A_A7 M_B_DQ45 AM26 SB_DQ28 SB_MA5 AW46M_B_A6
[15] M_B_DQ15 M_B_DQ15 AN54 DDR CHANNEL A AY39 M_A_A8 [15] M_B_DQ46 M_B_DQ46 AK25 AY46 M_B_A7
M_A_DQ16 AY58 SA_DQ31 SA_MA8 AU40 M_A_A9 M_B_DQ47 AL25 SB_DQ30 SB_MA7 AY47 M_B_A8
[14] M_A_DQ16 SA_DQ32 SA_MA9 [15] M_B_DQ47 SB_DQ31 SB_MA8
[14] M_A_DQ17 M_A_DQ17 AW58 AP35 M_A_A10 [14] M_A_DQ48 M_A_DQ48 AY23 DDR CHANNEL B AU46 M_B_A9
M_A_DQ18 AY56 SA_DQ33 SA_MA10 AW41M_A_A11 M_A_DQ49 AW23 SB_DQ32 SB_MA9 AK36 M_B_A10
[14] M_A_DQ18 SA_DQ34 SA_MA11 [14] M_A_DQ49 SB_DQ33 SB_MA10
[14] M_A_DQ19 M_A_DQ19 AW56 AU41 M_A_A12 [14] M_A_DQ50 M_A_DQ50 AY21 AV47 M_B_A11
M_A_DQ20 AV58 SA_DQ35 SA_MA12 AR35 M_A_A13 M_A_DQ51 AW21 SB_DQ34 SB_MA11 AU47 M_B_A12
[14] M_A_DQ21 M_A_DQ21 AU58 AV42 M_A_A14 [14] M_A_DQ52 M_A_DQ52 AV23 AK33 M_B_A13
C M_A_DQ22 AV56 SA_DQ37 SA_MA14 AU42 M_A_A15 M_A_DQ53 AU23 SB_DQ36 SB_MA13 AR46 M_B_A14 C
[14] M_A_DQ23 M_A_DQ23 AU56 [14] M_A_DQ54 M_A_DQ54 AV21 AP46 M_B_A15
M_A_DQ24 AY54 SA_DQ39 AJ61 M_A_DQS#0 M_A_DQ55 AU21 SB_DQ38 SB_MA15
[14] M_A_DQ24 SA_DQ40 SA_DQSN0 M_A_DQS#0 [14] [14] M_A_DQ55 SB_DQ39
[14] M_A_DQ25 M_A_DQ25 AW54 AN62 M_A_DQS#1 M_A_DQS#1 [14] [14] M_A_DQ56 M_A_DQ56 AY19 AW30 M_A_DQS#4 M_A_DQS#4 [14]
M_A_DQ26 AY52 SA_DQ41 SA_DQSN1 AM58 M_B_DQS#0 M_A_DQ57 AW19 SB_DQ40 SB_DQSN0 AV26 M_A_DQS#5
[14] M_A_DQ26 SA_DQ42 SA_DQSN2 M_B_DQS#0 [15] [14] M_A_DQ57 SB_DQ41 SB_DQSN1 M_A_DQS#5 [14]
[14] M_A_DQ27 M_A_DQ27 AW52 AM55 M_B_DQS#1 M_B_DQS#1 [15] [14] M_A_DQ58 M_A_DQ58 AY17 AN28 M_B_DQS#4 M_B_DQS#4 [15]
M_A_DQ28 AV54 SA_DQ43 SA_DQSN3 AV57 M_A_DQS#2 M_A_DQ59 AW17 SB_DQ42 SB_DQSN2 AN25 M_B_DQS#5
[14] M_A_DQ28 SA_DQ44 SA_DQSN4 M_A_DQS#2 [14] [14] M_A_DQ59 SB_DQ43 SB_DQSN3 M_B_DQS#5 [15]
[14] M_A_DQ29 M_A_DQ29 AU54 AV53 M_A_DQS#3 M_A_DQS#3 [14] [14] M_A_DQ60 M_A_DQ60 AV19 AW22 M_A_DQS#6 M_A_DQS#6 [14]
M_A_DQ30 AV52 SA_DQ45 SA_DQSN5 AL43 M_B_DQS#2 M_A_DQ61 AU19 SB_DQ44 SB_DQSN4 AV18 M_A_DQS#7
[14] M_A_DQ30 SA_DQ46 SA_DQSN6 M_B_DQS#2 [15] [14] M_A_DQ61 SB_DQ45 SB_DQSN5 M_A_DQS#7 [14]
[14] M_A_DQ31 M_A_DQ31 AU52 AL48 M_B_DQS#3 M_B_DQS#3 [15] [14] M_A_DQ62 M_A_DQ62 AV17 AN21 M_B_DQS#6 M_B_DQS#6 [15]
M_B_DQ16 AK40 SA_DQ47 SA_DQSN7 M_A_DQ63 AU17 SB_DQ46 SB_DQSN6 AN18 M_B_DQS#7
[15] M_B_DQ16 SA_DQ48 [14] M_A_DQ63 SB_DQ47 SB_DQSN7 M_B_DQS#7 [15]
[15] M_B_DQ17 M_B_DQ17 AK42 AJ62 M_A_DQS0 M_A_DQS0 [14] [15] M_B_DQ48 M_B_DQ48 AR21
M_B_DQ18 AM43 SA_DQ49 SA_DQSP0 AN61 M_A_DQS1 M_B_DQ49 AR22 SB_DQ48 AV30 M_A_DQS4
[15] M_B_DQ18 SA_DQ50 SA_DQSP1 M_A_DQS1 [14] [15] M_B_DQ49 SB_DQ49 SB_DQSP0 M_A_DQS4 [14]
[15] M_B_DQ19 M_B_DQ19 AM45 AN58 M_B_DQS0 M_B_DQS0 [15] [15] M_B_DQ50 M_B_DQ50 AL21 AW26 M_A_DQS5 M_A_DQS5 [14]
M_B_DQ20 AK45 SA_DQ51 SA_DQSP2 AN55 M_B_DQS1 M_B_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 M_B_DQS4
[15] M_B_DQ20 SA_DQ52 SA_DQSP3 M_B_DQS1 [15] [15] M_B_DQ51 SB_DQ51 SB_DQSP2 M_B_DQS4 [15]
[15] M_B_DQ21 M_B_DQ21 AK43 AW57 M_A_DQS2 M_A_DQS2 [14] [15] M_B_DQ52 M_B_DQ52 AN22 AM25 M_B_DQS5 M_B_DQS5 [15]
M_B_DQ22 AM40 SA_DQ53 SA_DQSP4 AW53 M_A_DQS3 M_B_DQ53 AP21 SB_DQ52 SB_DQSP3 AV22 M_A_DQS6
[15] M_B_DQ22 SA_DQ54 SA_DQSP5 M_A_DQS3 [14] [15] M_B_DQ53 SB_DQ53 SB_DQSP4 M_A_DQS6 [14]
[15] M_B_DQ23 M_B_DQ23 AM42 AL42 M_B_DQS2 M_B_DQS2 [15] [15] M_B_DQ54 M_B_DQ54 AK21 AW18 M_A_DQS7 M_A_DQS7 [14]
M_B_DQ24 AM46 SA_DQ55 SA_DQSP6 AL49 M_B_DQS3 M_B_DQ55 AK22 SB_DQ54 SB_DQSP5 AM21 M_B_DQS6
[15] M_B_DQ24 SA_DQ56 SA_DQSP7 M_B_DQS3 [15] [15] M_B_DQ55 SB_DQ55 SB_DQSP6 M_B_DQS6 [15]
[15] M_B_DQ25 M_B_DQ25 AK46 [15] M_B_DQ56 M_B_DQ56 AN20 AM18 M_B_DQS7 M_B_DQS7 [15]
M_B_DQ26 AM49 SA_DQ57 AP49 M_B_DQ57 AR20 SB_DQ56 SB_DQSP7
[15] M_B_DQ26 SA_DQ58 SM_VREF_CA +VREF_CA_CPU [15] M_B_DQ57 SB_DQ57
[15] M_B_DQ27 M_B_DQ27 AK49 AR51 +VREFDQ_SA_M3 [15] M_B_DQ58 M_B_DQ58 AK18
M_B_DQ28 AM48 SA_DQ59 SM_VREF_DQ0 AP51 M_B_DQ59 AL18 SB_DQ58
[15] M_B_DQ28 SA_DQ60 SM_VREF_DQ1 +VREFDQ_SB_M3 [15] M_B_DQ59 SB_DQ59
[15] M_B_DQ29 M_B_DQ29 AK48 [15] M_B_DQ60 M_B_DQ60 AK20
M_B_DQ30 AM51 SA_DQ61 M_B_DQ61 AM20 SB_DQ60
[15] M_B_DQ30 SA_DQ62 [15] M_B_DQ61 SB_DQ61
[15] M_B_DQ31 M_B_DQ31 AK51 [15] M_B_DQ62 M_B_DQ62 AR18
SA_DQ63 M_B_DQ63 AP18 SB_DQ62
[15] M_B_DQ63 SB_DQ63
B B
3 OF 19 4 OF 19
A A

PROJECT : ZQ0
3A
Haswell 2/5 (DDR3 I/F)
5 4 3 2 1
5 4 3 2 1
04
H_PECI (50ohm)
Haswell ULT (SIDEBAND)
Route on microstrip only
D
Spacing >18 mils D
Trace Length: 0.4~6.125 iches
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches HSW_ULT_DDR3L
U25B
CPU_PLTRST# (50ohm)
Trace Length: 10~17 inches PROC_DETECT D61
TP79 PROC_DETECT
CATERR# K61 MISC
TP25 N62 CATERR J62
[30] H_PECI H_PECI XDP_PRDY# XDP_PRDY# [13]
PECI PRDY K62 XDP_PREQ#
PREQ XDP_PREQ# [13]
E60 XDP_TCK0 TCK,TMS
PROC_TCK E61 XDP_TCK0 [8,13]
XDP_TMS_CPU Trace Length < 9000mils
H_PROCHOT# R525 56_4 H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# XDP_TMS_CPU [13]
[30,31,35] H_PROCHOT# PROCHOT PROC_TRST XDP_TRST# [8,13]
THERMAL F63 XDP_TDI_CPU
PROC_TDI F62 XDP_TDO_CPU XDP_TDI_CPU [13]
PROC_TDO XDP_TDO_CPU [13]
H_PWRGOOD_R C61
PROCPWRGD PWR
J60 XDP_BPM#0
BPM#0 H60 XDP_BPM#0 [13]
XDP_BPM#1
BPM#1 XDP_BPM#1 [13]
SM_RCOMP[0:2] H61 XDP_BPM#2 BPM#[0:7]
BPM#2 H62 TP82
Trace length < 500 mils XDP_BPM#3 Trace Length 1~6 inches
BPM#3 TP80
SM_RCOMP_0 AU60 K59 XDP_BPM#4
Trace width = 12~15 mils SM_RCOMP_1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM#5
TP23 Length match < 300 mils
C
Trace spacing = 20 mils SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM#6
TP81
C
SM_RCOMP2 BPM#6 TP124
CPU_DRAMRST# AV15 DSW J61 XDP_BPM#7
AV61 SM_DRAMRST BPM#7 TP24
DDR_PG_CTRL
SM_PG_CNTL1
2 OF 19
B B
DRAM COMP XDP PU/PD DDR3L ODT GENERATION +1.35V_SUS

+1.05V_VCCST
R157 200/F_4 SM_RCOMP_0 +5V_S5 +3V_SUS U13
XDP_TDO_CPU R141 51_4
5 1
VCC NC
1
R155 120/F_4 SM_RCOMP_1
1
XDP_TCK0 R62 51_4
XDP_TRST# R555 *51_4 R306 R695 C333 2 R316 *short_4 DDR_PG_CTRL
R148 100/F_4 SM_RCOMP_2 220K/F_4 *220K/F_4 0.1u/10V_4 A
2
2
2
4 3
[34] DDR_VTTT_PG_CTRL Y GND
+1.35V_SUS 74AUP1G07GW
PU/PD of CPU DRAMRST
3
+1.35V_SUS R321 66.5/F_4
+VCCIO_OUT M_A_ODT0_DIMM [14]
2 Q35
2N7002K R322 66.5/F_4 M_A_ODT1_DIMM [14]
1
H_PROCHOT# R522 *62_4

R182 R323 66.5/F_4 M_B_ODT0_DIMM [15]
+1.05V_VCCST 470_4
1
A R325 66.5/F_4 A
M_B_ODT1_DIMM [15]
R524 62_4
CPU DRAM
2
CPU_DRAMRST# R227 *short_4 DDR3_DRAMRST# [14,15]

1
H_PWRGOOD_R R51 10K_4 C271

*0.1u/10V_4
PROJECT : ZQ0
2

3A
Haswell 1/5 (PEG/DMI/FDI)
Date: Tuesday, April 08, 2014 Sheet 4 of 46
5 4 3 2 1
5 4 3 2 1
VDDQ Output Decoupling Recommendations

VCCST PWRGD
330uFx2
22uFx11
10uFx10
7343
0805
0805
BOT socket side
5 onTOP, 6 on BOT inside socket cavity
5 onTOP, 5 on BOT inside socket cavity +1.05V_VCCST
CRB is via +1.05V PG
+3V_S5
5
U29
1
05
VCC NC
C502
R601 0.1u/10V_4 2 VCCST_PWRGD_EN
10K_4 A
D Haswell ULT (POWER) VCCST_PWRGD R603 *short_4VCCST_PWRGD_R 4

Y GND
3 D
C498 74AUP1G07GW
*0.1u/10V_4
+ C422
*470u/2V_7343 R602 *0_4 HWPG_1.05V_EC
+1.35V_SUS
3
HSW_ULT_DDR3L
U25L
+1.35V_CPU 1.4A +VCCIN 32A Q41 Reserve from EC
TP29 ULT_RVSD_61 L59 C36
RSVD VCC +VCCIN
+1.35V_CPU TP9 ULT_RVSD_62 J58 C40 2 HWPG_1.05V_EC# [30]
RSVD VCC C44
AH26 VCC C48 C190 C46 C73 C100 C113 C75
C476 C478 C178 C477 C475 C480 AJ31 VDDQ VCC C52 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 *2N7002K
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AJ33 VDDQ VCC C56
1
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29 R618 *short_4
VDDQ VCC PCH_PWROK [7,30]
+ AY35 E31 VCCST_PWRGD_EN R617 *0_4
VDDQ VCC EC_PWROK [7,30]
C486 C145 C157 C479 C184 AY40 E33 C133 C136 C132 C201 C140 C202
AY44 VDDQ VCC E35
*470u/2V_7343 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 1A-6 2013/10/21 Del APWORK.
AY50 VDDQ VCC E37
VDDQ VCC E39
F59 VCC E41
+VCCIN VCC VCC
TP16 ULT_RVSD_63 N58 E43
R583 100/F_4 ULT_RVSD_64 AC58 RSVD VCC E45
+VCCIN TP41 RSVD VCC
C E47 C
R423 *short_4 VCC_SENSE_R E63 VCC E49 C135 C167 C127 C169 C165 C171
[35] VCC_SENSE VCC_SENSE VCC
TP42 ULT_RVSD_65 AB23 E51 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8
A59 RSVD VCC E53
300mA +VCCIO_OUT VCCIO_OUT VCC
300mA E20 E55 +1.05V +VCCIO_OUT
+VCCIOA_OUT VCCIOA_OUT VCC
TP18 ULT_RVSD_66 AD23 E57
ULT_RVSD_67 AA23 RSVD VCC F24 R55 *0_8
TP14 RSVD VCC
TP50 ULT_RVSD_68 AE59 F28
R65 *10K_4 RSVD VCC F32
+1.05V_VCCST VCC
H_CPU_SVIDART# L62 F36 C204 C125 C172 C170 C203 C130 C118
VRON_CPU R76 10K_4 IMVP_PWRGD H_CPU_SVIDCLK N63 VIDALERT HSW ULT POWER VCC F40 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 *4.7u/6.3V_6
H_CPU_SVIDDAT L63 VIDSCLK VCC F44
VCCST_PWRGD B59 VIDSOUT VCC F48
[13] VCCST_PWRGD F60 VCCST_PWRGD VCC F52
VRON_CPU
[35] VRON_CPU IMVP_PWRGD C59 VR_EN VCC F56
[10,35] IMVP_PWRGD VR_READY VCC G23
D63 VCC G25
R72 *short_4 PWR_DEBUG_R H59 VSS VCC G27 C137 C126 C71 C129 C74 C128
[13] PWR_DEBUG PWR_DEBUG VCC
P62 G29 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8
R68 150_6 ULT_RVSD_69 P60 VSS VCC G31
+1.05V_VCCST TP17 RSVD_TP VCC
ULT_RVSD_70 P61 G33
TP31
ULT_RVSD_71 N59 RSVD_TP VCC G35 SVID Layout note: need routing together
TP22 RSVD_TP VCC and ALERT need between CLK and DATA.
TP85 ULT_RVSD_72 N61 G37
ULT_RVSD_73 T59 RSVD_TP VCC G39
TP32 RSVD VCC
TP49 ULT_RVSD_74 AD60 G41
ULT_RVSD_75 AD59 RSVD VCC G43 +VCCIO_OUT +1.05V_VCCST
TP44 RSVD VCC VCC Output Decoupling Recommendations
TP36 ULT_RVSD_76 AA59 G45
ULT_RVSD_77 AE60 RSVD VCC G47
TP40 RSVD VCC 470uFx4 7343 TOP socket side
B TP37 ULT_RVSD_78 AC59 G49 B
ULT_RVSD_79 AG58 RSVD VCC G51
TP39 RSVD VCC 22uFx8 0805 4 on TOP, 4 on BOT near socket edge
TP20 ULT_RVSD_80 U59 G53 R535 R540
ULT_RVSD_81 V59 RSVD VCC G55 *130/F_4 130/F_4
TP34 RSVD VCC 22uFx11 0805 TOP, inside socket cavity
G57
AC22 VCC H23 H_CPU_SVIDDAT R528 *short_4
VCCST VCC 10uFx11 0805 BOT, inside socket cavity VR_SVID_DATA [35]
+1.05V +1.05V_VCCST AE22 J23
AE23 VCCST VCC K23
+1.05V_VCCST VCCST VCC Place PU resistor
R45 *SHORT_8 K57 close to CPU
AB57 VCC L22 +1.05V_VCCST +VCCIO_OUT
AD57 VCC VCC M23
C150 AG57 VCC VCC M57
*4.7u/6.3V_6 C24 VCC VCC P57
C28 VCC VCC U57
VCC VCC Place PU resistor
C32 W57 close to CPU R539 R534
+VCCIN VCC VCC 75_4 *75_4
12 OF 19
H_CPU_SVIDART# R502 43_4 VR_SVID_ALERT# [35]
+3V
HWPG_1.05V for DDR=1.5V
H_CPU_SVIDCLK R548 *short_4 VR_SVID_CLK [35]
+3V
R236
*4.7K_4
A A
R229
HWPG_1.05V [30]
*4.7K_4
3
3
R247
R225 *4.7K_4 2 2 *100K/F_4
+1.05V
Q30
1
C268 *MMBT3904-7-F C270 Q33

PROJECT : ZQ0
1
*1000p/50V_4 *1000p/50V_4 *DTC144EU

10/30 reserve Size Document Number Rev
DDR=1.5V ,This block POP Haswell 4/5 (POWER) 3A

5 4 3 2 1
5 4 3 2 1
Haswell ULT
U25S
(CFG,RSVD)
HSW_ULT_DDR3L
06
D CFG0 AC60 AV63 D
[13] CFG0 CFG0 RSVD_TP
CFG1 AC62 AU63
CFG2 AC63
[13] CFG2 CFG2
[13] CFG3 CFG3 AA63
CFG4 AA60 CFG3 C63
[8,13] CFG4 CFG4 RSVD_TP
[13] CFG5 CFG5 Y62 C62
CFG6 Y61 CFG5 RSVD_TP B43
[13] CFG6 CFG6 RSVD
CFG7 Y60
[13] CFG7 CFG7
[13] CFG8 CFG8 V62 A51
CFG9 V61 CFG8 RSVD_TP B51
[13] CFG10 CFG10 V60
CFG11 U60 CFG10 L60
CFG12 T63
[13] CFG12 CFG12 RESERVED
[13] CFG13 CFG13 T62 N60
CFG14 T61 CFG13 RSVD
[13] CFG14 CFG14
[13] CFG15 CFG15 T60 W23
CFG15 RSVD Y22
NOA_STBN_0 AA62 RSVD AY15 OPI_COMP1 R576 49.9/F_4
[13] NOA_STBN_0 CFG16 PROC_OPI_RCOMP
NOA_STBN_1 U63
[13] NOA_STBN_1 AA61 CFG18 AV62
NOA_STBP_0
[13] NOA_STBP_0 CFG17 RSVD
NOA_STBP_1 U62 D58
[13] NOA_STBP_1 CFG19 RSVD
R515 49.9/F_4 CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
C VSS C
REFPKG_OCC A5
TP100 RSVD P20
1A-10 20131025 reserve A5 ball to 100k PU 3VPCU.E1 RSVD R20
1A-12 20131028 reserve A5 ball toTP. D1 RSVD RSVD
J20 RSVD
H18 RSVD
R452 8.2K_4 TD_IREF B12 RSVD
TD_IREF
19 OF 19
Processor Strapping
1 0
CFG0 CFG0
(DEFAULT) NORMAL OPERATION; NO STALL STALL R134 *1K_4
EAR-STALL/NOT STALL RESET SEQUENCE
AFTER PCU PLL IS LOCKED
CFG1 CFG1
(DEFAULT) NORMAL OPERATION PCH-LESS MODE R552 *1K_4
PCH/ PCH LESS MODE SELECTION
B B
CFG3 DISABLED ENABLED CFG3 R549 *1K_4

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY) NO PHYSICAL DISPLAY PORT ATTACHED AN EXTERNAL DISPLAY PORT DEVICE IS
TO CONNECTED
EMBEDDED DISPLAY PORT TO THE EMBEDDED DISPLAY PORT
CFG 8 DISABLED(DEFAULT); IN THIS CASE, NOA ENABLED; NOA WILL BE AVAILABLE

ALLOW THE USE OF NOA ON LOCKED UNITS WILL BE DISABLED IN LOCKED UNITS AND REGARDLESS OF THE LOCKING OF THE UNIT CFG8 R537 *1K_4
ENABLED IN UN-LOCKED UNITS
CFG9 NO VR SUPPORTING SVID IS PRESENT. THE CFG9

VRS SUPPORTING SVID PROTOCOL ARE R532 *1K_4
NO SVID PROTOCOL CAPABLE VR CHIP WILL NOT GENERATE (OR RESPOND TO)
CONNECTED PRESENT SVID ACTIVITY
A A
CFG10 POWER FEATURES ACTIVATED POWER FEATURES (ESPECIALLY CLOCK
CFG10 R126 *1K_4
SAFE MODE BOOT DURING RESET GATINE ARE NOT ACTIVATED
PROJECT : ZQ0
3A
Haswell 5/5 (CFG/GND)
5 4 3 2 1
5 4 3 2 1
[30]
[13]
PCH_SUSACK#
PCH_SUSPWRACK R173
SYS_RESET#
R168 *0_4
*0_4 SUSACK#_R
SYS_RESET#
AK2
U25H
Haswell ULT PCH (PM)
HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
AW7 DSWVREN
Deep Sx
DSWVREN [8]
07
C207 *1u/6.3V_4 AC3 SUSACK DSWVRMEN AV5 DPWROK_R R599 *0_4
SYS_RESET DPWROK DPWROK [30]
SYS_PWROK R613 *short_4 SYS_PWROK_R AG2 DSW AJ5 PCIE_LAN_WAKE# PCIE_LAN_WAKE# [26]
R609 *0_4 R604 *0_4 EC_PWROK_R AY7 SYS_PWROK WAKE
D D
EC_PWROK R608 *0_4 R605 *0_4 APWROK_R AB5 PCH_PWROK
PCI_PLTRST# AG7 APWROK V5 CLKRUN#
PLTRST +3V_S5 +3V CLKRUN/GPIO32 AG4 GPIO61
CLKRUN# [21,30]
+3V_S5 SUS_STAT/GPIO61 TP123
+3V_S5 AE6 PCH_SUSCLK
SUSCLK/GPIO62 TP11
DSW AP5 PCH_SLP_S5# PCH_SLP_S5# [13]
R596 *short_4 PCH_RSMRST# AW6 SLP_S5/GPIO63
[30] RSMRST# RSMRST
[30] PCH_SUSPWRACK_R R692 *short_4 PCH_SUSPWRACK AV4 +3V_S5
R274 *short_4 PCH_PWRBTN# AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6 SUSC#
[30] DNBSWON# PWRBTN DSW DSW SLP_S4 SUSC# [13,30]
R277 *short_4 PCH_ACPRESENT AJ8 AT4 SUSB#
[31] ACPRESENT
PCH_BATLOW# AN4 ACPRESENT/GPIO31 DSW DSW SLP_S3 AL5 PCH_SLP_A#
SUSB# [13,30]
1C1-1 2014/02/19 add R692 for SUSPWRACK# to EC. BATLOW/GPIO72 DSW DSW SLP_A PCH_SLP_A# [13]
PCH_SLP_S0#_R AF3 +3V_S5 DSW AP4 PCH_SLP_SUS#
TP111 SLP_S0 SLP_SUS PCH_SLP_SUS# [30]
PCH_SLP_WLAN# AM5 DSW DSW AJ7 PCH_SLP_LAN#
TP51 SLP_WLAN/GPIO29 SLP_LAN TP12
8 OF 19
C C
Power Sequence R610 *short_4 APWROK_R
[30] APWORK
[5,30] PCH_PWROK R353 *short_4 EC_PWROK_R
EC_PWROK R612 *0_4 SYS_PWROK_R

R595 Speed up 250ms to boot up R606
100K_4
RSMRST# R597 *short_4 DPWROK_R for EC power on 250 ms 10K_4
Non Deep Sx
PCH PM PU/PD PLTRST# Buffer Deep Sx Circuit Non Deep Sx

+3V +3V
R300 *Short_6
C213 0.1u/10V_4
CLKRUN# R505 8.2K_4 +3V_S5 +3VCC_S5
5
SYS_RESET# R516 10K_4

2 1 3
4 PLTRST# [13,16,21,24,26,27,30]
B PCI_PLTRST# 1 R302 Q34 B
PCH_RSMRST# R590 10K_4 C237 *100K_4 *AO3413
2
SYS_PWROK R616 *10K_4 U6 *0.33u/10V_6
3
DPWROK_R R598 100K/F_4 TC7SH08FU R175

PCH_SUSCLK R110 *10K_4 100K_4
R303
*0_6
+3V_S5
3
PCH_SUSPWRACK R176 *10K_4
GPIO61 R521 *10K_4 SYSPWOK
1C-5 2014/01/16 Change R264 from 10k to 1k +3V_S5 PCH_SLP_SUS# 2
for wake on lan issue.
+3V_S5 C511 *0.1u/10V_4 Q27
*2N7002K
PCH_ACPRESENT R122 10K_4
1
5
PCH_BATLOW# R262 8.2K_4

PCIE_LAN_WAKE# R264 1K_4 2 EC_PWROK EC_PWROK [5,30]
PCH_PWRBTN# R261 *10K_4 DSW PU [13] SYS_PWROK SYS_PWROK 4
1 IMVP_PWRGD_3V [10]
A +3VPCU A
U30
3
R116 *10K_4 TC7SH08FU R615

R275
R276
*8.2K_4
*1K_4 R619 *0_4
10K_4 Quanta Computer Inc.
R273 *10K_4
PROJECT : ZQ0
3A
LPT 1/6 (DMI/FDI/VGA)
5 4 3 2 1
5 4 3 2 1
RTC Clock 32.768KHz (RTC)
08
C481 15p/50V_4 RTC_X1
Haswell ULT PCH (RTC/HDA/SATA/SPI)
1
Y5 R574
Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)
32.768KHZ 10M_4
U25E HSW_ULT_DDR3L
C485 15p/50V_4 RTC_X2
2
RTC_X1 AW5
RTC_X2 AY5 RTCX1
1B-12013/11/20 D24 down size. R591 1M_4 SM_INTRUDER# AU6 RTCX2 J5 U25G HSW_ULT_DDR3L
RTC Circuitry (RTC) +3V_RTC
+3V_RTC
PCH_INTVRMEN AV7 INTRUDER SATA_RN0/PERN6_L3 H5
SATA_RXN0 [25]
D INTVRMEN SATA_RP0/PERP6_L3 SATA_RXP0 [25] D
SRTC_RST# AV6 B15 AU14 +3V_S5 SMBALERT/GPIO11 AN2 SMBALERT#
Trace width = 30 mils SRTCRST
RTC
SATA_TN0/PETN6_L3 SATA_TXN0 [25] HDD [21,24,30] LPC_LAD0 LAD0
D17 +3V_RTC RTC_RST# AU7 A15 [21,24,30] LPC_LAD1 AW12 +3V_S5 AP2 SMB_PCH_CLK
[13] RTC_RST# RTCRST SATA_TP0/PETP6_L3 SATA_TXP0 [25] LAD1 SMBCLK
R345 *Short_6 +3V_RTC_2 R336 AY12 LPC +3V_S5 AH1 SMB_PCH_DAT
+3VPCU [21,24,30] LPC_LAD2 LAD2 SMBDATA
RTC_RST# J8 AW11 SMBUS
+3V_S5SML0ALERT/GPIO60 AL2 SMB0ALERT#
SATA_RN1/PERN6_L2 SATA_RXN1 [25] [21,24,30] LPC_LAD3 LAD3
VCCRTC_2 R346 1K_4 +3V_RTC_1 H8 [21,24,30] LPC_LFRAME#
AV12 +3V_S5 AN1 VGA_MBCLK
SATA_RXP1 [25]
1
20K/F_4 SATA_RP1/PERP6_L2 A17 LFRAME SML0CLK AK1 VGA_MBDATA
SATA_TN1/PETN6_L2 SATA_TXN1 [25] ODD +3V_S5 SML0DATA
VCCRTC_2 BAT54C B17 +3V_S5 AU4 SMB1ALERT# SMB1ALERT# [29]
SATA_TP1/PETP6_L2 SATA_TXP1 [25] SML1ALERT/PCHHOT/GPIO73
C671 J1 +3V_S5 AU3 SMB_ME1_CLK
1u/6.3V_4 *JUMP HDA_BCLK_R AW8 J6 SML1CLK/GPIO75 AH3 SMB_ME1_DAT
+3V_RTC_[0:2] +3V_S5
2
1
HDA_SYNC_R AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6 PCH_SPI_CLK AA3 SML1DATA/GPIO74

Trace width = 20 mils R338 HDA_RST#_R AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14 PCH_SPI_CS0# Y7 SPI_CLK AF2 CL_CLK
HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 SPI_CS0 CL_CLK TP87
SRTC_RST# [28] PCH_AZ_CODEC_SDIN0 AY10 AUDIO SATA C15 PCH_SPI_CS1# Y4 AD2 CL_DAT
HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 SPI_CS1 CL_DATA TP86
BT1 AU12 AC2 SPI C-LINK AF4 CL_RST#
TP89
1
20K/F_4 HDA_SDO_R AU11 HDA_SDI1/I2S1_RXD F5 PCH_SPI_SI AA2 SPI_CS2 CL_RST
AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5 PCH_SPI_SO AA4 SPI_MOSI
C676 C670 J2 AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17 PCH_SPI_IO2 Y6 SPI_MISO 2013/10/16 change SMbus VGA to
2
1u/6.3V_4 1u/6.3V_4 *JUMP AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 PCH_SPI_IO3 AF1 SPI_IO2 1A-3 PCH SML0CLK/SML0DATA.
2
I2S1_SCLK SATA_TP3/PETP6_L0 SPI_IO3
1A-22013/10/16 Chage +3V_RTC_0 to VCCTC_2. +3V V1 VGPU_EN VGPU_EN [37] 7 OF 19

SATA0GP/GPIO34 U1 ODD_PRSNT#
+3V SATA1GP/GPIO35 ODD_PRSNT# [25]
+3V V6 GPIO36
HDA
[28] PCH_AZ_CODEC_RST# R174 33_4 HDA_RST#_R +3V SATA2GP/GPIO36 AC1 GPIO37
SATA3GP/GPIO37 TP108
AU62
[4,13] XDP_TRST# PCH_TRST
[28] PCH_AZ_CODEC_SDOUT R580 33_4 HDA_SDO_R [13] XDP_TCK1 XDP_TCK1 AE62 A12 SATA_IREF R573 *short_4 +V1.05S_ASATA3PLL
XDP_TDI AD61 PCH_TCK SATA_IREF L11 +3V
[28] PCH_AZ_CODEC_BITCLK R584 33_4 HDA_BCLK_R
[13]
[13]
XDP_TDI
XDP_TDO R530 0_4 PCH_JTAG_TDOAE61 PCH_TDI RSVD K10 SMBus +3V_S5
AD62 PCH_TDO JTAG
RSVD C12 SATA_RCOMP R453 3.01K/F_4 GPIO37 10K_4 R517
[13] XDP_TMS PCH_TMS SATA_RCOMP +V1.05S_ASATA3PLL
AL11 U3 SATA_LED# R510 10K_4 +3V
C C483 AC4 RSVD SATALED GPIO36 10K_4 R97 R545 10K_4 SMB0ALERT# C
*10p/50V_4 R547 0_4 PCH_JTAGX AE63 RSVD R575 10K_4 SMB1ALERT#
[4,13] XDP_TCK0 JTAGX
PCH_EDM AV2 SATA_RCOMP *10K_4 R507 VGPU_EN 10K_4 R511 R162 10K_4 SMBALERT#
TP135 RSVD
Impedance = 50 ohm 1A-14 2013/12/02 change GPIO36 to PD.
R181 33_4 HDA_SYNC_R 1A-10 2013/10/25 reserve AV2 ball to GND. Trace length < 500 mils
[28] PCH_AZ_CODEC_SYNC
1A-12 2013/10/28 reserve AV2 ball to TP. Trace spacing = 15 mils 1B-2 2013/12/04 change GPIO36/GPI037 to PU. R285 2.2K_4 SMB_PCH_CLK
C219 *10p/50V_4 5 OF 19 R284 2.2K_4 SMB_PCH_DAT
Option: R536 2.2K_4 VGA_MBDATA
4M@ ->Stuff 33ohm. R164 2.2K_4 VGA_MBCLK
PCH SPI ROM(8M+4M)
RTC charge circuit 15ohm CS01502JB12
8M@->Stuff 15ohm.(default)
8M4M@->8M flash ROM stuff 15ohm(default),
+5V_S5
PCH JTAG 20MIL 33ohm CS03302JB29
4M flash ROM stuff 33ohm.
JTAG_TCK,JTAG_TMS VCCRTC_2 1 3VCCRTC_3 R193 4.7K_4 VCCRTC_4 R202 4.7K_4 R550 *Short_6
MP remove(Intel) +3V_S5 +3V_PCH_ME +3V_PCH_ME +3V
Trace Length < 9000mils Q21 R195
+1.05V_S5 MMBT3904 U14 C147 0.1u/10V_4
2 68.1K/F_4 PCH_SPI_CS0# 1 8
XDP_TMS R541 51_4 CS# VCC
XDP_TDI R542 51_4 PCH_SPI_SO R103 8M4M@15_4SPI_SO_8M 2 7 SPI_HOLD_IO3_ME R147 *1K_4 R289 R279
PCH_JTAG_TDO
PCH_JTAGX
R529
R538
51_4
*1K_4
PCH_SPI_SO_EC R489 8M@15_4
3
IO1/DO IO3/HOLD#
6 SPI_CLK_8M R145 8M4M@15_4 PCH_SPI_CLK
SMBus(PCH) Q14
4.7K_4 4.7K_4
R194 IO2/WP# CLK 5

XDP_TCK1 R546 *51_4 5 SPI_SI_8M R153 8M4M@15_4PCH_SPI_SI
150K/F_4 4 IO0/DI 3 4
GND SMB_PCH_DAT CLK_SDATA [13,14,15,24]
1A-22013/10/16 Add RTC charge circuit.
C162
W25Q64FW -- 8MB *22p/50V_4 2
PCH_SPI_CLK_EC R533 8M@15_4
B B
PCH_SPI_SI_EC R526 8M@15_4 6 1
ULT Strapping Table R106 *1K_4 SPI_WP_IO2_ME
SMB_PCH_CLK CLK_SCLK [13,14,15,24]
Pin Name Strap description Sampled Configuration note

+3V_PCH_ME
PCH_XDP_WLAN/S5 2N7002DW DDR_TP/S0
0 = Default enable (iPD 20K) R566 *4M@33_4 SPI_WP_IO2_EC
GPIO81(SPKR) No reboot on TCO Timer PWROK +3V R508 *1K_4 SPKR SPKR [10,28] 3.3K is original and for no PCH_SPI_IO2 R91 8M4M@15_4SPI_WP_IO2_ME
expiration 1 =Disable No-Reboot mode support fast read function R564 *4M@33_4SPI_HOLD_IO3_EC reserve for SPI fast read
0 = Default can program ME (iPD 20K) PCH_SPI_IO3 R146 8M4M@15_4
SPI_HOLD_IO3_ME
+3V_PCH_ME
SMBus(EC) +3V_S5
HDA_SDO Flash Descriptor Security PWROK HDA_SDO_R R582 *short_4
ME_WR# [30]
Override / Intel ME Debug Mode 1 =can't program ME U28
PCH_SPI_CS1# 1 8
PCH_SPI_CLK R553 *4M@33_4 6 CE# VDD
R592 330K_4 PCH_INTVRMEN R588 *330K_4 PCH_SPI_SI R551 *4M@33_4 5 SCK R290 R278
INTVRMEN Integrated 1.05V VRM enable ALWAYS 1=Should be always pull-up +3V_RTC
PCH_SPI_SO R586 *4M@33_4 2 SI 7SPI_HOLD_IO3_EC R572 *1K_4 *2.2K_4 *2.2K_4
SO HOLD# Q15
0 = Default disable (iPD 20K) [10] GPIO66 C461 *22p/50V_4 3 4 5
PCH_SPI_CLK_R WP# VSS C489
GPIO66 Top-Block Swap override R578 *1K_4 GPIO66 R577 *1K_4 PCH_SPI_SI_R *4M@ROM-4M_EC *4M@0.1u/10V_4 3 4 SMB_ME1_CLK
1 = Enable TBS function +3V
PCH_SPI_SO_R
[19,30] 2ND_MBCLK
0 = Default SPI (iPD 20K) [10] GPIO86

2
GPIO86 Boot BIOS Strap Bit R136 *1K_4 GPIO86 R129 *1K_4 R565 *1K_4 SPI_WP_IO2_EC
1 =LPC +3V +3V_PCH_ME
6 1 SMB_ME1_DAT
[19,30] 2ND_MBDATA
0 = Default enable w/o
1A-3 2013/10/16 Add U34 flash 4M ROM reserve for ZQ0D.
confidentiality(iPD 20K)
[10] GPIO15
EC/S5 *2N7002DW PCH/S5
GPIO15 TLS(Transport layer security) R99 8.2K_4 GPIO15 R95 *1K_4 R543 *4M@33_4 PCH_SPI_CLK_R
A 1 =Default enable with +3V_S5 [30] PCH_SPI_CLK_EC
R531 *4M@33_4 PCH_SPI_SI_R 2ND_MBCLK R280 *short_4 SMB_ME1_CLK
A
confidentiality [30] PCH_SPI_SI_EC

R98 *4M@33_4 PCH_SPI_SO_R 2ND_MBDATAR282 *short_4 SMB_ME1_DAT
[30] PCH_SPI_SO_EC
0 = Enable an external display

CFG4 port is connected to the eDP CFG4 R544 1K_4 R112 8M@0_4 PCH_SPI_CS0#
DP presence strap
1 =disable
[6,13] CFG4 [30] SPI_CS0#_UR_ME
R587 *4M@0_4 PCH_SPI_CS1# Quanta Computer Inc.
only 0ohm option PROJECT : ZQ0
[7] DSWVREN
DSWVREN Deep Sx well on die VR enable 1=Should be always pull-up +3V_PCH_ME Size Document Number Rev
R589 330K_4 DSWVREN R585 *330K_4 3A
+3V_RTC
R109 10K_4 SPI_CS0#_UR_ME
LPT 2/6 (SATA/HDA/SPI)
5 4 3 2 1
5 4 3 2 1
Haswell ULT PCH (PCIE,USB3.0,USB2.0) Haswell ULT PCH (CLOCK) XTAL24_IN C443 12p/50V_4
09
3
4
1A-6 2013/10/21 reversal PEG lan for layout.
1A-8 2013/10/21 Swap PEG to nomroal mode. U25K HSW_ULT_DDR3L 1A-1 2013/10/15 following up acer define and swap USB3 and USB2 R446 Y4
USB2 port. 1M_4 24MHz
[16] PEG_RX#0
F10 DSW AN8 USBP0- [27]
1
2
E10 PERN5_L0 USB2N0 AM8
[16] PEG_RX0 PERP5_L0 DSW USB2P0 USBP0+ [27] MB USB3.0 XTAL24_OUT
D D
[16] PEG_TX#0 C444 EV@0.22u/10V_4 C_PEG_TX#0 C23 DSW AR7 USBP1- [27] C442 12p/50V_4
C445 EV@0.22u/10V_4 C_PEG_TX0 C22 PETN5_L0 USB2N1 AT7 U25F HSW_ULT_DDR3L
[16] PEG_TX0 PETP5_L0 DSW USB2P1 USBP1+ [27] DB USB2.0
[16] PEG_RX#1 F8 DSW AR8 USBP2- [21]
E8 PERN5_L1 USB2N2 AP8
[16] PEG_RX1 PERP5_L1 DSW USB2P2 USBP2+ [21] DB FingerPrint
PEG x4
[16] PEG_TX#1 C451 EV@0.22u/10V_4 C_PEG_TX#1 B23 DSW AR10 TP75 CLK_PCIE_N0 C43 A25 XTAL24_IN
PETN5_L1 USB2N3 USBP3- [27] CLKOUT_PCIE_N0 XTAL24_IN
[16] PEG_TX1 C452 EV@0.22u/10V_4 C_PEG_TX1 A23 DSW AT10 DB USB2.0 TP73 CLK_PCIE_P0 C42 B25 XTAL24_OUT
PETP5_L1 USB2P3 USBP3+ [27] CLKOUT_PCIE_P0 XTAL24_OUT
TP84 CLK_PCIE_REQ0# U2 +3V
H10 AM15 PCIECLKRQ0/GPIO18 K21
[16] PEG_RX#2 PERN5_L2 DSW USB2N4 USBP4- [24] RSVD
[16] PEG_RX2 G10 DSW AL15 USBP4+ [24] BT 1B-2 2013/11/15 Swap LAN and WLAN B41 M21
PERP5_L2 USB2P4 Request clk port base on DG. A41 CLKOUT_PCIE_N1 RSVD C26 ICLK_BIAS R47 3.01K/F_4
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +V1.05S_AXCK_LCPLL
[16] PEG_TX#2 C432 EV@0.22u/10V_4 C_PEG_TX#2 B21 DSW AM13 TP10 CLK_PCIE_REQ1# Y5 +3V
C21 PETN5_L2 USB2N5 AN13 USBP5- [22] PCIECLKRQ1/GPIO19 C35
[16] PEG_TX2 C433 EV@0.22u/10V_4 C_PEG_TX2 DSW USBP5+ [22] Touch screen TESTLOW_C35
PETP5_L2 USB2P5 C41 CLOCK TESTLOW_C35 C34 TESTLOW_C34
VGA WLAN LAN

[26] CLK_PCIE_LANN CLKOUT_PCIE_N2 TESTLOW_C34
[16] PEG_RX#3 E6 DSW AP11 USBP6- [22] [26] CLK_PCIE_LANP B42 AK8 TESTLOW_AK8
F6 PERN5_L3 USB2N6 AN11 R519 *short_4CLK_PCIE_REQ2# AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 TESTLOW_AL8
[16] PEG_RX3 PERP5_L3 DSW USB2P6 USBP6+ [22] CCD [26] CLK_PCIE_LAN_REQ# PCIECLKRQ2/GPIO20 +3V TESTLOW_AL8 TPM@22_4 R170 PCLK_TPM [21]
[16] PEG_TX#3 C449 EV@0.22u/10V_4 C_PEG_TX#3 B22 DSW AR13 USBP7- [27] [24] CLK_PCIE_WLANN B38 AN15 CLK_PCH_PCI3 22_4 R171 CLK_PCI_LPC [24]
C450 EV@0.22u/10V_4 C_PEG_TX3 A21 PETN5_L3 USB2N7 AP13 C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCH_PCI4 22_4 R169
[16] PEG_TX3 PETP5_L3 DSW USB2P7 USBP7+ [27] Card reader [24] CLK_PCIE_WLANP
R493 *short_4CLK_PCIE_REQ3# N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_EC [30]
[24] PCIE_CLKREQ_WLAN# PCIECLKRQ3/GPIO21 +3V
[26] PCIE_RX3-_LAN
G11 B35 CLK_PCIE_XDPN [13]
F11 PERN3 G20 A39 CLKOUT_ITPXDP A35
[26] PCIE_RX3+_LAN PERP3 USB3RN1 USB3_RXN0 [27] [16] CLK_PCIE_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P CLK_PCIE_XDPP [13]
H20 B39
LAN
USB3RP1 USB3_RXP0 [27] [16] CLK_PCIE_VGA CLKOUT_PCIE_P4

[26] PCIE_TX3-_LAN C439 0.1u/10V_4 PCIE_TX3- C29 MB USB3.0 [16] CLK_PEGA_REQ# R87 *short_4CLK_PCIE_REQ4# U5 +3V
C438 0.1u/10V_4 PCIE_TX3+ B30 PETN3 PCIE USB C33 PCIECLKRQ4/GPIO22
[26] PCIE_TX3+_LAN PETP3 +3V_S5 USB3TN1 USB3_TXN0 [27]
C +3V_S5 B34 USB3_TXP0 [27] B37 C
F13 USB3TP1 A37 CLKOUT_PCIE_N5
WLAN
[24] PCIE_RX4-_WLAN PERN4 CLKOUT_PCIE_P5

[24] PCIE_RX4+_WLAN
G13 E18 CLK_PCIE_REQ5# T2 +3V
PERP4 USB3RN2 F18 PCIECLKRQ5/GPIO23
C441 0.1u/10V_4 PCIE_TX4- B29 USB3RP2
[24] PCIE_TX4-_WLAN PETN4
[24] PCIE_TX4+_WLAN C440 0.1u/10V_4 PCIE_TX4+ A29 +3V_S5 B33 6 OF 19
PETP4 USB3TN2 A33
+3V_S5 USB3TP2
G17
F17 PERN1/USB3RN3
PERP1/USB3RP3
USBCOMP +3V
C30
C31 PETN1/USB3TN3 +3V_S5 AJ10 USBCOMP R123 22.6/F_4
Impedance = 50 ohm
PETP1/USB3TP3 +3V_S5 USBRBIAS AJ11 Trace length < 500 mils CLK_PCIE_REQ0# R504 10K_4
F15 USBRBIAS AN10 Trace spacing = 15 mils CLK_PCIE_REQ1# R102 10K_4
G15 PERN2/USB3RN4 RSVD AM10 CLK_PCIE_REQ2# R518 10K_4
PERP2/USB3RP4 RSVD USB Overcurrent CLK_PCIE_REQ3# R492 10K_4 CLK_PCI_EC CLK_PCI_LPC PCLK_TPM
B31 CLK_PCIE_REQ5# R503 10K_4
A31 PETN2/USB3TN4 +3V_S5 +3V_S5
PETP2/USB3TP4 +3V_S5 AL3 USB_OC0# RP1
+3V_S5 OC0/GPIO40 AT1 USB_OC1#
USB_OC0# [27] MB U3 10 1 TESTLOW_C35 R465 10K_4 C221 C226 C222
+3V_S5 OC1/GPIO41 AH2 USB_OC2#
USB_OC1# [27] DB U2 USB_OC0# 9 2 TESTLOW_C34 R418 10K_4 *18p/50V_4 *18p/50V_4 *TPM@18p/50V_4
+3V_S5 OC2/GPIO42
E15 +3V_S5 AV3 USB_OC3# USB_OC1# 8 3 TESTLOW_AK8 R185 10K_4
E13 RSVD OC3/GPIO43 USB_OC2# 7 4 TESTLOW_AL8 R271 10K_4
R571 3.01K/F_4 PCIE_RCOMP A27 RSVD USB_OC3# 6 5
R570 *short_4 PCIE_IREF B27 PCIE_RCOMP
+V1.05S_AUSB3PLL PCIE_IREF 10K_10P8R
+3V
B B
11 OF 19
CLK_PCIE_REQ4# R90 10K_4
R92 *1K_4
A A

PROJECT : ZQ0
3A
LPT 3/6 (PCIE/USB/CLK)
5 4 3 2 1
5 4 3 2 1
High Low
Haswell ULT PCH (GPIO,CPU/MISC,NCTF)
U25J HSW_ULT_DDR3L PCH GPIO PU/PD
10
+3V
GPIO8 Touch panel No touch panel IRQ_SERIRQ R494 10K_4
DEVSLP0 R496 *10K_4
BOARD_ID0 P1 +3V D60 THRMTRIP# DEVSLP1 R486 *10K_4
D GPIO8 AU2 BMBUSY/GPIO76 THRMTRIP V4 SIO_RCIN# SIO_RCIN# R506 10K_4 D
[22] GPIO8 GPIO8 +3V_S5 +3V RCIN/GPIO82 SIO_RCIN# [30]
LAN_DISABLE# AM7 +3V_S5 T4 IRQ_SERIRQ IRQ_SERIRQ [21,30] SIO_EXT_SMI# R73 10K_4
GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 OPI_COMP2 R579 49.9/F_4 SIO_EXT_SCI# R131 10K_4
[8] GPIO15
SKU_ID0 Y1 GPIO15 +3V_S5 MISC PCH_OPI_RCOMP AF20
DGPU_PWROK T3 GPIO16 +3V RSVD AB21
[17] DGPU_PWROK
GPIO24 AD5 GPIO17 +3V RSVD GPIO85 R77 10K_4
WK_GPIO27 AN5 GPIO24 +3V_S5 1A-13 20131030 add touch pad GPIO87 R152 10K_4
GPIO28 AD7 GPIO27 DSW GPIO88 R67 10K_4
GPIO28 +3V_S5
interrupt pin on gpio83.
GPIO26 AN3 GPIO89 R81 10K_4
GPIO26 +3V_S5 R6 TP_INT_PCH GPIO90 R484 10K_4
+3V GSPI0_CS/GPIO83 TP_INT_PCH [22]
GPIO56 AG6 L6 GPIO84 GPIO91 R483 10K_4
TP26
GPIO57 AP1 GPIO56 +3V_S5 +3V GSPI0_CLK/GPIO84 N6 GPIO85 GPIO92 R78 10K_4
TP132
GPIO58 AL4 GPIO57 +3V_S5 +3V GSPI0_MISO/GPIO85 L8 GPIO86 GPIO93 R480 10K_4
TP15
GPIO59 AT5 GPIO58 +3V_S5 +3V GSPI0_MOSI/GPIO86 R7 GPIO87
GPIO86 [8]
GPIO94 R479 10K_4
TP53
GPIO44 AK4 GPIO59 +3V_S5 GPIO
+3V GSPI1_CS/GPIO87 L5 GPIO88 R470 *10K_4 PCH_ODD_EN R69 10K_4
GPIO47 AB6 GPIO44 +3V_S5 +3V GSPI1_CLK/GPIO88 N7 GPIO89 GPIO65 R473 10K_4
DGPU_HOLD_RST# U4 GPIO47 +3V_S5 +3V GSPI1_MISO/GPIO89 K2 GPIO90 TP_INT_PCH R94 10K_4
[16] DGPU_HOLD_RST#
DGPU_PWR_EN Y3 GPIO48 +3V +3V GSPI_MOSI/GPIO90 J1 GPIO91 GPIO84 R59 10K_4
[38] DGPU_PWR_EN
DGPU_PW_CTRL# P3 GPIO49 +3V +3V UART0_RXD/GPIO91 K3 GPIO92 I2C0_SDA_GPIO4 R474 2.2K_4
MODPHY_EN Y2 GPIO50 +3V +3V UART0_TXD/GPIO92 J2 GPIO93 I2C0_SCL_GPIO5 R475 2.2K_4
[33] MODPHY_EN
GPIO13 AT3 HSIOPC/GPIO71 +3V +3V
SERIAL IO UART0_RTS/GPIO93 G1 GPIO94 GPIO67 R130 10K_4
GPIO13 +3V_S5 +3V UART0_CTS/GPIO94 20130926 chnge GPIO port
GPIO14 AH4 K4 SIO_EXT_SMI# GPIO68 R128 10K_4
GPIO25 AM4 GPIO14 +3V_S5 +3V UART1_RXD/GPIO0 G2 SIO_EXT_SCI#
SIO_EXT_SMI# [30]
GPIO69 R581 10K_4
TP33
GPIO45 AG5 GPIO25 DSW +3V UART1_TXD/GPIO1 J3 DGPU_EVENT#
SIO_EXT_SCI# [30]
2013/10/16 BIOS suggestion R514 *100K_4 DGPU_PWR_EN R513 10K_4
TP13
ACCEL_INTA AG3 GPIO45 +3V_S5 +3V UART1_RST/GPIO2 J4 GC6_FB_EN
DGPU_EVENT# [19]
1A-3 change SMI/SCI to GPIO0~15 I2C1_SDA_GPIO6 R54 10K_4
[29] ACCEL_INTA GPIO46 +3V_S5 +3V UART1_CTS/GPIO3 F2 GPIO4
GC6_FB_EN [17,19]
I2C1_SCL_GPIO7 R53 10K_4
C +3V I2C0_SDA/GPIO4 I2C0_SDA_GPIO4 [29] C
GPIO9 AM3 +3V_S5 +3V F3 GPIO5 I2C0_SCL_GPIO5 [29] DGPU_HOLD_RST# R478 10K_4
GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 GPIO6 R150 *EVG@10K_4 GC6_FB_EN R79 *IV@10K_4
DEVSLP0 P2 GPIO10 +3V_S5 +3V I2C1_SDA/GPIO6 F1 GPIO7
I2C1_SDA_GPIO6 [22]
[25] DEVSLP0 DEVSLP0/GPIO33 +3V +3V I2C1_SCL/GPIO7 I2C1_SCL_GPIO7 [22]
BOARD_ID3 C4 +3V +3V E3 1A-1 20131015 For GC6 NV DG GC6_FB_EN PD.
SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 PCH_ODD_EN [25]
DEVSLP1 L2 +3V +3V F4 GPIO65
SKU_ID1 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 GPIO66 1A-8 20131022 Change GPIO83/84 GPU GC6 pin
DEVSLP2/GPIO39 +3V +3V SDIO_D0/GPIO66 GPIO66 [8]
[8,28] SPKR SPKR V2 +3V +3V E4 GPIO67 to GPIO2/3.
SPKR/GPIO81 SDIO_D1/GPIO67 C3 GPIO68 1A-12 20131029 Change GPIO45 to PU S5,
+3V SDIO_D2/GPIO68
+3V E2 GPIO69 GPU GC6 2.0 function use duble GPIO58 one is GPIO56.
SDIO_D3/GPIO69
GPIO2/3.
10 OF 19
1A-14 2013/11/01 change GPIO64 to PCH_ODD_EN and PD. high UMA Only
GPU power is control by PCH

low GPIO (Discrete, SG or Optimize) +3V
Board ID RAM ID CPU thermal trip
+1.05V_VCCST R500 EV@100K_4 DGPU_PW_CTRL#R499 *IV@1K_4
+3V DGPU_PWROK R96 *10K_4
3
DGPU_PWROK PD on GPU side +3V_S5
R497 10K_4 BOARD_ID0 R498 *10K_4
LAN_DISABLE# R260 10K_4
[2] BOARD_ID1 IMVP_PWRGD_3V 2 Q13
GPIO8 R167 10K_4
B R89 10K_4 BOARD_ID1 R88 *10K_4 FDV301N ACCEL_INTA R114 *10K_4 B
[2] BOARD_ID2 GPIO24 R101 10K_4
GPIO28 R520 10K_4
1
GPIO47 R113 10K_4
R491 10K_4 BOARD_ID2 R490 *10K_4 +1.05V_VCCST GPIO57 R554 10K_4
R132 GPIO56 R104 10K_4
R124 *10K_4 BOARD_ID3 R121 10K_4 1K_4 GPIO59 R183 10K_4
GPIO26 R163 10K_4
[2] BOARD_ID4 R133 GPIO58 R120 10K_4
GPIO44 R523 10K_4
2
R488 10K_4 BOARD_ID4 R487 *10K_4 1K_4 GPIO13 R558 10K_4
GPIO14 R115 10K_4
THRMTRIP# 1 3 GPIO9 R263 10K_4
SYS_SHDN# [32,36]
Q16 MMBT3904-7-F GPIO10 R161 10K_4
+3V GPIO45 R105 10K_4
SKU ID R127 10K_4
R556 *10K_4
Low High R509 *IV@10K_4 SKU_ID0 R512 EV@10K_4
U3 +1.05V_VCCST +3V +3VPCU
R86 *IV@10K_4 SKU_ID1 R143 EV@10K_4 GPIO25 R125 *10K_4
BOARD_ID0 N15V-GL-B N15V-GM-B 1 5 R560 *10K_4
NC VCC WK_GPIO27 R559 10K_4
1
R144
2 C154
BOARD_ID1 Reserved Reserve SKU_ID1 SKU_ID0 VGA H/W Setup [5,35] IMVP_PWRGD A 0.1u/10V_4
10K_4
1B-7 20131220 Change +3VPCU to +3V_S5
(Default)
2
Signal Menu non deep sx
A 3 4 IMVP_PWRGD_3V [7] GPIO27 : If not used then use A
UMA Only 0 0 UMA Hidden UMA boot GND Y
8.2-kΩ to 10-kΩ pull-down to GND.
BOARD_ID2 Reserve for Touch pad, default(low) 74AUP1G07GW
dGPU Only 0 1 GPU Hidden GPU boot
Switchable
1 0 UMA+GPU dGPU/SG UMA boot
BOARD_ID3 DTPM No DTPM (Mux) PROJECT :ZQ0
Non-Dolly Optimize Size Document Number Rev
1 1 UMA UMA/SG UMA boot 3A
BOARD_ID4 (Default) Dolly (Muxless) LPT 4/6 (GPIO/MISC)
5 4 3 2 1
5 4 3 2 1
C437
C163
C175
*1u/6.3V_4
1u/6.3V_4
1u/6.3V_4 U25M
Haswell ULT PCH (Power)
HSW_ULT_DDR3L
C139
1u/6.3V_4
+3VCC_S5
11
1.838A K9
+1.05V +1.05V_MODPHY VCCHSIO
L10
VCCHSIO +3V_RTC
1.741A M9
R43 *SHORT_8 +V1.05S_AIDLE N8 VCCHSIO HSIO RTC AH11
P9 VCC1_05 VCCSUS3_3 AG10 C488 C491 C487
D B18 VCC1_05 VCCRTC AE7 +VCCRTCEXT 0.1u/10V_4 0.1u/10V_4 1u/6.3V_4 D
+V1.05S_AUSB3PLL VCCUSB3PLL DCPRTC
C181 B11
+V1.05S_ASATA3PLL VCCSATA3PLL
*1u/6.3V_4
18mA C131
Y20 SPI Y8 +V3.3M_PSPI 0.1u/10V_4
AA21 RSVD VCCSPI R117 *Short_6
R294 *0_6
10mA +V1.05S_APLLOPI
W21 VCCAPLL
OPI
+3V_S5
+1.05V_S5 VCCAPLL AG14 R118 *0_6 +3V
VCCASW AG13 PCH_VCC_1_1_21
C177 C166 VCCASW
10u/6.3V_6 1u/6.3V_4 +1.05V_DCPSUS3 J13 USB3
+1.05V C144
DCPSUS3 J11 +V1.05S_CORE_PCH R119 *Short_6 0.1u/10V_4
VCC1_05 +1.05V
H11
AH14 HDA VCC1_05 H15
R292 *0_6
25mA +1.05V_DCPSUS2
+V3.3DX_1.5DX_1.8DX_AUDIO VCCHDA VCC1_05 AE8 R48 *SHORT_8
+1.05V_S5 VCC1_05 +1.05V
AF22
AH13 VRM VCC1_05 AG19
Deep Sx 0.114A DCPSUS2 CORE DCPSUSBYP
C149 +3VPCU R568 *0_6 AG20 C148 C159 C192
1u/6.3V_4 C236 22u/6.3V_8 DCPSUSBYP AE9 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6
VCCASW AF9
+3V_S5R569 *Short_6
VCCASW
AC9 AG8
+3VCC_S5 VCCSUS3_3 VCCASW
Non Deep Sx AA9 GPIO/LPC AD10 +1.05V_DCPSUS1 +PCH_VCCDSW
C152 +VCCPDSW AH10 VCCSUS3_3 DCPSUS1 AD8
1u/6.3V_4 +V3.3S_VCCPCORE V8 VCCDSW3_3 DCPSUS1
W9 VCC3_3 C153
VCC3_3 J15 1u/6.3V_4
R49 *SHORT_8
41mA THERMAL SENSOR VCCTS1_5 K14
+3V VCC3_3 +V1.05M_VCCASW
K16
VCC3_3
C114 +V1.05M_VCCASW
0.658A R108 *SHORT_8 +1.05V
C 22u/6.3V_8 J18 C
+V1.05S_AXCK_DCB
K19 VCCCLK SERIAL IO U8
0.109A
A20 VCCCLK VCCSDIO T9 R293 *0_6 C142 C134
+V1.05S_AXCK_LCPLL VCCACLKPLL VCCSDIO
J17 1u/6.3V_4 22u/6.3V_8
+1.05V VCCCLK +1.05V_S5
R21
+1.05V VCCCLK
C164 1u/6.3V_4 T21 LPT LP POWER C143
C119 1u/6.3V_4 K18 VCCCLK SUS OSCILLATOR AB8 1u/6.3V_4
M20 RSVD DCPSUS4
WW15 4/10 Intel VCCDSW3 RSVD
V21
G3 can't boot issue. 63mA AE20 RSVD AC20
3mA +V1.5S_VCCATS R111 *Short_6
C472 +3VCC_S5 VCCSUS3_3 RSVD +1.5V
AE21 AG16
+VCCPDSW +PCH_VCCDSW VCCSUS3_3 USB2 VCC1_05 AG17
1mA +V3.3S_VCCPTS R107 *Short_6
VCC1_05 +3V
0.47u/25V_6 C183
13 OF 19 1u/6.3V_4
+V3.3S_VCCSDIO
17mA R100 *Short_6 +3V
PCH VCCHSIO Power +1.05V_DCPSUS4 R291 *0_6 +1.05V_S5
C194
1u/6.3V_4
C197
1u/6.3V_4
+V1.05S_VCCUSBCORE R270 *SHORT_8 +1.05V

B B
C151
1u/6.3V_4
1A-1 2013/10/11 del LDO change to MOS.

VCCAPLL power +1.05V +V1.05S_AXCK_DCB
+1.05V +V1.05S_APLLOPI L5 2.2uH/210mA_8

0.2A
L3 2.2uH/210mA_8
57mA
C112 C104 C158
47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
C121 C122 C99

*47u/6.3V_8 *47u/6.3V_8 1u/6.3V_4
+1.05V +V1.05S_AXCK_LCPLL
PCH HDA Power L2 2.2uH/210mA_8

31mA
+1.05V_MODPHY +V1.05S_AUSB3PLL +1.05V_MODPHY +V1.05S_ASATA3PLL
11mA
A L7 2.2uH/210mA_8
41mA L28 2.2uH/120mA_6
42mA C68 C76 C111 A
+3V_S5 +V3.3DX_1.5DX_1.8DX_AUDIO 47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
R196 *Short_6
C88 C77 C115 C89 C79 C448
47u/6.3V_8 47u/6.3V_8 1u/6.3V_4 47u/4V_8 47u/4V_8 1u/6.3V_4
C155
0.1u/10V_4 Quanta Computer Inc.
Place close to ball PROJECT :ZQ0
2013/10/31 PN change to H=0.85.L17 H=0.9 Size Document Number Rev
3A
LPT 5/6 (POWER)
5 4 3 2 1
5 4 3 2 1
Haswell ULT (GND) 12

HSW_ULT_DDR3L HSW_ULT_DDR3L HSW_ULT_DDR3L HSW_ULT_DDR3L
U25N U25O U25P U25R
D H17 D
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10 N23
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22 RSVD R23
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59 RSVD T23
VSS VSS VSS VSS VSS VSS AT2 RSVD
A28 AJ45 AP3 AW33 D38 J63 RSVD U10
VSS VSS VSS VSS VSS VSS AU44 RSVD
A32 AJ47 AP31 AW35 D39 K1 RSVD
VSS VSS VSS VSS VSS VSS AV44
A36 AJ50 AP38 AW37 D41 K12 RSVD
VSS VSS VSS VSS VSS VSS D15
A40 AJ52 AP39 AW4 D42 L13 RSVD AL1
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15 RSVD AM11
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17 RSVD AP7
VSS VSS VSS VSS VSS VSS F22 RSVD
A52 AJ58 AP54 AW44 D46 L18 RSVD AU10
VSS VSS VSS VSS VSS VSS H22 RSVD
A56 AJ60 AP57 AW47 D47 L20 RSVD AU15
VSS VSS VSS VSS VSS VSS J21 RSVD
AA1 AJ63 AR11 AW50 D49 L58 RSVD AW14
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61 RSVD AY14
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7 RSVD
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10 18 OF 19
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
C AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9 C
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62 VSS_SENSE_R R422 *short_4
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE [35]
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 VSS R428 100/F_4
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH44 VSS VSS AN45 AV24 VSS VSS D12
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 VSS
14 OF 19
HSW_ULT_DDR3L
U25Q
DC_TEST_AY2_AW 2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW 3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 TP76
TP134 TP_DC_TEST_AY60 AY60
DC_TEST_AY61_AW 61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 TP74
DC_TEST_AY62_AW 62 AY62 A61 DC_TEST_A61_B61
TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62
A TP77 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 TP78 A
DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 TP95
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW 1
DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 TP94
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW 2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW 3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW 61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW 62
DAISY_CHAIN_NCTF_C2
17 OF 19
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
AW63 TP_DC_TEST_AW 63 TP133 Quanta Computer Inc.
PROJECT : ZQ0
3A
LPT 6/6 (GND)
5 4 3 2 1
5 4 3 2 1
H_SYS_PWROK_XDP R287 *1K_4

+3V_S5
13
+3V
XDP_PREQ_N NOA_STBP_0
[4] XDP_PREQ# TP106 TP125 NOA_STBP_0 [6]
XDP_DBRESET_N R657 *1K_4 XDP_PRDY_N NOA_STBN_0
[4] XDP_PRDY# TP117 TP128 NOA_STBN_0 [6]
D D
CFG0 CFG8
[6] CFG0 TP35 TP129 CFG8 [6]
CFG1 CFG9
[6] CFG1 TP121 TP131 CFG9 [6]
CFG2 CFG10
[6] CFG2 TP120 TP27 CFG10 [6]
CFG3 CFG11
[6] CFG3 TP130 TP19 CFG11 [6]
NOA_STBP_1
[4] XDP_BPM#0 TP113 TP107 NOA_STBP_1 [6]
NOA_STBN_1
[4] XDP_BPM#1 TP114 TP109 NOA_STBN_1 [6]
CFG4 CFG12
[6,8] CFG4 TP115 TP118 CFG12 [6]
CFG5 CFG13
[6] CFG5 TP116 TP112 CFG13 [6]
CFG6 CFG14
[6] CFG6 TP28 TP122 CFG14 [6]
CFG7 CFG15
[6] CFG7 TP30 TP127 CFG15 [6]
R286 *1K_4 VCCST_PWRGD_XDP CK_XDP_P_R R417 *0_4 CLK_PCIE_XDPP [9]
[30,33] HWPG_1.05V_S5 TP62 TP97
NBSWON# CK_XDP_N_R R416 *0_4 CLK_PCIE_XDPN [9]
TP140 TP96
[5] PWR_DEBUG XDP_RST_R_N R204 *1K_4

TP8 TP59 PLTRST# [7,16,21,24,26,27,30]
R288 *0_4 H_SYS_PWROK_XDP XDP_DBRESET_N R658 *0_4 SYS_RESET#
[7] SYS_PWROK TP136 TP139
[8,14,15,24] CLK_SDATA XDP_TDO R395 *51_4 +1.05V_S5

TP119 TP88
[8,14,15,24] CLK_SCLK XDP_TRST_N
TP45 TP90
XDP_TDI
C [8] XDP_TCK1 TP126 TP91 C
XDP_TMS
[4,8] XDP_TCK0 TP7 TP92
+3V
C176
*0.1u/10V_4
U20
14
VCC
B XDP_TDO 2 3 B
[8] XDP_TDO 1A 1B XDP_TDO_CPU [4]
1
APS1 R667 *0_6 APS3 R668 *0_6 APS7 1OE
XDP_TDI 5 6
[8] XDP_TDI 2A 2B XDP_TDI_CPU [4]
APS 4
2OE
[8] XDP_TMS XDP_TMS 9 8
+3VCC_S5 3A 3B XDP_TMS_CPU [4]
CN20 10
1 APS1 R666 *0_6 3OE
1 2 R665 *0_4 XDP_TRST_N 12 11
2 SUSB# [7,30] 4A 4B XDP_TRST# [4,8]
3 APS3 R659 *0_6 +3VPCU
3 4 R664 *0_4 13
4 5 R663 *0_4 PCH_SLP_S5# [7] 4OE 15
5 6 R662 *0_4 SUSC# [7,30] DPAD
6 7 APS7 R661 *0_6 PCH_SLP_A# [7] 7
7 +3VPCU GND
8
8 9 R674 *0_4 *74CBTLV3126
9 10 RTC_RST# [8]
10 11 R671 *0_4
11 12 NBSWON# [21,30] +1.05V +3V
12 13 R672 *0_4 SYS_RESET# U19
13 14 SYS_RESET# [7]
A 14 15 1 5 A
15 16 NC VCC R393
16
1
17 *10K_4
17 18 2 C387
18 [5] VCCST_PWRGD A *0.1u/10V_4 Quanta Computer Inc.
2
*ACES_88511-180N
3 4
GND Y PROJECT :ZQ0
*74AUP1G07GW 3A
CPU/PCH XDP
5 4 3 2 1
1 2 3 4 5 6 7 8
+1.35V_SUS
14
[3] M_A_A[15:0] JDIM2A JDIM2B
M_A_A0 98 5 75 44
A0 DQ0 M_A_DQ2 [3] VDD1 VSS16
M_A_A1 97 7 M_A_DQ6 [3] 76 48
M_A_A2 96 A1 DQ1 15 81 VDD2 VSS17 49
M_A_A3 95 17 M_A_DQ3 [3] 82 54
M_A_A4 92 A3 DQ3 4 87 VDD4 VSS19 55
M_A_A5 91 6 88 60
M_A_A6 90 16 M_A_DQ5 [3] 93 61
M_A_A7 86 A6 DQ6 18 94 VDD7 VSS22 65
M_A_A8 89 21 99 66
M_A_A9 85 A8 DQ8 23
M_A_DQ9 [3] 2.48A 100 VDD9 VSS24 71
M_A_A10 107 33 105 72
A10/AP DQ10 M_A_DQ15 [3] VDD11 VSS26
PC2100 DDR3 SDRAM SO-DIMM

A M_A_A11 84 35 M_A_DQ11 [3] 106 127 A
M_A_A12 83 A11 DQ11 22 111 VDD12 VSS27 128
A12/BC# DQ12 M_A_DQ12 [3] VDD13 VSS28
M_A_A13 119 24 M_A_DQ13 [3] 112 133
M_A_A14 80 A13 DQ13 34 117 VDD14 VSS29 134
A14 DQ14 M_A_DQ14 [3] VDD15 VSS30
M_A_A15 78 36 M_A_DQ10 [3] 118 138
A15 DQ15 39 123 VDD16 VSS31 139

DQ16 M_A_DQ16 [3] VDD17 VSS32
109 41 M_A_DQ17 [3] 124 144
[3] M_A_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_A_DQ19 [3] 145
[3] M_A_BS#1 BA1 DQ18 VSS34
79 53 M_A_DQ18 [3] 199 150
[3] M_A_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 151
[3] M_A_CS#0 S0# DQ20 M_A_DQ21 [3] VSS36
121 42 M_A_DQ20 [3] 77 155
[3] M_A_CS#1 S1# DQ21 NC1 VSS37
101 50 M_A_DQ23 [3] 122 156
[3] M_A_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_A_DQ22 [3] R259 *10K_4 125 161
[3] M_A_CLK0# CK0# DQ23 +3V NCTEST VSS39
102 57 M_A_DQ25 [3] 162
[3] M_A_CLK1 104 CK1 DQ24 59 198 VSS40 167
M_A_DQ24 [3] PM_EXTTS#0
[3] M_A_CLK1# CK1# DQ25 EVENT# VSS41
73 67 M_A_DQ31 [3] 30 168
[3] M_A_CKE0 CKE0 DQ26 [4,15] DDR3_DRAMRST# RESET# VSS42
74 69 M_A_DQ26 [3] C309 *0.1u/10V_4 172
[3] M_A_CKE1 CKE1 DQ27 VSS43
115 56 M_A_DQ28 [3] 173
[3] M_A_CAS# CAS# DQ28 VSS44
110 58 M_A_DQ29 [3] +SMDDR_VREF_DQ0 +SMDDR_VREF_DQ0 1 178
[3] M_A_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_A_DQ27 [3] 126 179
[3] M_A_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R258 10K_4 DIMM0_SA0 197 70 M_A_DQ30 [3] 184
R254 10K_4 DIMM0_SA1 201 SA0 DQ31 129 VSS47 185
SA1 DQ32 M_A_DQ33 [3] VSS48
202 131 M_A_DQ32 [3] 2 189
[8,13,15,24] CLK_SCLK 200 SCL DQ33 141 3 VSS1 VSS49 190
[8,13,15,24] CLK_SDATA SDA DQ34 M_A_DQ35 [3] VSS2 VSS50
143 8 195
(204P)
DQ35 M_A_DQ34 [3] VSS3 VSS51
116 130 M_A_DQ36 [3] 9 196
[4] M_A_ODT0_DIMM ODT0 DQ36 VSS4 VSS52
120 132 M_A_DQ37 [3] 13
[4] M_A_ODT1_DIMM ODT1 DQ37 VSS5
140 14
DQ38 M_A_DQ39 [3] VSS6
B 1A-8 2013/10/23 Change DIMM1_SA0/SA1 11 142 M_A_DQ38 [3] 19 B
to DIMM0_SA0/SA1. 28 DM0 DQ39 147 20 VSS7
DM1 DQ40 M_A_DQ46 [3] VSS8
46 149 M_A_DQ44 [3] 25
(204P)
63 DM2 DQ41 157 26 VSS9 203
DM3 DQ42 M_A_DQ41 [3] VSS10 VTT1 +DDR_VTT_RUN
136 159 31 204
DM4 DQ43 M_A_DQ45 [3] VSS11 VTT2
153 146 M_A_DQ40 [3] 32
170 DM5 DQ44 148 37 VSS12 205
DM6 DQ45 M_A_DQ42 [3] VSS13 GND
187 158 M_A_DQ43 [3] 38 206
DM7 DQ46 160 43 VSS14 GND
DQ47 M_A_DQ47 [3] VSS15
M_A_DQS0 12 163
DQS0 DQ48 M_A_DQ49 [3]
M_A_DQS1 29 165 M_A_DQ52 [3]
M_A_DQS2 47 DQS1 DQ49 175 DDR3-DIMM1_H=4.0_STD
M_A_DQS3 64 177 M_A_DQ53 [3]
M_A_DQS4 137 DQS3 DQ51 164
M_A_DQS5 154 166
M_A_DQS6 171 174 M_A_DQ51 [3]
M_A_DQS7 188 DQS6 DQ54 176
[3] M_A_DQS[7:0]
M_A_DQS#0 10 DQS7 DQ55 181
M_A_DQ50 [3] M1 solution
DQS#0 DQ56 M_A_DQ56 [3] +1.35V_SUS
M_A_DQS#1 27 183 M_A_DQ60 [3]
M_A_DQS#2 45 DQS#1 DQ57 191
DQS#2 DQ58 M_A_DQ58 [3]
M_A_DQS#3 62 193 M_A_DQ62 [3]
M_A_DQS#4 135 DQS#3 DQ59 180
M_A_DQS#5 152 DQS#4
DQS#5
DQ60
DQ61
182
M_A_DQ57
M_A_DQ61
[3]
[3] R310 Vref_CA
M_A_DQS#6 169 192 M_A_DQ63 [3] 1.8K/F_4
M_A_DQS#7 186 DQS#6 DQ62 194 +SMDDR_VREF_DIMM
[3] M_A_DQS#[7:0] DQS#7 DQ63 M_A_DQ59 [3]
+VREF_CA_CPU R382 *Short_6 R311 2/F_6

1A-2 2013/10/16 Chage net name M_B_DQS#[7:0] to DDR3-DIMM1_H=4.0_STD
2
M_A_DQS#[7:0].
C M3 solution C334 R295 C322
C
0.022u/16V_4 1.8K/F_4 470p/50V_4
1
+1.35V_SUS Place these Caps near SO-DIMM R381
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0 24.9/F_4
C320 C293 C295 C319 C291
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C315 + C297 C321 C336 C299 C288

330u/2V_7343
10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C314 C296 C294 C318 C316 2.2u/6.3V_6 2.2u/6.3V_6

M1 solution
10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 +1.35V_SUS
+3V +DDR_VTT_RUN
R252 Vref_DQ
1.8K/F_4
+SMDDR_VREF_DQ0
C312 C303 C323 C305 C306 C311 C324
C298 C289 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 +VREFDQ_SA_M3 R238 *Short_6 R244 2/F_6
2.2u/6.3V_6 0.1u/10V_4 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
2
M3 solution C287 R251 C300
0.022u/16V_4 1.8K/F_4 470p/50V_4
1
D D
R242
24.9/F_4
SA1 SA0 Quanta Computer Inc.

CHA 0 0
PROJECT : ZQ0
CHB 1 0 3A
DDR3 MEMORY SO-DIMM A
1 2 3 4 5 6 7 8
5 4 3 2 1
[3] M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
98
97
96
95
JDIM1A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
17
M_B_DQ23
M_B_DQ22
M_B_DQ19
M_B_DQ20
[3]
[3]
[3]
[3]
+1.35V_SUS
75
76
81
82
JDIM1B
VDD1
VDD2
VDD3
VSS16
VSS17
VSS18
44
48
49
54
15
M_B_A4 92 A3 DQ3 4 87 VDD4 VSS19 55
A4 DQ4 M_B_DQ16 [3] VDD5 VSS20
M_B_A5 91 6 M_B_DQ17 [3] 88 60
M_B_A6 90 A5 DQ5 16 93 VDD6 VSS21 61
M_B_A7 86 18 M_B_DQ18 [3] 94 65
M_B_A8 89 A7 DQ7 21 99 VDD8 VSS23 66
D
M_B_A9 85 A8 DQ8 23
M_B_DQ4 [3] 2.48A 100 VDD9 VSS24 71
D
M_B_A10 107 33 M_B_DQ7 [3] 105 72
M_B_A11 84 A10/AP DQ10 35 106 VDD11 VSS26 127

M_B_A12 83 22 M_B_DQ3 [3] 111 128
M_B_A13 119 A12/BC# DQ12 24 112 VDD13 VSS28 133
M_B_A14 80 34 M_B_DQ1 [3] 117 134
M_B_A15 78 A14 DQ14 36 118 VDD15 VSS30 138
39 123 139

DQ16 M_B_DQ13 [3] VDD17 VSS32
109 41 M_B_DQ12 [3] 124 144
[3] M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ11 [3] 145
[3] M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ10 [3] 199 150
[3] M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ9 [3] 151
[3] M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ8 [3] 77 155
[3] M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ15 [3] 122 156
[3] M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ14 [3] R327 *10K_4 125 161
[3] M_B_CLK0# CK0# DQ23 +3V NCTEST VSS39
102 57 M_B_DQ30 [3] 162
[3] M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ27 [3] PM_EXTTS#1 198 167
[3] M_B_CLK1# CK1# DQ25 EVENT# VSS41
73 67 M_B_DQ29 [3] 30 168
[3] M_B_CKE0 CKE0 DQ26 [4,14] DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ28 [3] C283 *0.1u/10V_4 172
[3] M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ31 [3] 173
[3] M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ26 [3] +SMDDR_VREF_DQ1 +SMDDR_VREF_DQ1 1 178
[3] M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ24 [3] 126 179
[3] M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R312 10K_4 DIMM1_SA0 197 70 M_B_DQ25 [3] 184
R319 10K_4 DIMM1_SA1 201 SA0 DQ31 129 VSS47 185
+3V SA1 DQ32 M_B_DQ36 [3] VSS48
202 131 M_B_DQ37 [3] 2 189
[8,13,14,24] CLK_SCLK 200 SCL DQ33 141 3 VSS1 VSS49 190
[8,13,14,24] CLK_SDATA SDA DQ34 M_B_DQ34 [3] VSS2 VSS50
143 M_B_DQ38 [3] 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ33 [3] 9 196
[4] M_B_ODT0_DIMM ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ32 [3] 13
[4] M_B_ODT1_DIMM ODT1 DQ37 VSS5
140 M_B_DQ35 [3] 14
11 DQ38 142 19 VSS6
DM0 DQ39 M_B_DQ39 [3] VSS7
28 147 M_B_DQ42 [3] 20
46 DM1 DQ40 149 25 VSS8
DM2 (204P) DQ41 M_B_DQ43 [3] VSS9
63 157 M_B_DQ45 [3] 26 203 +DDR_VTT_RUN
136 DM3 DQ42 159 31 VSS10 VTT1 204
DM4 DQ43 M_B_DQ47 [3] VSS11 VTT2
153 146 M_B_DQ41 [3] 32
170 DM5 DQ44 148 37 VSS12 205
DM6 DQ45 M_B_DQ40 [3] VSS13 GND
187 158 M_B_DQ44 [3] 38 206
DM7 DQ46 160 43 VSS14 GND
DQ47 M_B_DQ46 [3] VSS15
M_B_DQS2 12 163 M_B_DQ55 [3]
M_B_DQS0 29 DQS0 DQ48 165
DQS1 DQ49 M_B_DQ51 [3]
M_B_DQS1 47 175 M_B_DQ48 [3] DDR3-DIMM1_H=4.0_RVS
M_B_DQS3 64 DQS2 DQ50 177
M_B_DQS4 137 164 M_B_DQ52 [3]
M_B_DQS5 154 DQS4 DQ52 166
M_B_DQS6 171 174 M_B_DQ53 [3]
M_B_DQS7 188 DQS6 DQ54 176
[3] M_B_DQS[7:0] DQS7 DQ55 M_B_DQ50 [3]
M_B_DQS#2 10 181 M_B_DQ56 [3]
M_B_DQS#0 27 DQS#0 DQ56 183
DQS#1 DQ57 M_B_DQ61 [3]
M_B_DQS#1 45 191 M_B_DQ58 [3]
M_B_DQS#3 62 DQS#2 DQ58 193
DQS#3 DQ59 M_B_DQ60 [3]
M_B_DQS#4 135 180 M_B_DQ57 [3]
M_B_DQS#5 152 DQS#4 DQ60 182
DQS#5 DQ61 M_B_DQ62 [3]
B M_B_DQS#6 169 192 M_B_DQ59 [3] B
M_B_DQS#7 186 DQS#6 DQ62 194
[3] M_B_DQS#[7:0] DQS#7 DQ63 M_B_DQ63 [3]
M1 solution
1A-22013/10/16 Swap M_B_DQS2/M_B_DQS3 and swap DDR3-DIMM1_H=4.0_RVS +1.35V_SUS
M_B_DQS#2/M_B_DQS#3.
R308 Vref_DQ
1.8K/F_4
+1.35V_SUS Place these Caps near SO-DIMM +SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C275 C256 C284 C277 C253 +VREFDQ_SB_M3 R297 *Short_6 R305 2/F_6
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
2
C278 + C290 C281 C304 C264 C259
M3 solution C246 R309 C261
330u/2V_7343 0.022u/16V_4 1.8K/F_4 470p/50V_4
1
10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C258 C257 C254 C280 C279 2.2u/6.3V_6 2.2u/6.3V_6 R299

10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 24.9/F_4
+3V +DDR_VTT_RUN
A C249 C274 C262 C285 C265 C267 C273 A

C248 C260 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
2.2u/6.3V_6 0.1u/10V_4 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
SA1 SA0
CHA 0 0 Quanta Computer Inc.
PROJECT : ZQ0
CHB 1 0 Size Document Number Rev
3A
DDRIII Memory SO-DIMM B
5 4 3 2 1
1 2 3 4 5 6 7 8
+1.05V_GFX
C31
C33
Near GPU
EV@22U/6.3VS_6
EV@22U/6.3VS_6
U21A
1/14 PCI_EXPRESS
NVDD = 32.22 ~ 26.66 A +VGPU_CORE

14
C41 EV@10U/6.3VS_6 PEX_WAKE AB6 1B-7
C40 EV@10U/6.3VS_6 2013/12/20 del c8521 and R8391. Under GPU U21E
C34 EV@4.7U/6.3V_6 AA22 PEX_IOVDD 11/14 NVVDD
AB23 PEX_IOVDD PEX_RST AC7 C53 EV@1U/6.3V_4 K10 VDD
PEGX_RST# [19]
AC24 C56 EV@1U/6.3V_4 K12
C82 EV@1U/6.3V_4 AD25
PEX_IOVDD
PEX_IOVDD PEX_CLKREQ AC6 PEX_CLKREQ# R56 EV@10K/F_4
+3V_GFX C55 EV@1U/6.3V_4 K14
VDD
VDD U21C VDD33 = 56mA
A C52 EV@1U/6.3V_4 AE26 PEX_IOVDD C54 EV@1U/6.3V_4 K16 VDD 14/14 XVDD/VDD33 A
AE27 PEX_IOVDD PEX_REFCLK AE8 C39 EV@4.7U/6.3V_6 K18 VDD
CLK_PCIE_VGA [9]
Under GPU PEX_REFCLK AD8 C87 EV@4.7U/6.3V_6 L11 VDD AD10 NC VDD33 G10
CLK_PCIE_VGA# [9] +3V_GFX
C83 EV@4.7U/6.3V_6 L13 VDD AD7 NC VDD33 G12
AC9 PEG_RX0_C C430 EV@0.22U/10V_4 C80 EV@4.7U/6.3V_6 L15 B19 G8
PEX_IOVDD + PEX_IOVDDQ = 1.042A PEX_TX0
PEX_TX0 AB9 PEG_RX0#_C C429 EV@0.22U/10V_4
PEG_RX0
PEG_RX#0
[9]
[9] C90 EV@4.7U/6.3V_6 L17
VDD
VDD
NC VDD33
VDD33 G9
C42 EV@4.7U/6.3V_6 M10 VDD
PEX_RX0 AG6 C57 EV@4.7U/6.3V_6 M12 VDD F11 3V3AUX_NC Near GPU
+1.05V_GFX PEG_TX0 [9]
C32 EV@22U/6.3VS_6 AA10 PEX_IOVDDQ PEX_RX0 AG7 C91 EV@4.7U/6.3V_6 M14 VDD C109 EV@4.7U/6.3V_6
PEG_TX#0 [9]
C29 EV@22U/6.3VS_6 AA12 PEX_IOVDDQ C78 EV@4.7U/6.3V_6 M16 VDD V5 FERMI_RSVD1_NC C1101 2 EV@1U/10V_6
C44 EV@10U/6.3VS_6 AA13 PEX_IOVDDQ PEX_TX1 AB10 PEG_RX1_C C428 EV@0.22U/10V_4 C86 EV@4.7U/6.3V_6 M18 VDD V6 FERMI_RSVD2_NC
PEG_RX1 [9]
C26 EV@10U/6.3VS_6 AA16 PEX_IOVDDQ PEX_TX1 AC10 PEG_RX1#_C C427 EV@0.22U/10V_4 N11 VDD
PEG_RX#1 [9]
C43 EV@4.7U/6.3V_6 AA18 PEX_IOVDDQ N13 VDD
AA19 PEX_IOVDDQ PEX_RX1 AF7 2 1 N15 VDD
PEG_TX1 [9]
Near GPU AA20 AE7 C146 N17 C108 EV@0.1U/10V_4
+
PEX_IOVDDQ PEX_RX1 PEG_TX#1 [9] VDD
AA21 PEX_IOVDDQ EV@330u_2.5V_3528 P10 VDD CONFIGURABLE
AB22 PEX_IOVDDQ PEX_TX2 AD11 PEG_RX2_C C420 EV@0.22U/10V_4 P12 VDD POWER CHANNELS
PEG_RX2 [9]
AC23 PEX_IOVDDQ PEX_TX2 AC11 PEG_RX2#_C C418 EV@0.22U/10V_4 P14 VDD * nc on substrate Under GPU
PEG_RX#2 [9]
Under GPU AD24 PEX_IOVDDQ P16 VDD
C60 EV@1U/6.3V_4 AE25 PEX_IOVDDQ PEX_RX2 AE9 P18 VDD G1 XPWR_G1
PEG_TX2 [9]
C45 EV@1U/6.3V_4 AF26 PEX_IOVDDQ PEX_RX2 AF9 R11 VDD G2 XPWR_G2
PEG_TX#2 [9] +3V_MAIN
AF27 PEX_IOVDDQ C85 EV@22U/6.3V_8 R13 VDD G3 XPWR_G3
PEX_TX3 AC12 PEG_RX3_C C425 EV@0.22U/10V_4 C72 EV@10U/6.3VS_6 R15 VDD G4 XPWR_G4
PEG_RX3 [9]
PEX_TX3 AB12 PEG_RX3#_C C423 EV@0.22U/10V_4 R17 VDD G5 XPWR_G5
PEG_RX#3 [9]
C66 EV@4.7U/6.3VS_6 T10 VDD G6 XPWR_G6 C101 EV@4.7U/6.3V_6
PEX_RX3 AG9 C38 EV@4.7U/6.3VS_6 T12 VDD G7 XPWR_G7 C98 1 2 EV@1U/10V_6
PEG_TX3 [9]
PEX_RX3 AG10 C70 EV@4.7U/6.3VS_6 T14 VDD
PEG_TX#3 [9]
C47 EV@4.7U/6.3VS_6 T16 VDD
PEX_TX4 AB13 C49 EV@4.7U/6.3VS_6 T18 VDD V1 XPWR_V1 C93 EV@0.1U/10V_4
AC13 U11 V2 C92 EV@0.1U/10V_4
B PEX_PLL_HVDD + PEX_TX4
Near GPU U13
VDD
VDD
XPWR_V2
B
PEX_SVDD_3V3 = 143mA PEX_RX4 AF10

AE10
U15
U17
VDD Under GPU
PEX_RX4 VDD
V10 VDD
PEX_TX5 AD14 V12 VDD W1 XPWR_W1
+3V_GFX
AA8 PEX_PLL_HVDD PEX_TX5 AC14 V14 VDD W2 XPWR_W2
C107 EV@0.1U/10V_4 AA9 PEX_PLL_HVDD V16 VDD W3 XPWR_W3
C105 EV@4.7U/6.3V_6 PEX_RX5 AE12 V18 VDD W4 XPWR_W4
C106 EV@4.7U/6.3V_6 PEX_RX5 AF12
Near GPU AB8 PEX_SVDD_3V3
PEX_TX6 AC15 bga595-nvidia-n13p-gv2-s-a2 bga595-nvidia-n13p-gv2-s-a2 COMMON
AB15 COMMON
PEX_TX6
PEX_RX6 AG12
PEX_RX6 AG13
SYS_PEX_RST_MON# [19]
PEX_TX7 AB16
PEX_TX7 AC16 +3V
+3V
AF13
SYS_PEX_RST_MON#
PEX_RX7
PEX_RX7 AE13
PEX_TX8 AD17
NC
NC PEX_TX8 AC17 C455
U24 EV@0.1U/10V_4 C456 VDD33
AE15 EVG@MC74VHC1G08DFT2G U22 *EV@0.1U/10V_4
NC PEX_RX8 +3V_GFX/
5
NC PEX_RX8 AF15 *EV@MC74VHC1G08DFT2G
+3V_MAIN
5
2
[7,13,21,24,26,27,30] PLTRST#
F2 VDD_SENSE NC PEX_TX9 AC18 4 R450 *EV@0_4 2 t>0
[37] VGA_VCCSENSE
AB18 1 4 PEGX_RST# NVDD
C 8mils width NC PEX_TX9 [10] DGPU_HOLD_RST#
1 C
(0.2MM) F1 AG15
+VGPU_CORE
GND_SENSE NC PEX_RX9
3
[37] VGA_VSSSENSE AG16
NC PEX_RX9
3
R455 EVG@0_4 PXE_VDD
AB19 R456
NC PEX_TX10
AC19
+1.05V_GFX
NC PEX_TX10 EVG@100K/F_4 t>0
GPU_PEX_RST_HOLD# FBVDDQ
[19] GPU_PEX_RST_HOLD#
AF16
NC PEX_RX10
AE16
+1.35_GFX
NC PEX_RX10
N15x Power on sequance
PEX_TX11 AD20 Un-stuff Sys_PEX_RST_MON# , stuff PEGX_RST# for not GC6
NC
PEX_TX11 AC20
NC
stuff Sys_PEX_RST_MON# for GC6
NC PEX_RX11 AE18
AF18
NC PEX_RX11
Power down
1B-5 2013/12/17 Change R8051 to 0402 size. AC21
NC
NC
PEX_TX12
PEX_TX12 AB21 sequence
*EV@200/F_4 R409 PEX_TSTCLK AF22 PEX_TSTCLK_OUT NC PEX_RX12 AG18
PEX_TSTCLK# AE22 PEX_TSTCLK_OUT PEX_RX12 AG19
NC
CX300T30001 Change to 0ohm
R40 EV@0_4 PEX_TX13 AD23 +3V_GFX
+1.05V_GFX NC
NC PEX_TX13 AE23
Near GPU
EV@4.7U/6.3V_6 C63 PEX_PLLVDD AA14 PEX_PLLVDD PEX_RX13 AF19
NC
EV@1U/6.3V_4 C62 AA15 PEX_PLLVDD NC PEX_RX13 AE19 Follow Z09 to isolate CLK_REQ#
2
EV@0.1U/10V_4 C65 NC PEX_TX14 AF24

Under GPU PEX_TX14 AE24
NC
D PEX_CLKREQ# 1 3 D
PEX_PLLVDD = 130mA NC PEX_RX14 AE21
CLK_PEGA_REQ# [9]
PEX_RX14 AF21 Q7 PU at page 9

NC
EV@10K/F_4 R42 TESTMODE AD9 TESTMODE EV@2N7002K
PEX_TX15 AG24
NC
NC PEX_TX15 AG25
R64 *EV@0_4
NC PEX_RX15 AG21
AG22
NC PEX_RX15
GF117 GF119
PROJECT : ZQ0
EV@2.49K/F_4 R408 PEX_TERMP AF25 PEX_TERMP Size Document Number Rev
3A
N15S-GT (PCIE I/F) /NVDD
bga595-nvidia-n13p-gv2-s-a2 COMMON Date: Tuesday, April 08, 2014 Sheet 16 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R459 *EV@0_4 U21B
15
[17,19,30] EC_FB_CLAMP VMA_DQ[63:0]
2/14 FBA
VMA_DQ[63:0] [20]
R444 EV@10K/F_4 FB_CLAMP F3 NC GF119 FBA_D0 E18 VMA_DQ0
FBA_D1 F18 VMA_DQ1
For GC6 2.0 and 1.0 FB_CLAMP FBA_D2 E16 VMA_DQ2
GF117
stuff EC_FB_CLAMP F17 VMA_DQ3
FBA_D3
FBA_D4 D20 VMA_DQ4 FBVDDQ + FBVDD = 3.116A U21F
FBA_D5 D21 VMA_DQ5 13/14 GND
FBA_D6 F20 VMA_DQ6 +1.35V_GFX U21D A2 GND GND M13
FBA_D7 E21 VMA_DQ7 12/14 FBVDDQ AB17 GND GND M15
PV modify FBA_D8 E15 VMA_DQ8 AB20 GND GND M17
FBA_D9 D15 VMA_DQ9 C4 EV@0.1U/10V_4 B26 FBVDDQ AB24 GND GND N10
FBA_ODT_L FBA_CMD2 R27 EV@10K/F_4 FBA_D10 F15 VMA_DQ10 C2 EV@0.1U/10V_4 C25 FBVDDQ AC2 GND GND N12
FBA_D11 F13 VMA_DQ11 E23 FBVDDQ AC22 GND GND N14
A FBA_ODT_H FBA_CMD18 R10 EV@10K/F_4 FBA_D12 C13 VMA_DQ12 E26 FBVDDQ AC26 GND GND N16 A
FBA_D13 B13 VMA_DQ13 C30 1 2EV@1U/10V_6 F14 FBVDDQ AC5 GND GND N18
FBA_RST# FBA_CMD5 R23 EV@10K/F_4 FBA_D14 E13 VMA_DQ14 C3941 2EV@1U/10V_6 F21 FBVDDQ AC8 GND GND P11
FBA_D15 D13 VMA_DQ15 C12 EV@4.7U/6.3V_6 G13 FBVDDQ AD12 GND GND P13
FBA_CKE_L FBA_CMD3 R28 EV@10K/F_4 FBA_D16 B15 VMA_DQ16 C426 EV@10U/6.3V_6 G14 FBVDDQ AD13 GND GND P15
FBA_D17 C16 VMA_DQ17 C395 EV@22U/6.3VS_6 G15 FBVDDQ A26 GND GND P17
FBA_CKE_H FBA_CMD19 R11 EV@10K/F_4 FBA_D18 A13 VMA_DQ18 C424 EV@4.7U/6.3V_6 G16 FBVDDQ AD15 GND GND P2
FBA_D19 A15 VMA_DQ19 G18 FBVDDQ AD16 GND GND P23
FBA_D20 B18 VMA_DQ20 G19 FBVDDQ AD18 GND GND P26
FBA_D21 A18 VMA_DQ21 G20 FBVDDQ AD19 GND GND P5
FBA_D22 A19 VMA_DQ22 G21 FBVDDQ AD21 GND GND R10
FBA_D23 C19 VMA_DQ23 H24 FBVDDQ AD22 GND GND R12
FBA_D24 B24 VMA_DQ24 H26 FBVDDQ AE11 GND GND R14
FBA_D25 C23 VMA_DQ25 J21 FBVDDQ AE14 GND GND R16
FBA_D26 A25 VMA_DQ26 K21 FBVDDQ AE17 GND GND R18
FBA_D27 A24 VMA_DQ27 L22 FBVDDQ AE20 GND GND T11
FBA_D28 A21 VMA_DQ28 L24 FBVDDQ AB11 GND GND T13
FBA_D29 B21 VMA_DQ29 L26 FBVDDQ AF1 GND GND T15
FBA_D30 C20 VMA_DQ30 M21 FBVDDQ AF11 GND GND T17
FBA_D31 C21 VMA_DQ31 N21 FBVDDQ AF14 GND GND U10
FBA_D32 R22 VMA_DQ32 R21 FBVDDQ AF17 GND GND U12
C27 FBA_CMD0 FBA_D33 R24 VMA_DQ33 T21 FBVDDQ AF20 GND GND U14
[20] FBA_CMD0
TP93 FBA_CMD1 C26 FBA_CMD1 FBA_D34 T22 VMA_DQ34 V21 FBVDDQ AF23 GND GND U16
E24 FBA_CMD2 FBA_D35 R23 VMA_DQ35 W 21 FBVDDQ AF5 GND GND U18
[20] FBA_CMD2
F24 FBA_CMD3 FBA_D36 N25 VMA_DQ36 AF8 GND GND U2
[20] FBA_CMD3
D27 FBA_CMD4 FBA_D37 N26 VMA_DQ37 AG2 GND GND U23
[20] FBA_CMD4
D26 FBA_CMD5 FBA_D38 N23 VMA_DQ38 AG26 GND GND U26
[20] FBA_CMD5
F25 FBA_CMD6 FBA_D39 N24 VMA_DQ39 AB14 GND GND U5
[20] FBA_CMD6
F26 FBA_CMD7 FBA_D40 V23 VMA_DQ40 B1 GND GND V11
[20] FBA_CMD7
F23 FBA_CMD8 FBA_D41 V22 VMA_DQ41 B11 GND GND V13
[20] FBA_CMD8
B G22 FBA_CMD9 FBA_D42 T23 VMA_DQ42 B14 GND GND V15 B
[20] FBA_CMD9
G23 FBA_CMD10 FBA_D43 U22 VMA_DQ43 B17 GND GND V17
[20] FBA_CMD10
G24 FBA_CMD11 FBA_D44 Y24 VMA_DQ44 B20 GND GND Y2
[20] FBA_CMD11
F27 FBA_CMD12 FBA_D45 AA24 VMA_DQ45 B23 GND GND Y23
[20] FBA_CMD12
G25 FBA_CMD13 FBA_D46 Y22 VMA_DQ46 B27 GND GND Y26
[20] FBA_CMD13
G27 FBA_CMD14 FBA_D47 AA23 VMA_DQ47 B5 GND GND Y5
[20] FBA_CMD14
G26 FBA_CMD15 FBA_D48 AD27 VMA_DQ48 B8 GND
[20] FBA_CMD15
M24 FBA_CMD16 FBA_D49 AB25 VMA_DQ49 E11 GND
[20] FBA_CMD16
TP2 FBA_CMD17 M23 FBA_CMD17 FBA_D50 AD26 VMA_DQ50 E14 GND
K24 FBA_CMD18 FBA_D51 AC25 VMA_DQ51 E17 GND
[20] FBA_CMD18
K23 FBA_CMD19 FBA_D52 AA27 VMA_DQ52 E2 GND
[20] FBA_CMD19
M27 FBA_CMD20 FBA_D53 AA26 VMA_DQ53 E20 GND
[20] FBA_CMD20
M26 FBA_CMD21 FBA_D54 W 26 VMA_DQ54 E22 GND
[20] FBA_CMD21
M25 FBA_CMD22 FBA_D55 Y25 VMA_DQ55 E25 GND
[20] FBA_CMD22
K26 FBA_CMD23 FBA_D56 R26 VMA_DQ56 E5 GND
[20] FBA_CMD23
K22 FBA_CMD24 FBA_D57 T25 VMA_DQ57 E8 GND
[20] FBA_CMD24
J23 FBA_CMD25 FBA_D58 N27 VMA_DQ58 H2 GND
[20] FBA_CMD25
J25 FBA_CMD26 FBA_D59 R27 VMA_DQ59 H23 GND
[20] FBA_CMD26
J24 FBA_CMD27 FBA_D60 V26 VMA_DQ60 H25 GND
[20] FBA_CMD27
K27 FBA_CMD28 FBA_D61 V27 VMA_DQ61 FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ R38 EV@40.2/F_4 +1.35V_GFX H5 GND
[20] FBA_CMD28
K25 FBA_CMD29 FBA_D62 W 27 VMA_DQ62 K11 GND
[20] FBA_CMD29
J27 FBA_CMD30 FBA_D63 W 25 VMA_DQ63 K13 GND
[20] FBA_CMD30
TP1 FBA_CMD31 J26 FBA_CMD31 FB_CAL_PU_GND C24 FB_CAL_PU_GND R35 EV@42.2/F_4 K15 GND
K17 GND
FBA_DQM0 D19 VMA_DM0 L10 GND
D14 VMA_DM[7:0] [20] B25 L12
FBA_DQM1 VMA_DM1 FB_CALTERM_GND FB_CAL_TERM_GND R36 EV@51.1/F_4 GND
FBA_DQM2 C17 VMA_DM2 L14 GND
FBA_DQM3 C22 VMA_DM3 L16 GND
P24 VMA_DM4 bga595-nvidia-n13p-gv2-s-a2 L18
FBA_DQM4 GND
FBA_DQM5 W 24 VMA_DM5 COMMON L2 GND
+1.35V_GFX
C
FBA_DQM6 AA25 VMA_DM6 L23 GND C
R33 *EV@60.4_4F22 FBA_DEBUG0 FBA_DQM7 U25 VMA_DM7 L25 GND
R39 *EV@60.4_4J22 FBA_DEBUG1 L5 GND GND AA7
M11 GND GND AB7
FBA_DQS_WP0 E19 VMA_WDQS0
C15 VMA_WDQS1 VMA_WDQS[7:0] [20]
FBA_DQS_WP1
D24 FBA_CLK0 FBA_DQS_WP2 B16 VMA_WDQS2
[20] VMA_CLK0
D25 FBA_CLK0 FBA_DQS_WP3 B22 VMA_WDQS3 bga595-nvidia-n13p-gv2-s-a2 COMMON
[20] VMA_CLK0#
N22 FBA_CLK1 FBA_DQS_WP4 R25 VMA_WDQS4
[20] VMA_CLK1
M22 FBA_CLK1 FBA_DQS_WP5 W 23 VMA_WDQS5
[20] VMA_CLK1# +3V_GFX
FBA_DQS_WP6 AB26 VMA_WDQS6
FBA_DQS_WP7 T26 VMA_WDQS7
DGPU_PGOK-1
D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0 +3V R70
C18 C14 VMA_RDQS[7:0] [20]
FBA_WCK01 FBA_DQS_RN1 VMA_RDQS1 EV@4.7K_4
3
D17 FBA_WCK23 FBA_DQS_RN2 A16 VMA_RDQS2
D16 FBA_WCK23 FBA_DQS_RN3 A22 VMA_RDQS3 R58 EV@4.7K_4 DGPU_POK4 2 Q8
[38] HWPG_1.5VGFX
T24 FBA_WCK45 FBA_DQS_RN4 P25 VMA_RDQS4 EV@METR3904-G R74
DGPU_PWROK [10]
U24 FBA_WCK45 FBA_DQS_RN5 W 22 VMA_RDQS5 EV@4.7K_4
1
V24 FBA_WCK67 FBA_DQS_RN6 AB27 VMA_RDQS6 C120
3
V25 FBA_WCK67 FBA_DQS_RN7 T27 VMA_RDQS7 *EV@1000P/50V_4
FB_PLLAVDD = 55mA 2 Q9 R71
EV@DTC144EUA
L1 EV@BLM15PX331SN1D +FB_PLLAVDD F16 FB_PLLAVDD
+1.05V_GFX +3V
1
C59 EV@22U/6.3VS_6 P22 FB_PLLAVDD C123 EV@100K/F_4
C67 EV@0.1U/10V_4 EV@1000P/50V_4
C81 EV@0.1U/10V_4 H22 FB_DLLAVDD GF119
D C84 EV@0.1U/10V_4 *EV@0.1u/10V_4 C454 C453 D
EV@0.1U/10V_4
FB_PLLAVDD GF117
GPU_PWR_GD ,PD at GPU power side 5
R477 EV@0_4 2
[37] GPU_PWR_GD
FB_DLLAVDD = 15mA 4
FBVDDQ_EN [38]
R469 EV@0_4 1
D23
[10,19] GC6_FB_EN
FB_VREF_PROBE [17,19,30] EC_FB_CLAMP R471 *EV@0_4
INT EV@SN74AHC1G32DCKR U23
PROJECT : ZQ0
3
R476
bga595-nvidia-n13p-gv2-s-a2 COMMON
stuff EC_FB_CLAMP for GC6 1.0 EV@100K/F_4 Size Document Number Rev
3A
stuff GC6_FB_EN for GC6 2.0 N15S-GT (MEMEORY/GND)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
U21G U21J U21K 1B-7
16
4/14 IFPAB 3/14 DACA 2013/12/20 Change resistor to 2.2k.
7/14 IFPEF
GF117 GF119 GF119 GF119 GF117
GF117 GF117 GF119
NC IFPA_TXC AC4 W5 DACA_VDD I2CA_SCL B7 I2CA_SCL R430 EV@2.2K_4
DVI-DL DVI-SL/HDMI DP NC NC
IFPA_TXC AC3 I2CA_SDA A7 I2CA_SDA R429 EV@2.2K_4
NC NC
GF119 GF117 IFPE_AUX J3 AE2 DACA_VREF
GF119 GF117 NC I2CY_SDA I2CY_SDA TSEN_VREF
AA6 IFPAB_RSET NC NC I2CY_SCL I2CY_SCL IFPE_AUX J2
IFPA_TXD0 Y3 J7 IFPEF_PLLVDD AF2 DACA_RSET DACA_HSYNC AE3
NC NC NC NC
IFPA_TXD0 Y4 DACA_VSYNC AE4
NC NC
IFPE_L3 J1
NC TXC TXC
V7 IFPAB_PLLVDD IFPE_L3 K1
NC NC TXC TXC
NC IFPA_TXD1 AA2 K7 IFPEF_PLLVDD NC DACA_RED AG3
NC
W7 IFPAB_PLLVDD IFPA_TXD1 AA3 IFPE_L2 K3
NC NC NC TXD0 TXD0
A
IFPE_L2 K2 DACA_GREEN AF4 A
NC TXD0 TXD0 NC
IFPA_TXD2 AA1 K6 IFPEF_RSET IFPE_L1 M3 DACA_BLUE AF3

NC NC NC TXD1 TXD1 NC
NC IFPA_TXD2 AB1 IFPE_L1 M2
NC TXD1 TXD1
IFPE_L0 M1 27M_XTAL_IN_R
AA5 NC TXD2 TXD2 N1 27M_XTAL_OUT
NC IFPA_TXD3 NC TXD2 TXD2 IFPE_L0
IFPA_TXD3 AA4 bga595-nvidia-n13p-gv2-s-a2 COMMON Y3
NC
1 3
IFPE 2 4
IFPB_TXC AB4
NC
IFPB_TXC AB5 PLLVDD = 38mA C434 EV@27MHZ C431
NC
NC HPD_E HPD_E GPIO18 C2 EV@10p/50V_4 EV@10p/50V_4
GF119 GF117 L6 EV@BLM15PX331SN1D NV_PLLVDD
+1.05V_GFX
W6 IFPA_IOVDD IFPB_TXD4 AB2 C102 EV@0.1U/10V_4
NC NC
IFPB_TXD4 AB3 C103 EV@22U/6.3VS_6
NC GF119 GF117
Y6 IFPB_IOVDD NC
H6 IFPE_IOVDD NC
NC IFPB_TXD5 AD2 GF119
IFPB_TXD5 AD3 J6 IFPF_IOVDD GF117 SP_PLLVDD = 17mA U21M
NC NC DVI-DL DVI-SL/HDMI DP
9/14 XTAL_PLL
NC IFPF_AUX H4 L4 EV@BLM15PX181SN1D SP_PLLVDD
I2CZ_SDA +1.05V_GFX
IFPB_TXD6 AD1 NC I2CZ_SCL IFPF_AUX H3 C95 EV@0.1U/10V_4 L6 PLLVDD
NC
NC IFPB_TXD6 AE1 C94 EV@0.1U/10V_4 M6 SP_PLLVDD
C96 EV@4.7U/6.3V_6
NC TXC IFPF_L3 J5 C97 EV@22U/6.3VS_6 N6 VID_PLLVDD GF119
IFPB_TXD7 AD5 NC TXC IFPF_L3 J4
NC
IFPB_TXD7 AD4
NC NC GF117
NC TXD3 TXD0 IFPF_L2 K5 VID_PLLVDD = 41mA
NC IFPF_L2 K4
TXD3 TXD0
B B
NC TXD4 TXD1 IFPF_L1 L4 R420 XTAL_SSIN A10
EV@10K/F_4 XTALSSIN XTALOUTBUFF C10BXTALOUT R424 EV@10K/F_4
IFPF NC TXD4 TXD1 IFPF_L1 L3
NC GPIO14 B3
IFPAB NC
NC
TXD5
TXD5
TXD2
TXD2
IFPF_L0
IFPF_L0
M5
M4
27M_XTAL_IN_R C11 XTALIN XTALOUT B10 27M_XTAL_OUT
bga595-nvidia-n13p-gv2-s-a2 COMMON bga595-nvidia-n13p-gv2-s-a2 COMMON
U21H
5/14 IFPC
IFPC NC HPD_F GPIO19 F7
GF119 GF117
T6 IFPC_RSET GF117 GF119
NC
DVI/HDMI DP
M7 N5 bga595-nvidia-n13p-gv2-s-a2 COMMON
IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX
N7 IFPC_PLLVDD NC I2CW_SCL IFPC_AUX N4
NC
N3
3V MAIN POWER
NC TXC IFPC_L3
NC IFPC_L3 N2
TXC
+3V_GFX +3V_GFX
IFPC_L2 R3
NC TXD0
IFPC_L2 R2
NC TXD0
TXD1 IFPC_L1 R1
NC
IFPC_L1 T1 +3V_GFX R324 C117 60mil
NC TXD1
*EV@10K_4
1
IFPC_L0 T3 *EV@0.022U/25V_4
NC TXD2
C
IFPC_L0 T2 R50 C
NC TXD2
EVG@0_8
R439 R57 *EV@200K_4 2
*EV@10K_4
P6 IFPC_IOVDD NC GPIO15 C3
NC
3
*EV@AO3413 60mil
+3V_MAIN
3
bga595-nvidia-n13p-gv2-s-a2 COMMON C116 Q6
2
[19] 3V_MAIN_EN
U21I *EV@0.022U/25V_4
6/14 IFPD Q40 N15V stuff not support GC6.
*EV@2N7002K 1A-7 2013/10/21 add R5331 for not GC6 support.
GF119 GF117
1
U6 GF117 GF119
IFPD_RSET NC
DVI/HDMI DP
T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX P4

NC NC
NC I2CX_SCL IFPD_AUX P3
R7 IFPD_PLLVDD +3V_GFX
NC
IFPD_L3 R5
NC TXC
IFPD_L3 R4
NC TXC
+3V
IFPD_L2 T5 R84
NC TXD0
IFPD_L2 T4 EV@4.7K_4
NC TXD0
TXD1 IFPD_L1 U4 R82 3V_MAIN_PWGD

NC 3V_MAIN_PWGD [37,38]
IFPD NC TXD1 IFPD_L1 U3 EV@4.7K_4
3
D
IFPD_L0 V4 R83 D
NC TXD2
IFPD_L0 V3 2 *EV@100K/F_4
NC TXD2
3
2
+3V_MAIN R85 EV@4.7K_4
C51 Q11
1
R6 IFPD_IOVDD GPIO17 D4 Q12 EV@1000p/50V_4 EV@DTC144EU

GF119 NC
1
C64 EV@MMBT3904-7-F
NC GF117 *EV@1000p/50V_4 +1.05V_GFX and GPU core power EN Quanta Computer Inc.
PROJECT : ZQ0
bga595-nvidia-n13p-gv2-s-a2 COMMON 3A
N15S-GT (DISPALY)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3V_MAIN +3V_GFX
17
4.99k CS24992FB26 Default: HYNIX
U21L 10k CS31002FB26 Logical Strap Bit Mapping
15k CS31502FB24
10/14 MISC2
R413 20k CS32002FB29 PU-VDD PD
*EV@4.99K/F_4 24.9k CS32492FB16 R463 R457
+3V_GFX 30.1k CS33012FB18 EV@49.9K/F_4 *EV@30.1K/F_4 R462
TP6 E10 VMON_IN0 R411 R415 34.8k CS33482FB22 *EV@10K/F_4 4.99K 1000 0000
TP4 F10 D12 ROM_CS R41 EV@10K_4 *EV@10K/F_4 *EV@4.99K/F_4 45.3k CS34532FB18 R461 R460
For N15S-GT sku
VMON_IN1 ROM_CS
*EV@10K/F_4 *EV@10K/F_4 10K 1001 0001
B12 ROM_SI ROM_SI STRAP0
N15S-GT device ID=0x0FE4 ROM_SI
ROM_SO A12 ROM_SO ROM_SO N15S-GT STRAP1 15K 1010 0010
R3=40.3k pull down. STRAP0 D1 C12 ROM_SCLK ROM_SCLK STRAP2
1.ROM_SCLK =4.99K pull down STRAP1 D2
STRAP0
STRAP1
ROM_SCLK
STRAP1---> 50k PU STRAP3 20K 1011 0011
A
2.ROM_SO = 4.99K pull down STRAP2 E4 N15V-GM\GL STRAP4 A
3.ROM_SI= Memory strap setting STRAP3 E3

STRAP2
STRAP3 STRAP4---> 10k PD 24.9K 1100 0100
2
STRAP4 D3 R410 R414 R445 R443 R441
3.STRAP0 = 50k Pull pu. STRAP4
EV@4.99K/F_4 EV@4.99K/F_4 *EV@24.9K/F_4 *EV@15K/F_4 *EVG@10K/F_4 30.1K 1101 0101
4.Strap4~1 = reserve Pull pu R412
and Pull down GF119 GF117
EV@4.99K/F_4 R440 R436 34.8K 1110 0110
C1 *EV@45.3K/F_4 *EV@4.99K/F_4
STRAP5_NC NC 45.3K 1111 0111
1
For N15V-GL-B and N15V-GM-B sku BUFRST D11
Board_ID0= R442 F6 MULTISTRAP_REF0_GND
EV@40.2K/F_4 D10 N15S Based on RVL. N15S Strap0 pull up 50k, strap1~4 reverve only.
PGOOD
H=N15V-GM,L=N15V-GL N15V pull down10k. N15V Strap4 pull down 10k, strap0~3 based on RVL binary setting.
Device ID=0x1140 R3 GF119 GF117
Pull Down 4.99k for N15S-GT.
R3= N.C. R458 *EV@10K/F_4 +3V_GFX Pull Down 10k for N15V.
1.ROM_SCLK =10K pull down. F4 MULTISTRAP_REF1_GND NC
E9 SYS_PEX_RST_MON#
2.ROM_SI= 10k pull down F5
CEC SYS_PEX_RST_MON# [16]
MULTISTRAP_REF2_GND
3.ROM_SO= 10k pull down NC +3V_GFX
4.Strap3~0 = RVL memory +3V_MAIN
binary mode setting. bga595-nvidia-n13p-gv2-s-a2 COMMON
5.Strap4 =10k pull down
R44 R46
Q5 EV@4.7K_4 EV@4.7K_4
5
U21N
8/14 MISC1 1B-7 3 4 GPUT_CLK_L
[8,30] 2ND_MBCLK
I2CS_SCL D9 GPUT_CLK_L 2013/12/20 Change resistor to 2.2k.
I2CS_SDA D8 GPUT_DATA_L
2
I2CC_SCL A9 DGPU_EDIDCLK R421 EV@2.2K_4
B B9 DGPU_EDIDDATA R425 EV@2.2K_4 6 1 GPUT_DATA_L B
I2CC_SDA [8,30] 2ND_MBDATA
EC/S5 VGA/VGA
TP3 THERM- E12 THERMDN GF117 GF119 EV@2N7002DW
I2CB_SCL C9 N12E_SCL R427 EV@2.2K_4
NC
TP5 THERM+ F12 THERMDP I2CB_SDA C8 N12E_SDA R426 EV@2.2K_4
NC
EC_FB_CLAMP [17,30]
GC6_FB_EN [10,17]
TP101 JTAG_TCK AE5 JTAG_TCK R449 EV@0_4 VRAM Configuration Table
TP102 JTAG_TMS AD6 JTAG_TMS +3V_GFX
TP99 JTAG_TDI AE6 JTAG_TDI
TP98 JTAG_TDO AF6 JTAG_TDO 1 3 R468 *EVG@0_4 ROM_SI DESCRIPTION Vendor Vendor P/N QCI P/N STN P/N
JTAG_TRST# AG4 JTAG_TRST GPIO0 C6 FB_CLAMP_MON R467 EV@0_4
GPIO1 B2 Q24 R451 *EV@10K/F_4 0000 DDR3(L) 256MBx16x4, 64bit,1000MHz( HYNIX H5TC4G63AFR-11C AKD5PGWTW05 AKD5PGWTW13
GPIO2 D6 *EVG@2N7002K EV@10K/F_4 R447 *EV@0_4 R482 *EVG@0_4 FB_CLAMP_REQ# [30] 0010(0101)
DDR3(L) 256MBx16x4, 64bit,,1000MHz(900MHz) SAMSUNG K4W4G1646D-BC1A
2
GPIO3 C7 R464 R481 *EV@0_4 0110(1001)
DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) HYNIX H5TC2G63FFR-11C
F9 DGPU_EVENT# [10]
GPIO4 +3V_GFX 0111(1010) DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO MT41J128M16JT-093G:K
GPIO5 A3 3V_MAIN_EN 3V_MAIN_EN [18] 1000(1011) DDR3(L) 128MBx16x4, 64bit,,1000MHz(900MHz) SAMSUNG K4W2G1646Q-BC1A
GPIO6 A4 FB_CLAMP_REQ#_R 1 3 0001(0100) DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO MT41J256M16HA-093G:E
GPIO7 B6
GPIO8 A6 VGA_OVT# R434 Q26
GPIO9 F8 VGA_ALERT# *EVG@2N7002K
2
GPIO10 C5 Strap
GPIO11 E7 PWM-VID [37] EVG@10K/F_4 [3:0] DESCRIPTION Vendor Vendor P/N QCI P/N Note
GPIO12 D7 GPIO12_ACIN
GPIO13 B4 DGPU_PSI 0100 DDR3(L) 256MBx16x4, 64bit,1000MHz(900MHz) HYNIX H5TC4G63AFR-11C
DGPU_PSI [37]
1100 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) HYNIX H5TC2G63FFR-11C
+3V_GFX 0001 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO MT41J128M16JT-093G:K
GF117 GF119
1101 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO MT41J256M16HA-093G:E
GPIO16 D5 N15S -> GPIO0 un-stuff Q24 and EC_FB_CLAMP.
C NC C
NC GPIO20 E6 GPIO6 Un-stuff Q26\R70 and FB_CLAMP_REQ#.
GPIO21 C4 GPU_PEX_RST_HOLD#
NC GPU_PEX_RST_HOLD# [16]
N15V -> GPIO0 stuff Q24 and EC_FB_CLAMP, un-stuff R75 GC6_FB_EN.
GPIO6 stuff Q26\R70 and FB_CLAMP_REQ#, un-stuff R76,FB_Clamp_req#. GPIO I/O PIN USAGE
1C1-1 2014/02/6 add VGA_ALERT# PU +3V_GFX
bga595-nvidia-n13p-gv2-s-a2 COMMON 10K for FAE request.
VGA_ALERT# R689 EV@10K/F_4 0 IN FB_CLAMP_MON FB Clamp monitor
R435 EV@0_4 GPIO12_ACIN R448 EV@10K/F_4 1 OUT MEM_VDD_CTL Memory VDD VID
[16] PEGX_RST#
2 OUT LCD_BL_PWM Panel Backlight PWM
DGPU_PSI R437 *EV@10K/F_4
3 OUT LCD_VCC PANEL POWER ENABLE
2
dGPU_OPP# = EC control 4 OUT LCD_BLEN PANEL BACKLIGHT ENABLE

VGA_OVT# 1 3 VGA_OVT# R431 EV@10K/F_4
dGPU_OTP# [30]
GPIO12_ACIN 1 3
dGPU_OPP# [30] 5 OUT Reserved --
Q38 Q39 GPIO12 AC detect GPU_PEX_RST_HOLD# R472 EV@10K/F_4
EV@2N7002K EV@2N7002K AC high
6 OUT FB_CLAMP_TGL_REQ Active low FB Clamp toggle request
2
DC low
3V_MAIN_EN R438 *EV@10K/F_4 7 OUT 3D VISION 3D VISION LEFT/RIGHT signal
JTAG_TMS R678 *EV@10K/F_4
8 I/O OVERT ACTIVE LOW THERMAL OVER TEMP
+3V_GFX
JTAG_TDI R677 *EV@10K/F_4
9 I/O ALERT ACTIVE LOW THERMAL ALERT
10 OUT MEM VREF_CTL MEMMORY VREF CONTROL
JTAG_TRST# R419 EV@10K/F_4
11 OUT PWR_VID GPU CORE_VDD PWM Control signal
D JTAG_TCK R679 *EV@10K/F_4 D
12 IN PWR_LEVEL AC Power detect or power supply overdraw input
13 OUT PSI Phase Shedding
1C-2 2014/01/13 add R678\R677 PU and R679 PD
for ICT.
GPIO ASSIGNMENTS
PROJECT : ZQ0
3A
N15S-GT (GPIO/STRAPS)
1 2 3 4 5 6 7 8
5 4 3 2 1
MP-1 20140401 update Footprint like as ZQN. ：AKD5PGWTW08---AKD5PGWTW07

HYU 256Mx16, PN：
[17]
[17]
[17]
[17]
VMA_DQ[63..0]
VMA_DM[7..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0]
CHANNEL A: 256MB/512MB DDR3 ：AKD5MZDTW03---AKD5MZDTW02
HYU 128Mx16, PN：
SAM 256Mx16, PN：

QBC
：AKD5PZDT501---AKD5PZDT500
：AKD5MGGT535---AKD5MGGT534
SAM 128Mx16, PN：
TOP B/S
18
VRAM2 VRAM4 VRAM1 VRAM3
VREFC_VMA1 M8 E3 VMA_DQ11 VREFC_VMA1 M8 E3 VMA_DQ25 VREFC_VMA3 M8 E3 VMA_DQ40 VREFC_VMA3 M8 E3 VMA_DQ62

VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ9 VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ28 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ45 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ59
VREFDQ DQL1 F2 VMA_DQ14 VREFDQ DQL1 F2 VMA_DQ27 VREFDQ DQL1 F2 VMA_DQ42 VREFDQ DQL1 F2 VMA_DQ60
N3 DQL2 F8 VMA_DQ8 FBA_CMD9 N3 DQL2 F8 VMA_DQ29 FBA_CMD9 N3 DQL2 F8 VMA_DQ46 FBA_CMD9 N3 DQL2 F8 VMA_DQ56
D [17] FBA_CMD9 P7 A0 DQL3 H3 P7 A0 DQL3 H3 P7 A0 DQL3 H3 P7 A0 DQL3 H3 D
VMA_DQ12 FBA_CMD11 VMA_DQ26 FBA_CMD11 VMA_DQ43 FBA_CMD11 VMA_DQ61
[17] FBA_CMD11 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
P3 H8 VMA_DQ10 FBA_CMD8 P3 H8 VMA_DQ31 FBA_CMD8 P3 H8 VMA_DQ47 FBA_CMD8 P3 H8 VMA_DQ58
[17] FBA_CMD8 N2 A2 DQL5 G2 N2 A2 DQL5 G2 N2 A2 DQL5 G2 N2 A2 DQL5 G2
P8 H7 VMA_DQ13 FBA_CMD10 P8 H7 VMA_DQ30 FBA_CMD10 P8 H7 VMA_DQ44 FBA_CMD10 P8 H7 VMA_DQ57
P2 FBA_CMD24 P2 FBA_CMD24 P2 FBA_CMD24 P2
[17] FBA_CMD24 R8 A5 R8 A5 R8 A5 R8 A5
FBA_CMD22 FBA_CMD22 FBA_CMD22
[17] FBA_CMD22 A6 A6 A6 A6
R2 D7 VMA_DQ5 FBA_CMD7 R2 D7 VMA_DQ16 FBA_CMD7 R2 D7 VMA_DQ34 FBA_CMD7 R2 D7 VMA_DQ54
[17] FBA_CMD7 T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3
[17] FBA_CMD21 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
R3 C8 VMA_DQ6 FBA_CMD6 R3 C8 VMA_DQ18 FBA_CMD6 R3 C8 VMA_DQ32 FBA_CMD6 R3 C8 VMA_DQ55
L7 C2 VMA_DQ2 FBA_CMD29 L7 C2 VMA_DQ21 FBA_CMD29 L7 C2 VMA_DQ38 FBA_CMD29 L7 C2 VMA_DQ51
[17] FBA_CMD29 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
N7 A2 VMA_DQ3 FBA_CMD28 N7 A2 VMA_DQ22 FBA_CMD28 N7 A2 VMA_DQ37 FBA_CMD28 N7 A2 VMA_DQ50
[17] FBA_CMD28 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8
T7 A3 VMA_DQ0 FBA_CMD4 T7 A3 VMA_DQ20 FBA_CMD4 T7 A3 VMA_DQ39 FBA_CMD4 T7 A3 VMA_DQ49
M7 FBA_CMD14 M7 FBA_CMD14 M7 FBA_CMD14 M7
[17] FBA_CMD14 A15 A15 A15 A15
M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2

[17] FBA_CMD12 BA0 VDD#B2 +1.35V_GFX BA0 VDD#B2 BA0 VDD#B2 +1.35V_GFX BA0 VDD#B2
N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9
[17] FBA_CMD27 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7
[17] FBA_CMD26 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
[17] VMA_CLK0 CK VDD#N9 CK VDD#N9 [17] VMA_CLK1 CK VDD#N9 CK VDD#N9
K7 R1 VMA_CLK0# K7 R1 K7 R1 VMA_CLK1# K7 R1
[17] VMA_CLK0# CK VDD#R1 CK VDD#R1 [17] VMA_CLK1# CK VDD#R1 CK VDD#R1 +1.35V_GFX
K9 R9 FBA_CMD3 K9 R9 K9 R9 FBA_CMD19 K9 R9
[17] FBA_CMD3 CKE VDD#R9 CKE VDD#R9 +1.35V_GFX [17] FBA_CMD19 CKE VDD#R9 CKE VDD#R9
K1 A1 FBA_CMD2 K1 A1 K1 A1 FBA_CMD18 K1 A1
[17] FBA_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 [17] FBA_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
L2 A8 FBA_CMD0 L2 A8 L2 A8 FBA_CMD16 L2 A8
C [17] FBA_CMD0 J3 CS VDDQ#A8 C1 J3 CS VDDQ#A8 C1 [17] FBA_CMD16 J3 CS VDDQ#A8 C1 J3 CS VDDQ#A8 C1 C
[17] FBA_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
[17] FBA_CMD15 L3 CAS VDDQ#C9 D2 L3 CAS VDDQ#C9 D2 L3 CAS VDDQ#C9 D2 L3 CAS VDDQ#C9 D2
[17] FBA_CMD13 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_WDQS1 F3 VDDQ#F1 H2 VMA_WDQS3 F3 VDDQ#F1 H2 VMA_WDQS5 F3 VDDQ#F1 H2 VMA_WDQS7 F3 VDDQ#F1 H2
VMA_RDQS1 G3 DQSL VDDQ#H2 H9 VMA_RDQS3 G3 DQSL VDDQ#H2 H9 VMA_RDQS5 G3 DQSL VDDQ#H2 H9 VMA_RDQS7 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9
VMA_DM1 E7 A9 VMA_DM3 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 D3 DML VSS#A9 B3 VMA_DM2 D3 DML VSS#A9 B3 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_WDQS0 C7 VSS#G8 J2 VMA_WDQS2 C7 VSS#G8 J2 VMA_WDQS4 C7 VSS#G8 J2 VMA_WDQS6 C7 VSS#G8 J2
VMA_RDQS0 B7 DQSU VSS#J2 J8 VMA_RDQS2 B7 DQSU VSS#J2 J8 VMA_RDQS4 B7 DQSU VSS#J2 J8 VMA_RDQS6 B7 DQSU VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9
[17] FBA_CMD5 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R32 VSSQ#B9 D1 R407 VSSQ#B9 D1 R7 VSSQ#B9 D1 R404 VSSQ#B9 D1
Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1
Ohms +-1% EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
B J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 B
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16
+1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX
VMA_CLK0
R405 R37 R12 R401
EV@1.33K/F_4 EV@1.33K/F_4 VMA_CLK1 EV@1.33K/F_4 EV@1.33K/F_4
R31
EV@160/F_4 VREFC_VMA1 VREFD_VMA1 VREFC_VMA3 VREFD_VMA3
R9
VMA_CLK0# EV@160/F_4
R406 C413 R34 C28 R8 C1 R400 C400
EV@1.33K/F_4 EV@0.1U/10V_4 EV@1.33K/F_4 EV@0.1U/10V_4 EV@1.33K/F_4 EV@0.1U/10V_4 EV@1.33K/F_4 EV@0.1U/10V_4
VMA_CLK1#
+1.35V_GFX
+1.35V_GFX
A C412 EV@10U/6.3V_6 C393 EV@10U/6.3V_6 +1.35V_GFX A
+1.35V_GFX C401 EV@1U/6.3V_4 C392 EV@10U/6.3V_6 C421 EV@10U/6.3V_6

C35 EV@1U/6.3V_4
+1.35V_GFX C69 EV@10U/6.3V_6 C22 EV@1U/6.3V_4 C23 EV@0.1U/10V_4 C58 EV@10U/6.3V_6
C419 EV@1U/6.3V_4 C415 EV@0.1U/10V_4
C25 EV@1U/6.3V_4 C411 EV@1U/6.3V_4 C36 EV@1U/6.3V_4 C48 EV@0.1U/10V_4
C416 EV@1U/6.3V_4 C402 EV@1U/6.3V_4 C398 EV@1U/6.3V_4 C414 EV@0.1U/10V_4 Quanta Computer Inc.
C37 EV@1U/6.3V_4 C417 EV@1U/6.3V_4 C5 EV@1U/6.3V_4 C27 EV@0.1U/10V_4 C3 EV@0.1U/10V_4
C50 EV@1U/6.3V_4 C8 EV@1U/6.3V_4 C11 EV@1U/6.3V_4 C396 EV@0.1U/10V_4 C6 EV@0.1U/10V_4
PROJECT : ZQ0
3A
DGPU Memory (DDR3)
5 4 3 2 1
5 4 3 2 1
DP TO VGA
1A-1 2013/10/15 Change VGA ITE soltion to NXP.
1A-5 2013/10/18 Change VGA NXP soltion to ITE. 23
+3V
L10 80ohm@100MHz
C227 C228 20mils

C195
1u/6.3V_4 0.1u/10V_4 0.1u/10V_4
D D
L29 80ohm@100MHz
1C1-2 link L29 to +3V directly

C193
20mils FingerPrint Conn
(meet IVDDO vs OVDD sequence) RX_DVDD18
10u/6.3V_6
C182
15mils C224 0.1u/10V_4 C189
0.1u/10V_4 0.1u/10V_4
ISPSCL +5V
IVDDO
ISPSDA C474
CN6
*0.1u/10V_4
1 7
2 8
13
48
35
36
38
39
12
14
44
46
U5 3
1
2
[9] USBP2- 4
IVDDO
IVDDO
OVDD
OVDD
IVDD
IVDD
IVDD
IVDD
DDCSCL
IVDD33
IVDD33
DDCSDA
40 [9] USBP2+ 5
[2] CRT_HPD CRT_HPD 20mils
HPD +5VMCU +5V 6
45 80ohm@100MHz L9 *FingerPrint/B
C218 0.1u/10V_4 CRT_TXP0_C 26 MCUVDDH
[2] CRT_TXP0 27 RX0P
C216 0.1u/10V_4 CRT_TXN0_C 1A-7 2013/10/22 Change CN4 to 6pin.
[2] CRT_TXN0 RX0N
C212 0.1u/10V_4 CRT_TXP1_C 29 47 1B-6 2013/12/18 Change CN5 USB port to port2.
[2] CRT_TXP1 30 RX1P MCURSTN TP47
C210 0.1u/10V_4 CRT_TXN1_C
[2] CRT_TXN1 RX1N
28 URDBG
URDBG TP52
+3V
15 ISPSCL R151 22/J_4 DDCCLK
ISPSCL DDCCLK [22]
16 ISPSDA R156 22/J_4 DDCDAT
ISPSDA DDCDAT [22]
*1M_4 R187 CRT_AUXP CRT_AUXP C225 0.1u/10V_4 CRT_AUXP_C 20
[2] CRT_AUXP 19 RXAUXP 23
CRT_AUXN C229 0.1u/10V_4 CRT_AUXN_C R178 22/J_4 DDCCLK
[2] CRT_AUXN RXAUXN VGADDCCLK 21
*1M_4 R189 CRT_AUXN R179 22/J_4 DDCDAT
VGADDCSDA
18 3 VSYNC
DCAUXP VSYNC VSYNC [22]
17 4 HSYNC 20mils
DCAUXN HSYNC HSYNC [22]
DAC_VDDC 80ohm@100MHz L12 IVDDO_18
C C
C208 C215
IVDDO 30mils C214
20mils 10mils 25 10 0.1u/10V_4 0.1u/10V_4
L11 80ohm@100MHz IVDDO_18 31 AVCC VDDC 0.1u/10V_4
0.1u/10V_4 C217 AVCC
Power Button/Conn
C185
10u/6.3V_6 C191
10mils
22
PVCC
IT6513FN
1u/6.3V_4 0.1u/10V_4 C223 11 CRT_RED
IORP CRT_RED [22]
9 CRT_GRE
IOGP CRT_GRE [22]
10mils
L8 80ohm@100MHz RX_DVDD18 24
0.1u/10V_4 C220 DVDD18 8 CRT_BLU
IOBP CRT_BLU [22]
C179
15mils 41 +3VPCU
NC/VGADETECT TP46
4.7u/6.3V_6
10mils 5 VGA_RST R158 100/F_4
32 RSET C467
0.1u/10V_4 C205 ASPVCC
7 DAC_VDDC *0.1u/10V_4
VDDA C199 C209 CN4
20mils 1 5
6 VGA_COMP 0.1u/10V_4 0.1u/10V_4
COMP [22,30] LID# 2 6
2.2K_4 R138 43
+5VMCU PCSDA [13,30] NBSW ON# 3
2.2K_4 R139 42
PCSCL 34 27M_CRT_IN 4
XTALIN 33 27M_CRT_OUT Y1 PW R_4P
XTALOUT 1 3
PWDNB
1B-1 20131108 Change +5V to +5VMCU. 2 4
GND
C206 *27MHZ C198
IT6513N-QFN-48 *10p/50V_4 *10p/50V_4
37
49
1A-1 2013/10/15 change to 6pin.
+5VMCU R137 10K_4 1B-2 2013/12/3 change to 4pin.

1B-3 2013/12/10 change CN6 footprint.
1B-1 20131108 Change TP to +5VMCU and 10kohm.
B B
+3V_SUS
Green CLK Gen
TPM R685 *TPMN@0_4 +3V_S5
+3V R680 *TPMN@0_4
1C-4 R223 TPM@0_4 +3V_TPM_VDD R684 TPMI@0_4 +3V_TPM_VDD

2014/01/15 TPM CO-lay nuvoton
1
C251 C682 C241

TPM@0.1u/10V_4
2
*TPMN@10u/6.3V_4 TPM@0.1u/10V_4
2
1
C252 C250
TPM@10u/6.3V_4 TPM@0.1u/10V_4 1B-4 2013/12/13 remove Green GLK U9
2
24
19
U10
VDD
VDD
VSB
1A-9 2013/10/23 add R5335 Isolate SLB9660 NC.

28
26 LPCPD#
[8,24,30] LPC_LAD0 LAD0
TPMI@-->for SLB9655
23 9 R214 TPMI@0_4PLTRST#_TPM TPMN@-->for Nuvoton
[8,24,30] LPC_LAD1 20 LAD1 TESTB1/BADD
[8,24,30] LPC_LAD2 17 LAD2 8
[8,24,30] LPC_LAD3 LAD3 TEST1
R682 *TPMN@10K_4 SLB 9655 NPCT620
R685 Un-stuff stuff
TPM 14
PCLK_TPM 21 SLB 9655 TT 1.2 XTALO 13
[9] PCLK_TPM LCLK XTALI
[8,24,30] LPC_LFRAME# LPCFRAME# 22 C682 Un-stuff stuff
R212 *short_4 PLTRST#_TPM16 LFRAME# 2
[7,13,16,24,26,27,30] PLTRST# LRESET# GPIO2 6 R216 *20K/F_4 +3V_TPM_VDD
27 GPIO
[10,30] IRQ_SERIRQ
R224 *short_4 R683 Un-stuff stuff
SERIRQ 1
R683 *TPMN@0_4 15 NC 3
[7,30] CLKRUN# CLKRUN# NC
1A-11 12 R213 stuff Un-stuff
GND
GND
GND
GND
2013/10/28 U5013 Pin8,15,28 left NC. 7 NC 10 +3V_TPM_VDD

A A
PP NC
TPM@SLB9655TT_TSSOP28 R682 Un-stuff stuff
4
11
18
25
+3V_TPM_VDD 2 1
1A-11 R215 *TPM@4.7K R214 stuff Un-stuff
2013/10/28 Change U5013.7 from +3V_S5 to +3V.
2
R213 R684 stuff Un-stuff

TPMN@4.7K
1

PROJECT : ZQ0
3A
Mini DP/HD3SS2521
5 4 3 2 1
1 2 3 4 5 6 7 8
Q10 C168 *0.1u/10V_4

CRT +5V 3
IN OUT
1
2
GND CRTVDD5 CN3
16
AP2331SA-7
6
L32 BLM15BB470SN1D CRT_R1 1 11 CRT_11 TP48
+5V [21] CRT_RED
7
1C-1 2014/01/10 Remove U29 and add U40 and U41. L31 BLM15BB470SN1D CRT_G1 2 12 DDCDAT
[21] CRT_GRE DDCDAT [21]
8
L30 BLM15BB470SN1D CRT_B1 3 13 CRTHSYNC
[21] CRT_BLU
C677 9
4 14 CRTVSYNC
U40 0.1u/10V_4 C471 C468 C464 C463 C470 C473 10
R567 R561 R557 5 15 DDCCLK DDCCLK [21]
1 5 75/F_4 75/F_4 75/F_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4
OE# VCC
A A
CRT CONN
17
HSYNC 2 4 CRTHSYNC
[21] HSYNC A Y
3 DDCDAT 2.2K_4 R154 CRTVDD5

GND +5V DDCCLK 2.2K_4 R142
M74VHC1GT125DF2G U26
CRTHSYNC 1 10 CRTHSYNC C160 *0.22u/6.3V_4
C668 CRTVDD5 2 1 10 9 CRTVDD5
3 2 9 C173 *220p/50V_4
U41 0.1u/10V_4 CRTVSYNC 4 GND_3/8 7 CRTVSYNC
DDCCLK 5 4 7 6 DDCCLK C161 0.1u/10V_4 CRTVDD5
Power trace tracking
1 5 5 6
OE# VCC [2,5,7,8,9,10,11,13,14,15,16,17,18,21,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38] +3V
*RClamp0524P C458 10p/50V_4 CRTVSYNC [21,23,25,28,29,32,36] +5V
[7,8,10,11,13,21,25,27,28,29,30,31,32,36,37,38] +3VPCU
VSYNC 2 4 CRTVSYNC U4 C462 10p/50V_4 CRTHSYNC
[21] VSYNC A Y [31,32,33,34,35,36,37,38] VIN
CRT_R1 1 10 CRT_R1
CRT_G1 2 1 10 9 CRT_G1 C457 *10p/50V_4 DDCCLK
3 3 2 9
GND DDCDAT 4 GND_3/8 7 DDCDAT C460 *10p/50V_4 DDCDAT
CRT_B1 5 4 7 6 CRT_B1
M74VHC1GT125DF2G 5 6
*RClamp0524P
LCD CONNECTOR VIN

+3V
TP_PWR
CCD_PWR
LCD Power
+3V
C410 C409
C21 C24 Touch Panel interrupt R1 C7 C9
*10K_4 0.1u/10V_4_X7R
2
4.7u/25V_8 1000p/50V_4 0.1u/10V_4_X7R 1000p/50V_4 C10 U1
1000p/50V_4
B 3 1 TP_INT 1u/6.3V_4 6 1 LCDVCC B
[10] TP_INT_PCH IN OUT
Q1 4 2 C14 C16 C13 C15 C18
*2N7002K IN GND
+3V R29 EDP_VDD_EN_R
*short_4 3 5 *0.1u/10V_4 *2.2u/10V_8 0.1u/10V_4 0.01u/25V_4 22u/6.3V_8
[2] EDP_VDD_EN ON/OFF GND
R2 TSI@0_4
VIN
1A-5 2013/10/18 add 0ohm short TP interrap pin. G5243AT11U
R402 100K_4 EDP_AUX_C R14 *100K_4 CN2
R403 *100K_4 EDP_AUX#_C R15 100K_4 MAX 1.5A R26 *Short_6 R30
G_5
TP_RST# R6 *TSI@10K_4 R25 *Short_6 V_BLIGHT
40
39 100K_4
38
C19 C20 37
*1u/6.3V_4 *1u/6.3V_4 36
LCDVCC R24 *SHORT_8 35
1A-5 2013/10/17 Change Touch screen R18 *Short_6 CCD_PWR 34
power rail from 5V to 3V. +3V 33
MP-1 20140328 Change Touch screen 32
power rail from 3V to 5V. R13 0_6 TP_PWR 31 G_4
MP-1 20140408 reserve 3V TP_PWR.
+5V
+3V R699 *0_4 30 Touch screen level shift I2C(reserve)
29
BRIGHT 28 +3V
[2] PCH_BRIGHT 27
BL_ON
EDP_HPD 26
[2] EDP_HPD 25
EDP_AUX C407 .1U/16V_4 EDP_AUX_C 24 R337 *TSI@0_4 R4 R5
[2] EDP_AUXP 23
EDP_AUX# C408 .1U/16V_4 EDP_AUX#_C *TSI@10K_4 *TSI@10K_4
[2] EDP_AUXN 22
21 Q2
[2] EDP_TXP1 C406 .1U/16V_4 EDP_TX1_C TPD->100kHz,TS=400Khz
C405 .1U/16V_4 EDP_TX1#_C 20
eDP [2] EDP_TXN1 19
Intel design guide suggestion
1 6 I2C1_SDA_GPIO6_CONN MCP PIN 10u.
EDP_TX0 C404 .1U/16V_4 EDP_TX0_C 18
[2] EDP_TXP0 17 Per inch 3u TS=3x5inch
EDP_TX0# C399 .1U/16V_4 EDP_TX0#_C 2 400kHz10~100u =2.4~0.4k.
[2] EDP_TXN0 16 +3V
15 [10] I2C1_SDA_GPIO6 100Khz 10~100u=9k~1k.
[9] USBP6+ R399 *short_4 USBP6+_R USBP6+_R [10] I2C1_SCL_GPIO7
R398 *short_4 USBP6-_R USBP6-_R 14 4 3 I2C1_SCL_GPIO7_CONN
C [9] USBP6- CCD-USB 13 C
USBP5+_R 12 5
USBP5-_R 11
Touch Panel 10 G_1
I2C1_SCL_GPIO7_CONN 9 *TSI@2N7002DW
I2C1_SDA_GPIO6_CONN 8 R347 *TSI@0_4
TS_EN R3 *short_4 7
[30] TS_EN 6
TP_INT
TP_RST# 5
R397 *short_4 USBP5+_R 4
[9] USBP5+ 3
R396 *short_4 USBP5-_R
[9] USBP5- [10] GPIO8 2
1A-13 2013/10/30 CN5002.6 add USB

1
G_0 50398-04071-001
Backlight Control +3VPCU
touch screen on/off pin to EC.
R19
*100K_4
TS_EN R698 *0_4 TP_INT +3V LID# LID# [21,30]

LID591#,EC intrnal PU
1C1-2 2014/03/11 Add R698 for TS_EN short TP_INT,
for issue debug. D1
R16 R17 1N4148WS
10K_4 10K_4
BL_ON
BL#
R20 *short_4 PCH_BLON_R
[2] PCH_BLON
3
[30] PCH_BLON_EC R22 0_4 R21
2
EC_FPBACK# [30]
100K_4
Q4
1B-1 2013/11/28 Add BLON pin from PCH to lison. Q3 DTC144EUA
1
2N7002DW
D D
1
1B-3 2013/12/10 change Q3.3 from +3V to +3VPCU.

PROJECT : ZQ0
1A
CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
HDMI
From PCH
C527 0.1u/10V_4 INT_HDMITX2N_C
[2] INT_HDMITX2N
C528 0.1u/10V_4 INT_HDMITX2P_C
[2] INT_HDMITX2P
[2]
[2]
INT_HDMITX1N
INT_HDMITX1P
C526 0.1u/10V_4 INT_HDMITX1P_C HDMI connector
[2] INT_HDMITX0N
C533 0.1u/10V_4 INT_HDMITX0P_C
[2] INT_HDMITX0P
C524 0.1u/10V_4 INT_HDMICLK+_C
D [2] INT_HDMICLK+ D
C523 0.1u/10V_4 INT_HDMICLK-_C
[2] INT_HDMICLK-
CN10
20
1
INT_HDMITX0P_C 1 SHELL1
R639 R641 R255 R249 R241 R239 R248 R245 2 D2+
INT_HDMITX0N_C 3 D2 Shield
470_4 470_4 470_4 470_4 470_4 470_4 470_4 470_4 INT_HDMITX1P_C 4 D2-
5 D1+
2
INT_HDMITX1N_C 6 D1 Shield
INT_HDMITX2P_C 7 D1-
INT_HDMICLK+_CONN R234 *short_4 INT_HDMICLK+_C 8 D0+
R235 *680_4 INT_HDMICLK-_CONN R230 *short_4 INT_HDMICLK-_C INT_HDMITX2N_C 9 D0 Shield 23
1 2 INT_HDMICLK+_CONN INT_HDMICLK+_C 10 D0- GND
1B-1 20131108 Change +5V to +3V for DG. 11 CK+ 22
3
R231 *680_4 INT_HDMICLK-_C 12 CK Shield GND
1 2 INT_HDMICLK-_CONN 13 CK-
Q31 14 CE Remote
2 HDMI_DDCCLK_MB 15 NC
+5V DDC CLK
HDMI_DDCDATA_MB 16
+5V Q29 17 DDC DATA
2N7002E 3 1 HDMI_5V 18 GND
R226 IN OUT 2 19 +5V
1
*100K/F_4 GND HDMI_MB_HPD R218 *short_4HP_DET_CN HP DET 21
AP2331SA-7 C247 D5 SHELL2
1
*220p/50V_4 *AZ5125-01J HDMI connector
R221
20K_4
2
C C
HDMI-detect
+3V +3V
R63
2
1M_4
[2] INT_HDMI_HPD 1 3 HDMI_MB_HPD
Q20
2N7002K
I2C
+3V +5V
2
D2
RB501V-40
+3V
1
B B
R165 R184
EMI
2
2.2K_4 2.2K_4
Q19
1 3 HDMI_DDCCLK_MB
INT_HDMITX2P_C
2N7002K
R246 *120/F_4
+3V INT_HDMITX2N_C
+5V
INT_HDMITX1P_C
2
R240 *120/F_4
D3
RB501V-40 INT_HDMITX1N_C
+3V
INT_HDMITX0P_C
From PCH
1
R253 *120/F_4
R166 R186
[2] HDMI_DDCCLK_SW
2
2.2K_4 2.2K_4 INT_HDMITX0N_C

Q18
1 3 HDMI_DDCDATA_MB INT_HDMICLK+_C
[2] HDMI_DDCDATA_SW
2N7002K R640 *120/F_4
INT_HDMICLK-_C
A A

[2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,24,25,26,27,28,29,30,32,33,34,35,36,37,38]
[21,22,25,28,29,32,36]
+3V
+5V
PROJECT : ZQ0
1A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
Mini Card 1 (MPC)

26
D D
+WL_VDD +1.5V_WLAN
CN11
R645 *short_4 BT_PWRON_R 51 52
[30] BT_POWERON Reserved +3.3V
TP138 CL_RST1#_WLAN 49 50
PLTRST# R646 *0_4 CL_DATA1_WLAN 47 Reserved GND 48
[7,13,16,21,24,26,27,30] PLTRST# Reserved +1.5V
R647 *0_4 CL_CLK1_WLAN 45 46 2013/10/17 remove WLAN_OFF
[9] CLK_PCI_LPC Reserved LED_W PAN# no IOAC support.
43 44 WLAN# 1A-4
41 GND LED_W LAN# 42 WWAN#
+WL_VDD +3.3Vaux LED_W W AN# TP137
39 40
37 +3.3Vaux GND 38
GND USB_D+ USBP4+ [9]
35 36
GND USB_D- USBP4- [9]
33 34 1A-12 2013/10/29 Change CN5008 to S0 of SMbus
[9] PCIE_TX4+_WLAN PETp0 GND
31 32 WLAN_CLK_SDATA R635 *0_4 CLK_SDATA [8,13,14,15]
[9] PCIE_TX4-_WLAN PETn0 SMB_DATA
29 30 WLAN_CLK_SCLK R636 *0_4 CLK_SCLK [8,13,14,15]
27 GND SMB_CLK 28
25 GND +1.5V 26 2013/10/17 remove R5224\R5225\R5226
[9] PCIE_RX4+_WLAN PERp0 GND no IOAC support.
23 24 1A-4
[9] PCIE_RX4-_WLAN PERn0 +3.3Vaux
21 22 R637 *short_4 PLTRST#
GND PERST# PLTRST# [7,13,16,21,24,26,27,30]
19 20 RF_EN
UIM_C4 W _DISABLE# RF_EN [30]
17 18
UIM_C8 GND
15 16 A_LFRAME#_R R630 *0_4
Debug
C C
GND UIM_VPP LPC_LFRAME# [8,21,30]
R648 *short_4 CLK_PCIE_WLAN_C 13 14 A_LAD3_R R631 *0_4
[9] CLK_PCIE_WLANP REFCLK+ UIM_RESET LPC_LAD3 [8,21,30]
R649 *short_4 CLK_PCIE_WLAN#_C 11 12 A_LAD2_R R632 *0_4
[9] CLK_PCIE_WLANN REFCLK- UIM_CLK LPC_LAD2 [8,21,30]
9 10 A_LAD1_R R633 *0_4
GND UIM_DATA LPC_LAD1 [8,21,30]
PCIE_CLKREQ_WLAN#_R 7 8 A_LAD0_R R634 *0_4
CLKREQ# UIM_PW R LPC_LAD0 [8,21,30]
5 6
3 Reserved +1.5V 4
GND
GND
R643 4.7K_4 PCIE_WAKE#_R 1 Reserved GND 2
+WL_VDD W AKE# +3.3V
MINI-CARD1
53
54
1C-3 2014/01/14 Change Cn11 Footprint.
+1.5V
+WL_VDD
500mA for +1.5V
+3V R651 *SHORT_8 +WL_VDD +1.5V_WLAN R629 *0_6
C518
B B
C532 C516 C514 C520 C517 C519
1A-4 2013/10/17 remove Q5020 no IOAC support. 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *1000p/50V_4 *0.1u/10V_4 *10u/6.3V_8
+WL_VDD
1C1-2 2014/03/08 Remove PCIE wake and

stuff R642, un-stuff Q44.
R650
S0
2
4.7K_4
3 1 PCIE_CLKREQ_WLAN#_R
[9] PCIE_CLKREQ_WLAN#
Q44
*2N7002K
S5 R642 *short_4
A A
1A-4 2013/10/17 remove Q5019 no IOAC support.

PROJECT : ZQ0
1A
Mini-Card/WL/3G/SIM
5 4 3 2 1
5 4 3 2 1
2.5" SATA HDD (HDD) SATA ODD Connector
CN12
GND23
23
CN7
27
1 14
GND1 2 SATA_TXP0_C C353 0.01u/16V_4 GND14
RXP SATA_TXP0 [8]
3 SATA_TXN0_C C345 0.01u/16V_4 SATA_TXN0 [8] 1
RXN 4 GND1 2 SATA_TXP1_C C492 0.01u/16V_4
GND2 RXP SATA_TXP1 [8]
5 SATA_RXN0_C C343 0.01u/16V_4 3 SATA_TXN1_C C490 0.01u/16V_4 SATA_TXN1 [8]
D TXN SATA_RXN0 [8] RXN D
6 SATA_RXP0_C C340 0.01u/16V_4 4
TXP SATA_RXP0 [8] GND2
7 5 SATA_RXN1_C C484 0.01u/16V_4
GND3 TXN SATA_RXN1 [8]
6 SATA_RXP1_C C482 0.01u/16V_4
TXP SATA_RXP1 [8]
7
GND3 ODD_PRSNT# [8]
8
3.3V 9 DEVSLP0_R R265 *0_4 R160 10K_4 +5V_ODD
3.3V DEVSLP0 [10] +3V
10 8 C200 *15p/50V_4
3.3V 11 DP 9
GND 12 +5V 10
GND 13 1B-4 2013/10/23 remove C5056 is duplicater. +5V +5V 11 C188 C466 C187 C186 C465 C459
+
GND 14 RSVD 12
5V 15 +5V_HDD 60mil R653 *SHORT_8 GND 13 0.01u/25V_4 0.01u/25V_4 *0.1u/16V_4 *0.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528
5V 16 GND
5V 17 C531 C534 C535 C529 C537 C539 15
GND 18 + GND15
RSVD 19 0.01u/25V_4 0.01u/25V_4 *0.1u/16V_4 *0.1u/16V_4 10u/6.3V_6 100u/6.3V_3528 C185Q2-11311-L
GND EC_ODD_EJ [30]
20
12V 21
12V 22 1A-8 2013/10/23 remove R5017 5V is duplicater.
12V R135 10K_4 +3V
24
GND24
HDD CONN 1A-8 2013/10/23 remove C5056 is duplicater.
C FFC Type SATA HDD CON ODD Power (SATA) +3VPCU Q17 C
+15V +5V AO6402A +5V_ODD
+5V
1
1C-2 2014/01/13 change CN14 sata net name 6
and add C678~C681. R200 5 4 R159 *0_8
CN14 100K 2
1 1 R172
2 SATA_TXP0_CN C679 *0.01u/16V_4 SATA_TXP0 22_8
2
3 SATA_TXN0_CN C681 *0.01u/16V_4 SATA_TXN0 R180
3
4 ODD_EN_Q 2 1
MOD_EN_5V
5 SATA_RXN0_CN C680 *0.01u/16V_4 SATA_RXN0 100K
3
6 SATA_RXP0_CN C678 *0.01u/16V_4 SATA_RXP0
7 DEVSLP0_R
8 [30] ODD_POWER R199 *short_4 ODD_EN
11 9 +5V_HDD ODD_EN_Q 2
1
12 10 [10] PCH_ODD_EN R192 *0_4
C234 Q22
*SATA_CONN R188 0.1u/25V_6 DMN601K-7
2
*100K
1
2
2N7002DW
Q23
1
1B-3 2013/12/10 change Cn20 Pin define.
1A-9 2013/10/17 Change power LED from +3VPCU to +3V_S5.

1A-10 2013/10/25 change LED from 3pin to 4pin.
B for acer reqeust, B
POWER LED 1A-11 2013/10/28 change LED from 4pin to 3pin.

and power LED to +3VPCU.
1B-2 2013/12/03 change LED from 3pin to 4pin.
1C1-1 2014/02/06 change Blue LED power rail to +5VPCU.
1C1-1 2014/02/11 add ESD on led.
1C1-1 2014/02/13 Change LED to lite-on and reisstor
base on test result.
R380 *1M_4 +5VPCU
R376 *1M_4 +3VPCU
D23 1 2 *5.5V/25V/410P_4 +5VPCU +3VPCU
Power LED Blue
R379 2K/F_4 3 2
[30] PWRLED#
R375 820/F_4 4 1
[30] SUSLED#
LED1 POWER LED
1 Amber
2
D24 *5.5V/25V/410P_4
R383 *1M_4 +5VPCU

R377 *1M_4 +3VPCU
+5VPCU +3VPCU
Battery D25 1 2 *5.5V/25V/410P_4
Blue
R384 2K/F_4 3 2
[30] BATLED0#
A R688 820/F_4 4 1 A
[30] BATLED1#
LED2 POWER LED
Amber
1 2
D26 *5.5V/25V/410P_4

PROJECT : ZQ0
1A
SATA HDD/LED/SW
5 4 3 2 1
5 4 3 2 1
LAN
LAN_XTALI C230 10p/50V_4
1
2
Y2
25MHZ +-30PPM
VDD10
3
4
LAN_XTAL2
C232 *10P/50V/COG_4 C231 10p/50V_4
R197 2.49K/F_4 RSET
10 mils TP54
TP55
TP56 +3V_S5 2013/10/23 add 10k
1A-9 for vensor suggestion.
D LANVCC D
C233 *10P/50V/COG_4
R208 10K/J_4
2
32
31
30
29
28
27
26
25
U7
3 1 PCIE_REQ_LAN#_R
AVDD33
AVDD10
CKXTAL2
CKXTAL1
LED0
RSET
LED1/GPO
LED2(LED1)
[9] CLK_PCIE_LAN_REQ#
33 Q28
GND 2N7002K
R209 *0/J_4
MDI_0+ 1 24
MDIP0 REGOUT REGOUT
MDI_0- 2 23 VDDREG/VDD33
3 MDIN0 VDDREG(VDD33) 22 +3V_S5
VDD10 AVDD10(NC) DVDD10(NC) VDD10
MDI_1+ 4 21 PCIE_LAN_WAKE#_R
MDI_1- 5 MDIP1 LANWAKEB 20 ISOLATEB R190 *10K/J_4
2
MDI_2+ 6 MDIN1 ISOLATEB 19
MDI_2- 7 MDIP2(NC) RTL8111GS-CG PERSTB 18 GPP_TX3N_LAN C238 0.1U/10V_4
PLTRST# [7,13,16,21,24,27,30]
MDIN2(NC) HSON PCIE_RX3-_LAN [9]
8 17 GPP_TX3P_LAN C239 0.1U/10V_4 Q25
VDD10 AVDD10 HSOP PCIE_RX3+_LAN [9]
*DTC144EUA
+3V 3 1 PCIE_LAN_WAKE#_R
[7] PCIE_LAN_WAKE#
AVDD33(NC)
REFCLK_N
MDIN3(NC)
MDIP3(NC)
REFCLK_P
CLKREQB
LANVCC R191 *short_4
+3V_S5 LANVCC R201
HSIN
HSIP
1K_4
40 mils (Iout=1A) 40 mils (Iout=1A) ISOLATEB
9
10
11
12
13
14
15
16
R621 2.2_6
1 2
R203
15K_4
MDI_3+
C510 C509 MDI_3-
0.1U/10V_4 10U/6.3V_6 LANVCC
C C
CLK_PCIE_LANN [9]
CLK_PCIE_LANP [9]
PCIE_TX3-_LAN [9]
PCIE_TX3+_LAN [9]
PCIE_REQ_LAN#_R
1C-4 2014/01/15 SWAP PCIE LAN TX single.
[5,7,8,9,10,11,13,21,27,29,30,32,35,37] +3V_S5
18,21,22,23,24,25,27,28,29,30,32,33,34,35,36,37,38] +3V
For RTL8111G(S)
* Place 1uF CAP close to each VDD10 pin-- 22 (reserve)
LANVCC
For RTL8111G(S)
VDDREG/VDD33 RTL8111GS * Place 0.1uF CAP close to each VDD10
40 mils (Iout=1A) REGOUT (SWR mode) support VDD10 pin-- 3, 8, 22, 30
R614 *0_8_S
40 mils (Iout=1A) 40 mils (Iout=1A)
C508 C493 C240 C235 40 mils (Iout=1A) C501 C505 L33 4.7uH
0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 4.7U/6.3V_6
C504 C506 C496 C494 C503 C495 C500 C499

4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 0.1U/10V_4
For RTL8111GS For Surge improvement

* Place 0.1uF CAP close to each C5117\C5111 close Remove For Not Using SWR mode
VDD33 pin-- 11, 32 to pin 11,23. C824,C825 close to Pin23.
B
Tramsformer B
RJ45 Connector
U31
Layout:All termination CN8

MDI_0+ R607 1/F_4 MDI_0+_C 1 TD1+ MX1+ 24 LAN_MX0+
signal should have 30
MDI_0- R611 1/F_4 MDI_0-_C 2 TD1- MX1- 23 LAN_MX0- mil trace
3 TCT1 MCT1 22 LAN_MCT3 R206 75/F_12 LANCT3
U8 LANVCC
MDI_0-_C 1 6MDI_0+_C 4 21 LAN_MCT2 R207 75/F_12 LAN_MX0+ 1
2 IO1 IO4 5 TCT2 MCT2 LAN_MX0- 2
MDI_1+_C 3 GND REF 4MDI_1-_C MDI_1+ R620 1/F_4 MDI_1+_C 5 20 LAN_MX1+ LAN_MX1+ 3
IO2 IO3 TD2+ MX2+ LAN_MX2+ 4
*CM1293A-04SO MDI_1- R622 1/F_4 MDI_1-_C 6 19 LAN_MX1- LAN_MX2- 5
TD2- MX2- LAN_MX1- 6
LAN_MX3+ 7 9 R205 *0/J_6
LAN_MX3- 8 10 R219 *0/J_6
U9 LANVCC MDI_2+ R623 1/F_4 MDI_2+_C 7 18 LAN_MX2+
MDI_2-_C 1 6 MDI_2+_C TD3+ MX3+
2 IO1 IO4 5 MDI_2- R624 1/F_4 MDI_2-_C 8 17 LAN_MX2-
MDI_3+_C 3 GND REF 4 MDI_3-_C TD3- MX3-
IO2 IO3 9 16 LAN_MCT1 R210 75/F_12
*CM1293A-04SO TCT3 MCT3
LAN_RJ45
1A-7 2013/10/22 CN5006 pin9/10
add R5332/r5333 for ESD protect.
10 15 LAN_MCT0 R211 75/F_12
TCT4 MCT4
Reserve for Surge 11 14
MDI_3+ R625 1/F_4 MDI_3+_C LAN_MX3+
Line to GND TVS TD4+ MX4+
A MDI_3- R626 1/F_4 MDI_3-_C 12 13 LAN_MX3- R600 A
TD4- MX4-
0_12
C512
0.01U/50V/X7R_4 D22 D4
*BS4200N-C_1812 *BS4200N-C_1206
NS692417
R594
C497
*1M_8
220p/3KV_1808
PROJECT : ZQ0
1A-7 2013/10/22 Change LGND to GND 1A
LAN (RTL8111GS)
5 4 3 2 1
5 4 3 2 1
1B-6 2013/12/18 Change CN12 USB2.0 port to port0.

USB 3.0 Connector HOLE(OTH) HOLE24
*HG-C276D118P2
HOLE1
*hg-tsbc276d118p2
HOLE7
*hg-tr260x283bc276d189p2
HOLE16
*HG-C276D118P2
HOLE2
*HG-C276D118P2
7 6 7 6 7 6 7 6 7 6
8 5 8 5 8 5 8 5 8 5
USBPWR1 9 4 9 4 9 4 9 4 9 4
USBP0- R313 *short_4 CN13
[9] USBP0-
USBP0+ R317 *short_4 USB3.0 CONN
[9] USBP0+
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1 USBP0-_R RV3 1 2 *EGA_4
1 VBUS
USBP0-_R 2
3 2 D-
USBP0+_R USBP0+_R RV4 1 2 *EGA_4
4 3 D+ HOLE3 HOLE23 HOLE25 HOLE10 HOLE9 HOLE5 HOLE15
R334 *short_4 USB3_RXN0_R 5 4 GND USB3_RXN0_R RV6 1 2 *EGA_4 *HG-C276D118P2 *HG-C276D118P2 *HG-C276D118P2 *hg-tc276bc197d118p2 *H-TC256BC236D161P2 *H-TC256BC236D161P2 *H-TC256BC236D161P2
R326 *short_4 USB3_RXP0_R 6 5 SSRX- 7 6 7 6 7 6 7 6
USB3_RXN0 7 6 SSRX+ USB3_RXP0_R RV5 1 2 *EGA_4 8 5 8 5 8 5 8 5
[9] USB3_RXN0 8 7 GND 9 4 9 4 9 4 9 4
USB3_RXP0 USB3_TXN0_R
[9] USB3_RXP0 8 SSTX-
USB3_TXP0_R 9
D 9 SSTX+ USB3_TXN0_R RV2 1 2 *EGA_4 D
13
12
11
10
1
2
3
1
2
3
1
2
3
1
2
3
1
USB3_TXP0_R RV1 1 2 *EGA_4
13
12
11
10
C335 0.1u/10V_4 USB3_TXN0_C R304 *short_4
[9] USB3_TXN0
C325 0.1u/10V_4 USB3_TXP0_C R298 *short_4 HOLE26 HOLE27 HOLE18 HOLE8 HOLE19 HOLE6 HOLE11 HOLE13 HOLE12 HOLE4
[9] USB3_TXP0
*H-C236D140P2 *H-C236D140P2 *H-ZQ0-1 *h-tsbc276d118p2 *H-ZQ0-1 *SPAD-C236 *SPAD-C236 *SPAD-C236 *SPAD-C236 *SPAD-C236
+5V_S5
1C1-2 2014/03/08 ChangeU12 footprint to sot23
1u/6.3V_4 C308 and add VC2\VC1 change C307 to 3528.
USBPWR1
1
*TVM0G5R5M261R_4 VC1 U12 Close USB3.0
5 1
*22U/6.3V_6 C715 IN OUT C541
2 C540
GND C307
USBON# 4 3 C714 + VC2 HOLE28 HOLE14
[27,30] USBON# EN /OC 470P/50V_4 HOLE20 *H-C236D140P2 HOLE17 *SPAD-C236 HOLE29 HOLE22
*TVM0G5R5M261R_4
G524B2T11U 0.1u/10V_4 *O-ZQ0-1 *h-c102d102n *H-O114X91D114X91N *h-o102x165d102x165n
470P/50V_4
220U/6.3V/ESR35_3528
[9] USB_OC0#
1
1
1
G524B2T11U: Enable: Low Active /2.5A
USB IO D/B Card Reader and Connector

DVDD
C C
DVDD
+5V_S5 C543 0.1u/10V_4
CN18 R342 *short_4 USBP7-_R
[9] USBP7-
[9] USBP7+ R339 *short_4 USBP7+_R R362 *short_4
1 VCC_XD PLTRST# [7,13,16,21,24,26,30] R355
2
3 *1K_4
TP72
4
5
[27,30] USBON# 6 C684 68p/50V_4 RSTZ
SD_CDZ
VCC_XD
[9] USB_OC1# 7 C359
GPIO0
D/B USB Port
DVDD
RSTZ
8 C377 0.1u/10V_4
[9] USBP1- 9
[9] USBP1+ 4.7u/25V_8 1C-5 2014/01/14 add C684\C683\C685 for FAE request.
10 C366
D/B USB Port 11 R356
24
23
22
21
20
19
[9] USBP3- 12 15 0.1u/10V_4
[9] USBP3+ U17 *100K_4
13 16 C685
GPIO0
DVDD
DVDD
RSTZ
SD_CDZ
PMOS
14 C544 0.1u/10V_4 68p/50V_4
50501-01401-001
1 18 VDD18 C3830.1u/10V_4
DVDD DVDD VDD18
USBP7-_R 2 17 SD_D2/MS_D5
USBP7+_R 3 DM SB13 16 SD_D3/MS_D4
4 DP SB12 15 SD_CMD
AVDD
MS_INS 5 AVDD GL834L SD_CMD 14 SD_CLK
TP64 SD_D7/MS_CLK 6 MS_INS QFN24-3.3V SD_CLK 13 SD_D0/MS_D6
1B-6 2013/12/18 Change CN16 USB2.0 port to port1\port2 for DB. TP65 SB0 SB9
C683 1C-3 2014/01/14 change R654 to 0ohm.
MS_BS
2
C542 68p/50V_4
SB1
SB3
SB4
SB5
SB8
R654 *Short_6
25
+3V DVDD
0.1u/16V_4 C346
1
2.2u/6.3V_6 QFN24-3.3V
25
7
8
9
10
11
12
C349
C348 C347
10u/6.3V_6 2.2u/6.3V_6 4.7u/10V_6
B B
TP67 SD_D6/MS_D3 SD_D1/MS_D7 TP83

TP66 SD_D5/MS_D2 MS_BS TP71 DVDD AVDD
TP69 SD_D4/MS_D0 SD_WP/MS_D1 TP70 L34
BLM18PG121SN
+1.05V_S5 +1.35V_GFX +3V

SD/MMC CARD READER (MMC)
C435 C436 C403 C397
C156
EMI *0.1u/10V_4 *1000p/50V_4 *0.1u/10V_4 *1000p/50V_4
*1000p/50V_4
CN1
SD_CLK
SD_WP/MS_D1 R374 90.9_4 SD_WP_R 11 SD_CDZ
SD_CDZ R368 90.9_4 SD_CD#_R 10 WP 16 SD_D2/MS_D5
SD_D2/MS_D5 R371 90.9_4 SD_DATA2_R 9 CD NC 17 SD_D1/MS_D7
SD_D1/MS_D7 R369 90.9_4 SD_DATA1_R 8 DATA2 NC SD_D0/MS_D6
SD_D0/MS_D6 R372 90.9_4 SD_DATA0_R 7 DATA1 SD_D3/MS_D4
6 DATA0
+VCCIN +V1.05M_VCCASW +3V_S5 SD_CLK R367 90.9_4 SD_CLK_R 5 VSS2 C380 C372 C382 C373 C379 C381
4 CLK
VCC_XD VDD
3 *1.6P/50V_4 *1.6P/50V_4 *1.6P/50V_4 *1.6P/50V_4 *1.6P/50V_4 *1.6P/50V_4
SD_CMD R370 90.9_4 SD_CMD_R 2 VSS1
GND
GND
GND
GND
C124 C61 C141 C138 C242 C507 SD_D3/MS_D4 R373 90.9_4 SD_DATA3_R 1 CMD
CD/DATA3
*0.1u/10V_4 *1000p/50V_4 *0.1u/10V_4 *1000p/50V_4 *0.1u/10V_4 *1000p/50V_4 SD-CARD
12
13
14
15
A C378 A
0.1u/16V_4
+1.35V_SUS +3VPCU +WL_VDD
C255 C317 C17 C546 C538 C515 Quanta Computer Inc.

*0.1u/10V_4 *1000p/50V_4 *0.1u/10V_4 *1000p/50V_4 *0.1u/10V_4 *1000p/50V_4
PROJECT : ZQ0
1A
USB Port/ DB
5 4 3 2 1
5 4 3 2 1
Codec(ADO) Grounding circuit(ADO)

HPR
+3VPCU
HPL
LINE1L-VREFO PIN1, PIN4, PIN3, PIN6 are ANALOG R318
LINE1R-VREFO +3V
2N7002DW
MIC2-VREFO 1A-9 2013/10/24 add 100kohm on U5011 pin 26 with C5164. 100K_4
1 6 SLEEVE
CODEC_VREF C364 2.2U/6.3V_4 R272
ADOGND
2
INT_AMIC-VREFO C362 10u/6.3V_4 ADOGND +5VA
3
D D
C357
C363
placed close to codec R350 100K_4 4 3 RING2 *100K_4
C355 5
1u/10V_4
2 10K_4 PCH_AZ_CODEC_RST#
10u/6.3V_4
R301
1u/10V_4 C360 ADOGND Q37
C365 Q36
0.1u/10V_4 10u/6.3V_4 2N7002K C313
*1u/10V_4
1
+AZA_VDD
Place next to pin 26
36
35
34
33
32
31
30
29
28
27
26
25
+1.5VA
U15
ADOGND
CPVEE
HP-OUT-L
LINE1-VREFO-L
MIC2-VREFO
LDO1-CAP
AVDD1
AVSS1
CPVDD
CBN
HP-OUT-R
LINE1-VREFO-R
VREF
C351
C352
10u/6.3V_4 0.1u/10V_4
ADOGND 37
CBP LINE2-L
24 LINE2-L
T2 6/26 MIC change chanel for B-test.
D-Mic 1B-5 2013/12/18 U34 pin6 reserve 0402 resistor for power noise issue.
38 23 LINE2-R
AVSS2 LINE2-R T1
ADOGND +3V
Place next to pin 40 C350 10u/6.3V_4 39 22 LINE1L_R R392 0_4 C391 10u/6.3V_4
LDO2-CAP LINE1-L C390 0.1u/10V_4
Analog 40 21 LINE1R_R
AVDD2 LINE1-R U32
Digital 41 20 6 1
+5V PVDD1 NC VDD GND
L_SPK+ 42 19 C341 10u/6.3V_4 DMIC_DAT_L 5 2
SPK-L+ MIC1-CAP ADOGND DATA CS
C339
0.1u/10V_4
L_SPK- 43
SPK-L-
ALC283 MIC2-R/SLEEVE
18 SLEEVE DMIC_CLK_L 4
CLK GND
3
R_SPK- 44 17 RING2 D-MIC

SPK-R- MIC2-L/RING2
near Codec R_SPK+ 45 16
SPK-R+ MONO-OUT
46 15 CODEC_JDREF R328 20K/F_4
+5V PVDD2 JDREF ADOGND
GPIO0/DMIC-DATA
Low is power down PD# 47 GPIO1/DMIC-CLK 14

C C337 amplifier output PDB Sense B C
48 13 SENSEA R320 39.2K/F_4 HP_JD#
SDATA-OUT
TP63 SPDIFO/GPIO2 Sense A
LDO3-CAP
0.1u/10V_4
SDATA-IN
DVDD-IO
PCBEEP
RESETB
BIT-CLK
1A-7 2013/10/22 del C5079.
Placement near Audio Codec
DVDD
SYNC
DVSS
49
DGND
near Codec Analog
1
10
11
12
Digital
Universal Audio Jack

C326 1.6Vrms D13 RB500V-40
SPKR [8,10]
+3V R296 *Short_6 +AZA_VDD
10u/6.3V_4 PCBEEP C329 1u/10V_4 BEEP_1 R269 47K_4
C332 C328 R268 D12 RB500V-40 MIC2-VREFO

DMIC_DAT_L
DMIC_CLK_L
PCBEEP_EC [30]
C331 4.7K_4
0.1u/10V_4 10u/6.3V_4 100p/50V_4
R349 R283
+3V +1.5V
Place next to pin 1 2.2K_4 2.2K_4

PCH_AZ_CODEC_RST# PCH_AZ_CODEC_RST# [8] 40mils
R266 *short_4
RING2 L24 80ohm@100MHz RING2_R
PCH_AZ_CODEC_SYNC [8]
DVDD_IO R267 *0_4
SLEEVE L22 80ohm@100MHz SLEEVE_R

R394 *short_4 ACZ_SDIN R281 33_4 C310 C330
PCH_AZ_CODEC_SDIN0 [8]
R314 *short_4 40mils
R364 *short_4 0.1u/10V_4 10u/6.3V_4 1C-1 2014/1/06 Change R351\R388 from 47ohm to 65ohm
PCH_AZ_CODEC_BITCLK [8] base on FAE request.
R366 *short_4 CN16
R365 *short_4 C327 *22p/50V_4 SLEEVE_R 4
R363 *short_4 HPR R351 56/F_4 HPR-1 L23 0_6 HPR_SYS 2
C389 *1000p/50V_4 Place next to pin 9 HP_JD# 6
PCH_AZ_CODEC_SDOUT [8]
C354 *1000p/50V_4 5
7
HPL R388 56/F_4 HPL-1 L25 0_6 HPL_SYS 1
B B
RING2_R 3
ADOGND C376
COMBOJACK
2200P/50V_4 C371
R391
R352 C386 *100P/50V_4
*1K_4 C344
*1K_4 2200P/50V_4
*100P/50V_4
LINE1R_R C369 4.7u/6.3V_4 ADOGND ADOGND ADOGND
LINE1L_R C388 4.7u/6.3V_4
+AZA_VDD
Codec PWR 5V(ADO) Mute(ADO) LINE1R-VREFO
LINE1L-VREFO
R354 4.7K_4 SLEEVE_R D18 1 2 *VPORT 0402 151 MV05
R385 4.7K_4
R307 HPR_SYS D19 1 2 *VPORT 0402 151 MV05
1A-1 2013/10/15 swap CAP C8579/C8580 to Vrefo and
*1K_4 RB500V-40 D14 AMP_MUTE# resistor R5214/R5215 to Line in.
AMP_MUTE# [30]
HPL_SYS D20 1 2 *VPORT 0402 151 MV05
PD# RB500V-40 D15 PCH_AZ_CODEC_RST#

DIGITAL ANALOG RING2_R D21 1 2 *VPORT 0402 151 MV05
L21 HCB2012KF220T60/6A/22ohm_8 ESD 2'nd CY00G050B00

+5V +5VA R315
U18 *10K_4 ADOGND
3 4
IN OUT
2
GND C356 C367
1 5 R357 *29.4K/F_4
SHDN SET *10u/6.3V_6 *0.1u/10V_4
*G923-330T1UF
A
C368 C358 R358
*10K/F_4 Codec PWR 3V/1.5V(ADO) A
*0.1u/10V_4 *10u/6.3V_6 ADOGND
Internal Speaker +1.5VA
R343 *0_4
40mil for each signal
DIGITAL ANALOG
ADOGND CN19
R_SPK+ R390 *Short_6 R_SPK+_1
R_SPK- R389 *Short_6 R_SPK-_1 4 6 R335 *short_4
3 5 +1.5V
L_SPK- R387 *Short_6 L_SPK-_1
L_SPK+ L_SPK+_1 2
C730, C787 close U37 pin3 and L65 R386 *Short_6
1
C342
SPK_CONN_4P 1U/6.3V_4 Quanta Computer Inc.

C548 C547 C552 C551
*68p/50V_4 *68p/50V_4 *68p/50V_4 *68p/50V_4
1B-2 2013/12/04 Change PN and footprint. PROJECT : ZQ0
1B-5 2013/12/17 Change CN14 pin define 3B
ALC283/HP/SPK
5 4 3 2 1
5 4 3 2 1
TOUCHPAD BOARD CONN (TPD I2C/PS2 co-lay) 1C-2 2014/01/13 Change TP power rail from +3V_S51C-4 2014/01/15 reserve TP power rail +3V_S5.
K/B (KBC) to +3V_SUS.
32
7 8 MX3 R693 *0_4 R690 0_6 1C1-1 2014/02/17 Add Q47 for PTP
+3V power EN and soft up R694\C713.
5 6 MX2 L35 0_6
+3V_S5 and C712\C686.
3 4 MY17 TPD->100kHz,TS=400Khz R655 0_4 *AO3413
+3V_S5
1 2 MY16 Intel design guide suggestion L36 *0_6 1 3
+3V_SUS
CN15 CP6 *100p/50Vx4 MCP PIN 10u. +3V_SUS R656 *0_4
MY0 1 7 8 MX7 Per inch 3u TS=3x5inch L37 *0_6 C686 Q47 C712 + C545
[30] MY0 +3V
MY1 2 5 6 MX6 R670 R669
400kHz10~100u =2.4~0.4k.
2
[30] MY1 3 3 4
MY2 MX5 0.1u/10V_4 0.22u/25V_6 0.1u/10V_4
[30] MY2
MY3 4 1 2 MX4
100Khz 10~100u=9k~1k. 10K_4 10K_4
[30] MY3 5
MY4 CP5 *100p/50Vx4 R694 *0_4 C713 *1000p/50V_4 50mil CN17
[30] MY4 [30] PTP_PWR_EN#
MY5 6 7 8 MY3 +TPVDD 1
[30] MY5
MY6 7 5 6 MY2 R675 *short_4 TPCLK_R 2
D [30] MY6 8 3 4 [30] TPCLK 3 D
MY7 MY1 R676 *short_4 TPDATA_R
[30] MY7 [30] TPDATA
MY8 9 1 2 MY0 4
[30] MY8 10 5
MY9 CP3 *100p/50Vx4 I2C_TP_SDA_R
[30] MY9
MY10 11 7 8 MY7 R660 *TDI@0_4 I2C_TP_SCL_R 6
[30] MY10
MY11 12 5 6 MY6 TPD_INT# 7 9
[30] MY11 13 3 4 TDI@2N7002DW 8 10
MY12 MY5 C549 C550
[30] MY12 [30] TPD_EN
MY13 14 1 2 MY4 *0.1u/10V_4 *0.1u/10V_4
[30] MY13 15 1 6
MY14 CP1 *100p/50Vx4
[30] MY14 TP CN
MY15 16 7 8 MY11
[30] MY15
MY16 17 5 6 MY10 2 I2C_TP_SDA_R
[30] MY16 [10] I2C0_SDA_GPIO4
MY17 18 3 4 MY9 I2C_TP_SCL_R
[30] MY17 [10] I2C0_SCL_GPIO5
MX7 19 1 2 MY8
[30] MX7 20 4 3
MX6 CP2 *100p/50Vx4
[30] MX6
MX5 21 7 8 MY15 1A-5 2013/10/18 Change CN21 Pin8 for
[30] MX5 [2,30] TPD_INT#
MX4 22 5 6 MY14 5 I2C/PS2 TPD idendify.
[30] MX4 23 3 4
MX3 MY13
[30] MX3 Q45
MX2 24 27 1 2 MY12 2013/10/29 Change CN21 power rail to S5
[30] MX2 25 28
MX1 CP4 *100p/50Vx4 R673 *TDI@0_4 change Q42 direction and net name,
[30] MX1
MX0 26 1A-12 reseve PS2 PU to +3V.
[30] MX0 C385 *100p/50V_4 MX1 +3V
C384 *100p/50V_4 MX0
KB_CONN
1A-7 2013/10/22 change CN24 pin define based on spec.

CPU FAN (THM)
1A-8 2013/10/22 change CN24 pin define based on spec based on ZRQ.
+3VPCU
+3V
C RP2 *10K_10P8R +3V C

10 1 MX3
MX4 9 2 R563
MX6 8 3 MX2 R140
MX5 7 4 MX0 +5V 10K_4
MX7 6 5 MX1 *10K_4
2
C196
[30] FANSIG
2.2U_6
U2 30mils CN5
1
2 3 TH_FAN_POWER
VIN VO 5 1
1 GND 6 2
/FON GND 3
2
[8] SMB1ALERT# 7 C174 C180 C469
4 GND 8 FAN_3P
[30] CPUFAN# VSET GND 2.2U_6 .01U_4 *.01U_4
1
G991P11U
FANPWR = 1.6*VSET
1A-1 2013/10/15 change pin define and add pwm IC U17.
1A-42013/10/17 Change U17 to G991P11U and PU U17 pin1.
1A-92013/10/24 Add alert on U17.1 for CPU themal tempture.
KB_BL LED (KBC) 1A-13 2013/10/31CN15 Pin2/3 swap.
B B
+5V
+5V Accelerometer Sensor(reserve only)
C522 *KBL@2.2u/6.3V_6
R638
1
R333 *GS@0_6 +3V

*KBL@10K_4 Q43
*KBL@AO3413
2 +G_SEN_PW
U16
3
C375 C370 1 2
*GS@0.1U/10V_4 14 Vdd_IO NC 3
*GS@10u/6.3V_6
3
2 +5V_KB R628 *KBL@0_4 +5V_KB_R VDD NC

[30] KB_BL_LED
Q42 C521 C513
*KBL@DTC144EU CN9
1
*KBL@4.7u/6.3V_6 *KBL@0.01u/16V_4 10
4 *GS@RB500V-40 D16 ACCEL_INTA_R 11 RESERVED 15
3 6 [10] ACCEL_INTA INT1 RESERVED
9
2 5 TP68 INT2
1 ACCEL_INTA R361 *GS@0_4 7
*KBL@KB_backlight G_MBDATA R359 *GS@0_4 G_MBDATA_R 6 SA0 5
[30] G_MBDATA SDA GND
G_MBCLK R348 *GS@0_4 G_MBCLK_R 4 12
[30] G_MBCLK SCL GND
A 1A-7 2013/10/22 change CN25 pin define for spec. 13 A
C338 +G_SEN_PW 8 GND 16
+G_SEN_PW CS GND
1A-8 2013/10/23 change CN25 footprint. *GS@22P/50V_4
G_MBDATA C374 *GS@33P/50V_4
*GS@LIS3DHTR
G_MBCLK C361 *GS@33P/50V_4

PROJECT : ZQ0
R360 *GS@4.7K_4 G_MBDATA_R Size Document Number Rev
+G_SEN_PW
R344 *GS@4.7K_4 G_MBCLK_R
KB/TP/FAN 3A

5 4 3 2 1
5 4 3 2 1
L14 +A3VPCU +3VPCU

EC(KBC)
33
BLM15AG121SN1D(120,500MA)_4 +3VPCU_ECPLL L13 +3VPCU_EC
C286 BLM15AG121SN1D(120,500MA)_4
0.1u/10V_4 C243 (For PLL Power) S5_ON R250 10K_4
ECAGND 12 mils 0.1u/10V_4 NBSWON# R627 10K_4

+3V_RTC
R257 2.2_6 12 mils HWPG
+3VPCU 1 2 +3VPCU_EC C263
SUSC# [7,13]
SUSB# [7,13]
C244 C266 C301 C245 C292 C536 0.1u/10V_4
+3VPCU_EC and +3V_RTC ODD_POWER [25]
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
minimum trace width 12mils. EC_ODD_EJ [25]
R232 2.2_6 1C1-1 2014/02/17 Add U11.98 GPIO5 1C1-2 2014/03/08 add R696\R697 PU. +3V_GFX
D 1 2 +3V_EC for PTP power en function. D
+3V PTP_PWR_EN# [29]
dGPU_OTP# R696 EV@10K_4
C269 dGPU_OPP# R243 EV@10K_4
CLKRUN# [7,21]
FB_CLAMP_REQ# R697 EV@10K_4
0.1u/10V_4
114
121
127
MAINON R233 100K_4
11
26
50
92
74
84
83
82
19
20
99
98
97
96
93
3
U11
10 110 MBCLK SUSON R220 100K_4
VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VCC
AVCC
EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)
L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)
WUI42/GPH6/ID6(Dn)
WUI41/GPH5/ID5(Dn)
WUI40/GPH4/ID4(Dn)
WUI19/GPH3/ID3(Dn)
CLKRUN#/WUI16/GPH0/ID0(Dn)
[8,21,24] LPC_LAD0 LAD0/GPM0(X) SMCLK0/GPB3(X) MBCLK [31]
9 111 MBDATA
[8,21,24] LPC_LAD1 LAD1/GPM1(X) SMDAT0/GPB4(X) MBDATA [31]
8 115 2ND_MBCLK 2ND_MBCLK [8,19] VRON R644 100K_4
[8,21,24] LPC_LAD2 LAD2/GPM2(X) SMCLK1/GPC1(X)
7 116 2ND_MBDATA 2ND_MBDATA [8,19]
[8,21,24] LPC_LAD3 LAD3/GPM3(X) SMDAT1/GPC2(X)
PLTRST# 22 117 EC_PECR_R R217 43_4 H_PECI [4] PCH_SPI_SI_EC R341 *10K_4
[7,13,16,21,24,26,27] PLTRST# LPCRST#/WUI4/GPD2(Up) PECI/SMCLK2/WUI22/GPF6(Up)
SM BUS
+3VPCU 13 118
[9] CLK_PCI_EC LPCCLK/GPM4(X) SMDAT2/WUI23/GPF7(Up) EC_FPBACK# [22]
6 PCH_SPI_SO_EC R222 *10K_4
[8,21,24] LPC_LFRAME# LFRAME#/GPM5(X) 85
PROCHOT_EC 17 PS2CLK0/TMB0/CEC/GPF0(Up) 86
LPCPD#/WUI6/GPE6(Dn) PS2DAT0/TMB1/GPF1(Up) LID# [21,22]
2
89
PS2CLK2/WUI20/GPF4(Up) TPCLK [29]
D8 TP61 SIO_A20GATE 126 90
GA20/GPB5(X) PS2DAT2/WUI21/GPF5(Up) TPDATA [29]
PS/2
R256 SDMK0340L-7-F 5
100K_4
[10]
[10,21]
SIO_EXT_SMI#
IRQ_SERIRQ
15
23
SERIRQ/GPM6(X)
ECSMI#/GPD4(Up)
SM BUS PU(KBC)
[10] SIO_EXT_SCI# ECSCI#/GPD3(Up) LPC
1
WRST# 14 GPIO
4 WRST#
[10] SIO_RCIN# KBRST#/GPB6(X)
16
[5] HWPG_1.05V_EC# PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT
C282
1u/6.3V_4 24 +3VPCU
PWM0/GPA0(Up) PWRLED# [25]
25
1B-1 2013/11/28 Add BLON pin from PCH to lison.
[22] PCH_BLON_EC
[32,34] SUSON
119
123 CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(Dn) CIR
IT8587 PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
PWM4/GPA4(Up)
28
29
30
SUSLED#
BATLED1#
SUSLED#
BATLED0#
APWORK
[25]
[25]
[25]
[7]
MBCLK
MBDATA
R332
R340
4.7K_4
4.7K_4
31
PWM5/GPA5(Up) +3V_S5
PWM 1A-1 2013/10/15 del fan Pwm
CLK_PCI_EC 80 2ND_MBCLK R331 4.7K_4
C [34,36] MAINON DAC4/DCD0#/GPJ4(X) C
BT_POWERON 104 47 2ND_MBDATA R330 4.7K_4
[24] BT_POWERON DSR0#/GPG6(X) TACH0A/GPD6(Dn) FANSIG [29]
33 48
[5,7] EC_PWROK GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(Dn)
88
[29] KB_BL_LED PS2DAT1/RTS0#/GPF3(Up)
R237 81 120
[29] CPUFAN# DAC5/RIG0#/GPJ5(X) TMRI0/WUI2/GPC4(Dn) DNBSWON# [7]
87 124
[29] TPD_EN PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(Dn) DPWROK [7]
*22_4 TP60 E51_TXD 109
108 TXD/SOUT0/GPB1(Up)
[28] AMP_MUTE# RXD/SIN0/GPB0(Up) H_PROCHOT# [4,31,35]
3
71 125 NBSWON#
[7]
PCH_SLP_SUS# ADC5/DCD1#/WUI29/GPI5(X) PWRSW/GPE4(Up) NBSWON# [13,21]
C276 72 18 dGPU_OPP# Q32
[31] ACIN
73 ADC6/DSR1#/WUI30/GPI6(X) UART port RI1#/WUI0/GPD0(Up) 21
dGPU_OPP# [19]
*10p/50V_4 [31] TEMP_MBAT SB_ACDC [31]
35 ADC7/CTS1#/WUI31/GPI7(X) RI2#/WUI1/GPD1(Up) PROCHOT_EC 2
[22] TS_EN RTS1#/WUI5/GPE5(Dn) WAKE UP
34
[28] PCBEEP_EC PWM7/RIG1#/GPA7(Up)
107 112
[31] D/C# DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) RSMRST# [7]
1A-5 2013/10/18 change U27.87 for Touch pad ID
[29] G_MBDATA 95 R329 2N7002K
for I2C/PS2 solution switch. 94 CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
[29] G_MBCLK
1
CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn) 100K_4
1A-13 2013/10/29 add U27.35 for 105
touch pad on/off. [8] PCH_SPI_CLK_EC FSCK/GPG7
101
[8] SPI_CS0#_UR_ME FSCE#/GPG3 RF_EN [24]
102 EXTERNAL SERIAL FLASH ICMNT
[8] PCH_SPI_SI_EC FMOSI/GPG4 ICMNT [31]
103 66
[8] PCH_SPI_SO_EC FMISO/GPG5 ADC0/GPI0(X) 67 C302 10u/6.3V_6 ECAGND 1A-12 2013/10/29 add U27.68 for
56 ADC1/GPI1(X) 68 touch pad interrupt.
[29] MY16 KSO16/SMOSI/GPC3(Dn) ADC2/GPI2(X) TPD_INT# [2,29]
57 69
[29] MY17 KSO17/SMISO/GPC5(Dn) ADC3/GPI3(X) VRON [35]
32 70 FB_CLAMP_REQ#
PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(X) FB_CLAMP_REQ# [19]
Please do not place any
S5_ON 100 A/D D/A
pull-up resistor [32,33,36] S5_ON
106 SSCE0#/GPG2(X)
on GPG0, GPG2, and GPG6 [8] ME_WR# SSCE1#/GPG0(X) SPI ENABLE
76 dGPU_OTP#
TACH2/GPJ0(X) dGPU_OTP# [19]
(Reserved [29] MY0
36
KSO0/PD0 GPJ1(X)
77 EC_FB_CLAMP
EC_FB_CLAMP [17,19]
hardware strapping). 37 78
[29] MY1 KSO1/PD1 DAC2/TACH0B/GPJ2(X) PCH_PWROK [5,7]
38 79
[29] MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(X) USBON# [27]
39
[29] MY3 KSO3/PD3
B 40 KBMX B
[29] MY4 KSO4/PD4
41
[29] MY5 KSO5/PD5
42
[29] MY6 KSO6/PD6
43
[29] MY7 KSO7/PD7
44
[29] MY8 KSO8/ACK#
45
[29] MY9 KSO9/BUSY
46
[29]
[29]
MY10
MY11
51 KSO10/PE
KSO11/ERR# CK32KE/GPJ7
2
PCH_SUSACK# [7]
HWPG(KBC)
KSI3/SLIN#
KSI1/AFD#
KSI0/STB#
KSI2/INIT#
52 128 +3V
[29] MY12 KSO12/SLCT CK32K/GPJ6 PCH_SUSPWRACK_R [7]
53 R177 *0_4
VCORE
[29] MY13 KSO13

AVSS
54 CLOCK 1A-12 2013/10/29 Swap U27 pin2 and pin128. DDR=1.5V, D1 DNP and D2 POP
KSI4
KSI5
KSI6
KSI7
[29] MY14
VSS
VSS
VSS
VSS
VSS
VSS
55 KSO14 1B-1 2013/11/27 connecto to GND of pin128.

[29] MY15 KSO15 1C1-01 2014/02/19 add SUSPWRACK# to PCH. DDR=1.35V, D1 POP and D2 DNP R228
IT8587E/FX 10K_4
SM BUS ARRANGEMENT TABLE
58
59
60
61
62
63
64
65
27
49
91
113
122
75
12
D1
D10 RB500V-40 HWPG
[36] HWPG_1.5V
[29] MX0 SM Bus 1 Battery D2
C272 D6 *RB500V-40
[29] MX1 [5] HWPG_1.05V
ECAGND
[29] MX2
0.1u/10V_4 SM Bus 2 PCH/VGA D11 RB500V-40
[29] MX3 [34] HWPG_VDDR
[29] MX4
D9 RB500V-40
[29] MX5 [13,33] HWPG_1.05V_S5
[29] MX6 SM Bus 3 G-Snesor
L16 D7 RB500V-40
[29] MX7 [32] SYS_HWPG
BLM15AG121SN1D(120,500MA)_4
SM Bus 4
For test only iRST

SW1
A 3 2 NBSWON# A
4 1
TP57 TP58
5
6
1A-4 2013/10/17 Del U22 becuse no support IOAC
*Power Switch

PROJECT : ZQ0
3A
KBC IT8587
5 4 3 2 1
5 4 3 2 1
1A-7 2013/10/22 change PJ1 Pin define
34
same as ZQN. UMA->0.02/F CS+0208FP04
VA2 PR1 DIS->0.01/F
1A-14 2013/10/30 change Pin define revers. VA1 PQ1 PD1 0.01/F_0612 PQ2
AOL1413 SBR1045SP5-13 VIN AOL1413
PJ1 1 1 1
2 5 3 1 2 2 5
1 3 2 3
2 PR2
3
1
*Short_4
4 PC3 PC4 PR3 24737_ACN PC5 PC6 PR4
4
Power conn 0.1u/50V_6 0.1u/50V_6 220K_4 0.1u/50V_6 2200p/50V_6 33K/F_4
PD2
P4SMAFJ20A 24737_ACP
2
D D
PC1 PC2 PR5
0.1u/50V_6 2200p/50V_6 1 6 *Short_4
20131024 Modify PN for low H.
PD3 PR6 2 5 PR8
D/C# [30]
1N4148WS 220K_4 20140304 Short Pad 10K_4
recommend 200mA at least. 3 4 PR7
*Short_4
PQ3
3
IMD2AT108 20140304 Short Pad
2
24737_ACP
PQ4
2N7002K
24737_ACN
1
PR9
*Short_6 PC7 PC11 PC8
0.1u/50V_6 0.1u/50V_6 0.1u/50V_6
PR10
+3VPCU 63.4K/F_4
1
VIN
PR11 PC12
ACP
ACN
10K/F_4 1u/16V_6
C 24737_ACDET 6 16 24737_REGN C
ACDET REGN
PR14 PR12 PR15 PC13
*10K_4 100K_4 100K_4 0.1u/25V_4 PD4
24737_VCC 20 RB500V-40
VCC PC9 PC14
PR13 PC10 PR16 2200p/50V_6 4.7u/25V_8
20_1206 0.47u/25V_6 17 24737_BST
[30] ACIN BTST
5
*Short_6 PC15
47n/50V_6
[7] ACPRESENT
PQ5
PR17 18 24737_DH 4 MDV1528
HIDRV
6
*0_4 5
[30] SB_ACDC ACOK#
PR18 20140304 Short Pad 19 24707_LX
3
2
1
*Short_4 PHASE PR20
0.01/F_0612
MBDATA 8 PU1 PL1
PQ6 SDA BQ24737RGRR 6.8uH_7X7X3
20140304 Short Pad
2N7002DW PR19 15 24737_DL 1 2 BAT-V
1
*Short_4 LCDRV
PC16 MBCLK 9
SCL
5
0.1u/50V_6
+3VPCU PR21
20140328 EMI add. PR25 *Short_4 14 PR22
PC20 10K_4 PGND *4.7_6
100p/50V_4 24737_BM# 11 4 PR23 PR24
PL12 HCB2012KF-800T50 BM# PQ7 *Short_4 *Short_4
B B
PR26 PC21 MDV1528
*10K_4 24737_CMPOUT 3 PR209 10_6 0.1u/25V_4
3
2
1
MBAT+ PL13 HCB2012KF-800T50 BAT-V CMPOUT 13 24737_SRP 24737_SRP PC18 PC17 PC19
SRP PC22 2200p/50V_6 10U/25V_8 10U/25V_8
No need batt en pin 24737_ILIM 10 PC23 *680p/50V_6 24737_SRN
PJ2 ILIM 0.1u/25V_4
PR37 *Short_4 PR28 PR210 7.5_6 20131009 CHANGE
10 1 316K/F_4 24737_CMPIN 4 12 24737_SRN
2 CMPIN SRN 20140304 Short Pad
50458-00801-V01
3 PR30 100_4 TEMP_MBAT
IOUT
GND
GND
GND
GND
GND
4 TEMP_MBAT [30]
PC24
5 0.1u/25V_4
6 PR33 PR36
12/23 Change to avoid revise BATT
7
21
22
23
24
25
7 +3VPCU
PR35 1M_4 *100K_4
9 8 *100K_4
PC26 PC27
*47p/50V_4 *47p/50V_4 +1.05V
PR34 PC25
100K/F_4 0.01u/25V_4
REGN MAX voltage 6.5V
3
PR40
PR38 PR39
100_4 100_4 PR41
*100K_4 V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
24737_BM# 2 PR42
MBCLK [30]
*1.62K/F_4
*0_4
=0.793V for 3.965A current limit
H_PROCHOT# [4,30,35]
PQ8
3
*2N7002K
A MBDATA [30]
[30] ICMNT Pin10 ILIM=0.793V A
1
Rsr = 0.01ohm
PU2 24737_CMPOUT 2
*IP4223-CZ6
1 6 MBDATA 1A-7 2013/10/22 change PJ2 Pin define PC28 PQ9
CH1 CH4 100p/50V_4 *2N7002K
same as ZQN.
2 5
+3VPCU Quanta Computer Inc.
1
VN VP 1A-10 2013/10/25 modify PJ2 footprint.
TEMP_MBAT 3 4 MBCLK
CH2 CH3 PROJECT : ZQ0
Add ESD diode base on EC FAE suggestion Limit set on 60W/3.16A 2A
Charger(BQ24737RGRR)
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND [33,36]
SYS_SHDN#
SYS_SHDN# [10,36]
35
PR43
*Short_6
20140304 C1-Stage Remove Jumper VL 3V_LDO

20140304 C1-Stage Remove Jumper
+3VPCU
PR44
D D
10K/F_4
[30] SYS_HWPG
VIN VIN
SYS_SHDN#
10u/6.3V_6
0.1u/25V_4
4.7u/6.3V_6
1
*Short_4
+
PR45 PR47
2
PC29 PC30 PC31 *Short_4 *100K/F_4
PC32
PC33
33U/25V_6x4.5 4.7u/25V_8 2200p/50V_6 PC35 PC36
51225_VIN
PR46
PC34
2200p/50V_6 4.7u/25V_8
+5VPCU +5VPCU 20140304 Short Pad
5
+3VPCU
5 Volt +/- 5%
5
TDC : 6.8A PQ11 +3VPCU
PEAK : 9A MDV1528 3.3 Volt +/- 5%
13
12
3
4
OCP : 11A PQ10 4 TDC : 3A
VREG5
VREG3
VIN
MDV1528
Width : 280mil 7 6 SYS_SHDN#
PEAK : 4A
3
2
1
PGOOD EN2
OCP : 5A
1
2
3
51225_EN1 20 10 51225_DH2
EN1 DRVH2 PR48 PC37 Width : 120mil
20140304 C1-Stage Remove Jumper PL2 51225_DH1 16 9 51225_VBST2 PL3
2.2uH_7X7X3 PC38 PR49 DRVH1 VBST2 6.8uH_7X7X3 20140304 C1-Stage Remove Jumper
51225_VBST1 17 8 51225_SW2 1/F_6 0.1u/50V_6
VBST1 PU3 SW2
0.1u/50V_6 1/F_6 51225_SW1 18 TPS51225RUKR 11 51225_DL2
5
C
SW1 DRVL2 C
PR50 51225_DL1 15 4 51225_FB2 PR52
15.4K/F_4 DRVL1 VFB2 PQ13 6.81K/F_4
PQ12 51225_FB1 2 21 MDV1595S PR51
+ PR53 MDV1595S 4 VFB1 GND 4 4.7_6 +
4.7_6 14 22
VO1 GND
VCLK
PC39 PC40 PC41 PC42
GND
GND
GND
GND
CS1
CS2
220u/6.3V_6X4.2 0.1u/50V_6 0.1u/50V_6 220u/6.3V_6X4.2
1
2
3
3
2
1
PC43
PR54 680p/50V_6 PR55
19
26
25
24
23
10K/F_4 PC44 10K/F_4
680p/50V_6
51225_CS1
51225_CS2
51225_VCLK
OCP:5A
107K/F_4
L(ripple current)
52.3K/F_4
PC45 PR56 =(9-3.3)*3.3/(6.8u*0.355M*9)
2 0.1u/50V_6 *Short_6 ~0.865A
PD5 Iocp=5-(0.865/2)=4.57A
OCP:11A 1PS302 3
PR59 Vth=4.57A*14mOhm+1mV=64.94mV
L(ripple current) 1 1/13 Adding +3V_SUS power for touch pad
*Short_6 R(Ilim)=(64.94mV*8)/10uA
=(9-5)*5/(2.2u*0.3M*9) (By acer request)
PR57
PR58
PC47
~51.95K
=3.367A 0.1u/50V_6 PC46
Iocp=11-(3.367/2)=9.316A 0.1u/50V_6
2
B Vth=9.316A*14mOhm+1mV=131.43mV PD6
B
R(Ilim)=(131.43mV*8)/10uA 1PS302 3 VIN +3V_SUS +15V VIN +3VPCU

=105.14K 1
+15V_ALWP PR227 PR225 PR229 PR230

+15V
*1M_6 *22_8 *1M_6 *1M_6
3
PR60
22_8 PC48
0.1u/50V_6
SUSD 2
3
PQ56
2 *AO3404
[30,34] SUSON
1
2 2
+3V_SUS
PR228 PQ54 PQ53
1
PQ57 *1M_6 *2N7002K *2N7002K
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU *DTC144EU PC164
TDC : 0.038A
1
+3VPCU +3VPCU *2.2n/50V_4
PEAK : 0.05A
PR61 PR62 PR63 PR64 PR65 Width : 20mil
5
1M_6 22_8 22_8 1M_6 *1M_6
3
S5D 4 MAIND 4 MAIND 2 S5D 2
A PQ14 PQ15 A
3
MDV1528Q MDV1528Q
PQ16 PQ17
3
2
1
3
2
1
2 AO3404 AO3404
3,36] S5_ON
1
1
2 2 2
+5V_S5 +5V +3V +3V_S5
PR66 PQ19 PQ20 PQ21
1
PQ18 1M_6 2N7002K 2N7002K 2N7002K

DTC144EU PC49
TDC : 3A TDC : 3.77A TDC : 0.69A TDC : 0.6A
1
*2.2n/50V_4
PEAK : 4A PEAK : 5.02A PEAK : 0.92A PEAK : 0.81A PROJECT : ZQ0
Width : 120mil Width : 160mil Width : 40mil Width : 40mil SYSTEM 5V/3V (TPS51225) 2A

5 4 3 2 1
5 4 3 2 1
20140304 C1-Stage Remove Jumper 36

VIN
D D
+5VPCU
+3V
PC52 PC50 PC51

1u/10V_4 2200p/50V_6 4.7u/25V_8
5
PR67
100K/F_4
7
PQ22
MDV1528
V5IN
51211V_DRVH 4
1 9 PR69 PC53 +1.05V_S5
[13,30] HWPG_1.05V_S5 PGOOD DRVH *Short_6 0.1u/50V_6 20140304 C1-Stage Remove Jumper
PR68 *Short_4 51211V_EN 3 10 51211V_VBST PL4
[30,32,36] S5_ON
3
2
1
EN VBST 2.2uH_7X7X3
51211V_TRIP 2 PU4 8 51211V_SW
PR70 93.1K/F_4 TRIP TPS51211DSCR SW
51211V_TST 5 6 51211V_DRVL
PR72 464K/F_4 TST DRVL
5
12 11
C PR71 GND GND PR73 PR74 +1.05V C
GND
GND
GND
GND
*100K/F_4 4.7_6 5.1K/F_4 1.05 Volt +/- 5%
FB
+
4 TDC : 5.7A
13
14
15
16
4
PC54 PC55
51211V_FB 0.1u/50V_6 330u/2.5V_6X4.2 PEAK : 7.2A
PQ23 PC56 OCP : 9A
3
2
1
OCP=9A MDV1595S 680p/50V_6 PR75
L ripple current 10K/F_4 Width : 240mil
=(19-1.05)*1.05/(2.2u*290k*19)
=1.555A
Vtrip=10-(1.555/2)*14mohm
=115.12mV
Rlimit=115.12mV/10uA*8=92.09Kohm VFB=0.7V
+1.05V_S5
+1.05V_MODPHY +1.05V
B B
5
PR223 0_8
1C-1 2014/1/06 add 0ohm pass

1.05V_Modphy to 1.05V.
MAIND 4
VIN +1.05V_S5 [32,36] MAIND
+1.05V_MODPHY +15V PQ24
1C-1 2014/1/06 add PR224 PU to 3VPU. MDV1528Q
3
2
1
+3V PR222 PR217 PR219
3
*1M_4 *22_8 *1M_4
+1.05V
PR224 MODPHY_D 2 1B-2 2013/12/03 change PQ24 to DFN 3x3 size
*100K/F_4
TDC : 2.4A
3
3
3
PR220
*0_4 PR218
PQ41
*AO3404
PEAK : 3.2A
Width : 100mil
1
2 *1M_4 2 2
[10] MODPHY_EN PC151 +1.05V_MODPHY
1
PQ42 PQ55 *2.2n/50V_4

A PQ51 *2N7002K *2N7002K A
1
PC152 PR221 *PDTC143TT

1
*1u/10V_4 *100K_4
+1.05V_MODPHY Quanta Computer Inc.
2
TDC : 1.43A PROJECT : ZQ0

PEAK : 1.9A Size Document Number Rev
Width : 80mil +1.05V_S5 (TPS51211) 2A

5 4 3 2 1
5 4 3 2 1
TDC : 0.75A
PEAK : 1A
Width : 40mil
+DDR_VTT_RUN
37
PC57 PC58
10u/6.3V_6 10u/6.3V_6
D TDC : 0.38A D
PEAK : 0.5A DDR_VTTREF
Width : 20mil
Close to IC
Greater than or equal 40mil
PC59
0.22u/10V_4
+5VPCU
+3V 20140304 C1-Stage Remove Jumper

PC60 PC61
22
21
10u/6.3V_6 1u/10V_4
2
PR76
VIN
100K/F_4
PAD
PAD
VTTGND
VLDOIN
VTTSNS
VTTREF
VTT
+1.35V_SUS
20 12
1.35 Volt +/- 5%
C
[30] HWPG_VDDR PGOOD V5IN PC62 PC63 TDC : 5.6A C
2
PR77 51216_S3 17 14 51216_DRVH
2200p/50V_4 4.7u/25V_8
PEAK : 7.5A
D1
D1
D1
[30,36] MAINON S3 DRVH
*0_4 PR79 PC64 OCP : 10A
2/F_6 0.1u/50V_6 20140304 C1-Stage Remove Jumper
PR78 51216_S5 16 15 51216_VBST Width : 240mil
[30,32] SUSON S5 VBST 1
*Short_4 PU5 G1 PL11
TPS51216RUKR 2.2uH_7X7X3
PR80 51216_MODE 19 13 51216_SW S1/D2 9 51216_SW +1.35V_SUS
200K/F_4 MODE SW
PR81 51216_TRIP 18 11 51216_DRVL 8 G2 11/4 Change to 2.2uH

TRIP DRVL +1.35V_SUS [4,5,14,15,27]
26.1K/F_4
VDDQSNS
PQ52 PR82
26 10 FDMS3660S 4.7_6
S2
S2
S2
PAD PGND
REFIN
GND
PAD
PAD
PAD
REF
7
6
5
PC65 PC66
VREF=1.8V PC67 0.1u/50V_6 330u/2.5V_6X4.2
6
25
24
23
7 PR83 680p/50V_6
51216_REF *Short_6
51216_REFIN
PC68
B 0.1u/10V_4 B
RDSon=2.2mohm
PR84
51216_S3 PR85 51216_S5 10K/F_4 Close to output cap
*0_4
PR86 PC69
30.1K/F_4 0.01u/25V_4 Mode Frequency Discharge mode
51216_S3 200K 400K Tracking Discharge

[4] DDR_VTTT_PG_CTRL
PR216 *Short_4
100K 300K Tracking Discharge

OCP=10A
L ripple current
=(19-1.35)*1.35/(2.2u*400k*19) DDR=1.35V
A =1.425A PR84=10K/F_4 S3 S5 +1.35VSUS REF VTT A
Vtrip=10-(1.425/2)*2.2mohm PR86=30.1K/F_4
=20.432mV
Rlimit=20.432mV/10uA*8=16.35Kohm S0 1 1 ON ON ON Quanta Computer Inc.
S3 (mainon off) 0 1 ON ON OFF PROJECT : ZQ0
2A
S4/S5 0 0 OFF OFF OFF DDR 1.35V(TPS51216)
5 4 3 2 1
5 4 3 2 1
1C-2 20140113 PU6\PU12

change footprint for SMT request. 20140304 C1-Stage Remove Jumper
38
IMON offset
Place NTC close to the VIN
VIN +3V_S5 51624_VREF
VCORE Hot-Spot. +5V_S5 +5V_S5
2200p/50V_4
33U/25V_6x4.5
1
0.1u/50V_6
4.7u/25V_8
4.7u/25V_8
PC71
PC72
PC73
PC74
PC75
PC70 +
100K/F_4_4250NTC
1u/10V_4
2M/F_4
PR87
2
665K/F_4
20/F_6
36.5K/F_4
*90.9K/F_4
*39.2K/F_4
2
PR88
PR89
PR90
PR91
PR92
PR93
PR94
10K/F_4
D D
1_6
PR95
VDD
51624_SKIP# 1 5 PL6
PR96 SKIP# VIN 0.15uH_7X7X4
8 4 1 2
DCR= 0.66mOhm
51624_OCP-I 51624_VRON 51624_PWM1 CS_SW1
PWM VSW +VCCIN
*2M/F_4 CS_BSTR1 6 3
4
BOOT_R PGND
PC154
PR104
1n/50V_4
150K/F_4
1u/6.3V_4
20K/F_4
100K/F_4
150K/F_4
39K/F_4
0.33u/10V_4
2.26K/F_4
PC79
PR97
PR100
PR101
PR102
1000p/50V_6 2.2_6
*Short_4
CS_BST1 7 9
9.09K/F_4
PR98 2.2u/10V_6 +
BOOT PAD
PC77
PR99
PR103
PC78
*330u/2V_7343
100K/F_4
0.1u/10V_4
22u/6.3V_8
22u/6.3V_8
PC80
PC82
PC83
PC81
PR105 PC84 PU6
PC85
2.2/F_6 0.22u/25V_6 CSD97374CQ4M
Add 11 GND VIAs
for thermal pad
PR106
PR107
51624_CSP1
2.94K/F_4
+1.05V
PR108
51624_B-RAMP
51624_SLEWA
51624_F-IMAX
51624_O-USR
Close to VR 51624_THERM PC86
51624_VREF
51624_VDD
0.12u/10V_4
*0.1u/25V_4
PC87
51624_V5A
16.9K/F_4
10K/F_4_3435KNTC
PR109
51624_VBAT
0.1u/10V_4
56_4
PC88
PR110
PR111
PR112
PR113
*56_4
130/F_4
*75/F_4
PR114
51624_CSN1
27
10
11
15
14
28
16
2
9
PC89
*0.1u/25V_4
F-IMAX
B-RAMP
SLEWA
V5A
VDD
VREF
O-USR
THERM
VBAT
30 6 51624_PWM1
[4,30,31] H_PROCHOT# VR_HOT PWM1
VR_SVID_CLK PR115 *Short_451624_CLK 31 5 51624_PWM2 Close to the Close with
[5] VR_SVID_CLK VCLK PWM2
VR side. phase1 inductor
[5] VR_SVID_ALERT# VR_SVID_ALERT# PR116 *Short_451624_ALERT# 32 4 51624_MODE
ALERT MODE
VR_SVID_DATA PR117 *Short_451624_DATA 1 17 51624_CSP1
[5] VR_SVID_DATA VDIO CSP1
C 20140304 Short Pad 3 PU7 18 51624_CSN1 C
PGOOD TPS51624RSM CSN1
+3V +3V +3V 51624_SKIP# 7 19 51624_CSN2
SKIP CSN2 PS3 OSR
51624_VRON 8 20 51624_CSP2
VR_ON CSP2
51624_VFB 24 21
*100K/F_4
*100K/F_4
*100K/F_4
VFB NC
Rmode 100K Ohm ON ON
PR118
PR119
PR120
51624_GFB 23 22 PR121
GFB N/C 150K/F_4
DROOP
COMP
OCP-I
IMON 150K Ohm ON OFF

GND
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
51624_VREF
26
25
12
13
29
33
34
35
36
37
38
39
40
41
42
[5,10] IMVP_PWRGD PR122 *Short_4
For BW 1 Phase
51624_DROOP
51624_OCP-I
51624_IMON
51624_COMP
[30] VRON
PR124 *0_4 PR123
VIN
*Short_4
*Short_4
4.99K/F_4
0_8
[5] VRON_CPU PR29 *Short_4
+VCCIN
+5V_S5
PC90
PR129
PR128
374K/F_4
10K/F_4
*100p/50V_4
*2200p/50V_4
20131014 add
0.1u/50V_6
*4.7u/25V_8
*4.7u/25V_8
PC162
PC160
PC159
PC161
PC163
PR125
PR213
4700p/25V_4
PC91 *1u/10V_4
PR212
PC92
PR130 *330p/50V_4
*10_4
For BW 1 Phase
2
1500p/50V_4
VDD
PR132
PR133
1 5
39K/F_4
51624_SKIP#
4.75K/F_4
[5] VCC_SENSE PL10

SKIP# VIN
PC93
*0.15uH_7X7X4 DCR= 0.66mOhm

51624_PWM2 8 4 CS_SW2 1 2
[12] VSS_SENSE +3V_S5 PWM VSW +VCCIN
CS_BSTR2 6 3
4
BOOT_R PGND
PR31
*2.2_6
*1.82K/F_4
PR134 CS_BST2 7 9
PC94 BOOT PAD
B Parallel *10_4 B
*0_4
*0.1u/10V_4
*22u/6.3V_8
*22u/6.3V_8
*0.01u/50V_4
PC141
PC139
PC140
*1000p/50V_6
PR131 PC158 PU12
PC138
Close to the 0_4 PR214 *0.22u/25V_6 *CSD97374CQ4M
CPU side. *2.2/F_6 Add 11 GND VIAs
for thermal pad
PR127
PR32
51624_CSP2 51624_CSP2
*10K/F_4_3435KNTC *2.67K/F_4
PR126
51624_PWM2 PC155
*0.15u/10V_4
*0.1u/25V_4
PC156
51624_CSN2
*22.6K/F_4
PR27
PR215
51624_CSN2
BW-U 15W (1 phase) BW-U 28W (1 phase) PR135

0_4
PR136
*0_4
PC157
*0.1u/25V_4
Icc TDC PL2：14A Icc TDC PL2：19A

Close to the Close with
Icc Max：32A Icc Max：40A VR side. phase1 inductor
OCP：37A OCP：47A
Fsw：1.2MHz Fsw：800KHz
：
VCORE L/L：：
VCORE L/L：
R_DC_LL：- 2.0mV/A R_DC_LL：- 2.0mV/A
A A
R_AC_LL：- 7.0mV/A R_AC_LL：- 7.0mV/A

PROJECT : ZQ0
2A
+VCCIN(TPS51624)
5 4 3 2 1
1 2 3 4 5
+3VPCU
+1.5V
1.5Volt +/- 5%
+1.5V
39
+3V
PC95 PC96 TDC : 0.6A
10u/6.3V_6 0.1u/25V_6
PU8 TPS54318RTER
PEAK : 0.8A
PR137 16
VIN PH
10 Width : 40mil 20140304 C1-Stage Remove Jumper
A
100K/F_4 A
1 11 PL7
VIN PH 1uH_7X7X3
2 12
VIN PH
14 13 PR138 *Short_6
[30] HWPG_1.5V PW RGD BOOT
MAINON 15 6 PC97
PR139 *Short_4 EN VSNS 0.1u/50V_6 PR140
7 3
R1
100K/F_4
COMP GND PC98 PC99 PC100
8 4 0.1u/10V_4 10u/6.3V_6 10u/6.3V_6
RT/CLK GND 1.5V_VSNS
PAD
PAD
PAD
PAD
PAD
PAD
PC101 9 5
1000p/50V_4 PR141 PR142 SS AGND
8.06K/F_4 121K/F_4 VFB=0.8V R2 PR143
22
21
20
19
18
17
113K/F_4
PC102 PC103 PC104

*100p/50V_4 1500p/50V_4 0.01u/25V_4
V0=0.8*(R1+R2)/R2
B B
VIN
Thermal protection
PD7
DA2J10100L
Need fine tune
for thermal protect point VIN +3V +5V +1.05V +15V
Note placement position
TEMP=85C
PR144 PR145 PR146 PR147 PR148 PR149
1M_6 1M_4 22_8 22_8 22_8 1M_4
1
PQ27
AO3409 MAINON_ON_G MAIND
2 MAIND [32,33]
3
3
3
PR150
2 PQ30 1M_4 2 2 2 2
3
S5_ON 2 [30,34] MAINON DTC144EU PC105

[30,32,33] S5_ON
PQ31 PQ32 PQ28 PQ33 *2200p/50V_4
2N7002K 2N7002K 2N7002K 2N7002K
1
PQ29 PR151 PR152
1
1
DTC144EU *Short_6 *100K/F_6
C C
VL VL
SYS_SHDN# [10,32]
11/4 Change to 1.47K/F PR154 PC106 PR155

PR153 200K/F_4 0.1u/50V_6 200K_6
3
1.58K/F_4
8
PR156
10K/F_4_3435NTC 2.469V 3
+ 1 2
LM393_PIN2 2
- PQ34
3
PU9A 2N7002K
4
AS393MTR-E1 PC107
1
0.1u/50V_6
S5_ON 2
PR157
PQ35 200K/F_4
2N7002K
1
D 5 D
+ 7
6
-
PU9B
AS393MTR-E1

For EC control thermal protection (output 3.3V) PROJECT : ZQ0
2A
+1.5V/Thermal Protect
1 2 3 4 5
5 4 3 2 1
+5V_S5
40
PR158
*EV@SHORT_6
D VIN D
11/4 Change to 6.81K/F 11/4 Change to 12.4K/F
EV@2200p/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
EV@33U/25V_6x4.5
1
PR160
18 1658R-PVCC
PC115
PC108
PC109
PC110
PC111
PR161 EV@6.81K/F_4 PR159 EV@12.4K/F_4 EV@2.2/F_6 +
1
3V_MAIN_PWGD 1658R-VREF 1658R-BOOT1
PC112
2
EV@1U/10V_4
2
PC113 *EV@0.01U/25V_4 PC114
5
PR162 1 2 EV@0.22u/25V_6
EV@100K/F_4 PU10
PR165 1 1658R-BOOT1
PVCC
VIN 1658R-OCS/CB 9 BOOT1 1658R-UGATE1 4 PQ36
PR163 *EV@1/F_4 OCS/CB 2 1658R-UGATE1 EV@AON6414AL
PR184 *EV@0_4 *EV@499K/F_4 UGATE1
[8] VGPU_EN
1
2
3
20 1658R-PHASE1 PL8
3V_MAIN_PWGD PR164 *EV@Short_4 1658R-EN 3 PHASE1 EV@0.24uH_7X7X3
[18,38] 3V_MAIN_PWGD EN 19 1658R-LGATE1 1658R-PHASE1
DCR=1.1m ohm
LGATE1 +VGPU_CORE
DGPU_PSI PR166 *EV@Short_4 1658R-PSI 4
[19] DGPU_PSI
5
PSI PR168
EV@UP1658RQKF EV@2.2/F_6
PWM-VID PR167 *EV@Short_4 1658R-VID 5 15 1658R-BOOT2 +
EV@330u/2V_7343
[19] PWM-VID VID BOOT2 1658R-LGATE1 4
EV@0.1u/10V_4
EV@10u/6.3V_8
14
PC116
PC117
PC118
1658R-UGATE2
1 2 1658R-VREF 8 UGATE2
1
2
3
PC119 EV@1U/10V_4 VREF 16 1658R-PHASE2 PQ37 PC120
PHASE2 EV@AON6752 EV@1000p/50V_6
1658R-REFADJ 6 17 1658R-LGATE2 PR169 EV@10K_4
REFADJ LGATE2 1 2 +3V
C C
7
+3V_S5 +3VPCU R1 PR170 REFIN 13 1658R-PG PR171 *EV@Short_4
PR172 EV@20K/F_4
R2 PGOOD GPU_PWR_GD [17]
1658R-REFIN
*E@0.01U/25V_4
PC121
EV@20K/F_4 12 1658R-COMP
COMP
EV@4700P/25V_4
GND
PR173 PR189 10
FB
1
FBRTN VIN
PC123
EV@10K_4 *EV@10K_4
1
PR175
11
21
DGPU_PSI PR174 EV@2.2/F_6
EV@22P/50V_4
R3
2
1658R-FBRTN
PC122 EV@2K/F_4 1658R-BOOT2
2
PC124
EV@2700P/50V_4
EV@2200p/50V_4
EV@16K/F_6
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
1658R-FB
PR177
PC126
PC127
PC128
PC129
PR176 PC125
5
*EV@0_4 EV@0.22u/25V_6
1658R-UGATE2 4
PR178
EV@18.2K/F_4
R4
1
2
3
Phase Number of Operation *EV@22P/50V_4 PQ38 PL9
1
EV@AON6414AL EV@0.24uH_7X7X3 DCR=1.1m ohm
*EV@Short_4
*EV@Short_4
PC130
PR180
PR181
PR179 1658R-PHASE2 +VGPU_CORE
*EV@5.1K/F_4
2
5
PR182 PR183
EV@0_4
R5 +
EV@330u/2.5V_6X4.2
EV@2.2/F_6 +
EV@330u/2V_7343
3
1658R-LGATE2 4
EV@0.1u/10V_4
EV@10u/6.3V_8
PC131
PC132
PC133
PC134
B B
20131018 no need standby function
1
2
3
2 PQ39 PC135
PQ40 EV@AON6752 EV@1000p/50V_6
*EV@2N7002K
1
Standby PC136
1
Function *EV@1U/10V_4
2
+VGPU_CORE
PR185 N15S-GT
*EV@0_4
+VGPU_CORE
PR186 *EV@Short_4
[16] VGA_VCCSENSE Countinue current:26A
PR187 *EV@Short_4
[16] VGA_VSSSENSE Peak current:60A
OCP:75A
PR188 FSW:300KHz
*EV@0_4
L/L=0mV/A
A
Parallel A

PROJECT : ZQ0
2A
+VGPU_CORE(UP1642PQAG)
5 4 3 2 1
5 4 3 2 1
[16,17,18]
[17,20,27]
[16,17,18,19,30]
+1.05V_GFX
+1.35V_GFX
+3V_GFX 41
D D
VIN +1.05V_GFX +15V +1.05V_S5
5
PR197 PR198 PR199
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D1 4 PQ43
EV@MDV1528Q
3
3
+1.05V_GFX
3
2
1
PR201
[18,37] 3V_MAIN_PWGD
PR200 *EV@Short_4 2 EV@1M_4 2 2
PC145 +1.05V_GFX
TDC : 1.73A
PEAK : 2.3A
1
PQ44 PQ46 *EV@2.2n/50V_4
PQ45 EV@2N7002K EV@2N7002K
Width : 80mil
1
PC146 PR202 EV@PDTC143TT
1
*EV@1u/10V_4 EV@100K_4
VIN +3V_GFX +15V +3VPCU
C PR203 PR204 PR205 C
3
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D 2
3
3
PQ47
PR207 EV@AO3404 +3V_GFX
1
[10] DGPU_PWR_EN
PR206 *EV@Short_4 2 EV@1M_4 2 2
PC147
+3V_GFX TDC : 0.17A
PEAK : 0.23A
1
PQ49 PQ50 *EV@2.2n/50V_4

PQ48 EV@2N7002K EV@2N7002K
Width : 20mil
1
PC148 PR208 EV@PDTC143TT
1
*EV@1u/10V_4 EV@100K_4
2
VIN
+5V_S5
+3V
PC143 PC137 PC76

B EV@2200p/50V_6 EV@4.7u/25V_8 B
EV@1u/10V_4
5
PR196
EV@100K/F_4
7
PQ26
EV@MDV1528
V5IN
1.5GFX_DRVH 4
HWPG_1.5VGFX 1 9 PR211 PC149 1C1-1 2014/03/01 change PR193 to 9.3K for +1.35V. +1.35V_GFX
[17] HWPG_1.5VGFX PGOOD DRVH *EV@SHORT_6 EV@0.1u/50V_6
PR194 *EV@Short_4 1.5GFX_EN 3 10 1.5GFX_VBST PL5
3
2
1
[17] FBVDDQ_EN EN VBST EV@2.2uH_7X7X3
1.5GFX_TRIP 2 PU11 8 1.5GFX_SW
PR195 EV@78.7K/F_4 TRIP EV@TPS51211DSCR
SW
1.5GFX_TST 5 6 1.5GFX_DRVL
PC144 PR191 EV@464K/F_4 TST DRVL
5
*EV@1u/10V_4 12 11
GND GND PR192 PR193 +1.35V_GFX
GND
GND
GND
GND
11/4 Change to 78.7K/F *EV@4.7_6 EV@9.31K/F_4 1.35 Volt +/- 5%

FB
+
4 TDC : 3.3A
13
14
15
16
OCP=8A 1.5GFX_FB
PC153
EV@0.1u/50V_6
PC150
EV@330u/2V_7343
PEAK : 4.3A
L ripple current PQ25 PC142 OCP : 8A
3
2
1
EV@MDV1595S *EV@680p/50V_6 PR190

=(19-1.5)*1.5/(2.2u*290k*19) EV@10K/F_4 Width : 160mil
=2.165A
Vtrip=8-(2.165/2)*14mohm
=96.84mV
Rlimit=96.84mV/10uA*8=77.47Kohm
VFB=0.704V
A A

PROJECT : ZQ0
2A
+1.35V_GFX/+1.05V_GFX/+3V_GFX
5 4 3 2 1
1 2 3 4 5 6 7 8
VGA power up sequence

42
+3VPCU
PCH MOSFET +3V_GFX

A A
dGPU_PWR_EN
VGA_VID
VIN
+VGPU_CORE
VGPU_EN VIN +1.35V_GFX

PWM
+1.05V_S5
PWM
VGPU_PWRGD
OR FBVDDQ_EN DGPU_PWROK
Gate MOSFET +1.05V_GFX
HWPG_1.5VGFX
1.05V_GFX_EN
VGPU_PWRGD
EC_FB_CLAMP
EC
B B
VGA Reset Power States

Thermal Follow Chart
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
PLTRST# VIN +10V~+19V MAIN POWER ALWAYS ALWAYS

PEGX_RST# CPU NTC
PCH DGPU_HOLD_RST#
+3V_RTC +3V~+3.3V RTC POWER ALWAYS ALWAYS Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS Protection
PEX_RST timing +5VPCU +5V USB CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

CPU H_PROCHOT# PM_THRMTRIP# SYS_SHDN# 3V/5 V
I/O 3.3V +3V_S5 +3.3V LAN/BT POWER S5_ON S0-S5 CORE PWR H/W Throttling WIRE-AND SYS PWR
PEX_RST +5V_S5 +5V USB POWER S5_ON S0-S5
HSW ULT
+5V +5V HDD/SPK/HDMI POWER MAINON S0
C Trise >= 1uS Tfail <=500nS C
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
+1.35VSUS +1.35V CPU/SODIMM/MD POWER SUSON S0-S3
+DDR_VTT_RUN +0.675V SODIMM/MD Termination POWER MAINON S0 GPU NTC

Thermal SM-Bus1
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0 Protection CPU FAN
FAN1_PWM
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
+1.05V +1.05V PCH CORE VCCST POWER MAINON S0
+VCCIN variation CPU CORE POWER VRON S0 EC

GPU FAN2_PWM GPU FAN
+VGPU_CORE variation External GPU POWER VGPU_EN S0 CORE PWR
+3V_GFX +3.3V External GPU POWER dGPU_PWR_EN S0
dGPU_OPP#
dGPU_OTP#
dGPU_ALT#
SM-Bus1
+1.35V_GFX +1.35V External GPU POWER FBVDDQ_EN S0
GPU_THAL#
+1.05V_GFX +1.05V External GPU POWER 1.05V_GFX_EN S0
GPIO12 HW throttle
over power protect
D GPIO12_ACIN D
dGPU

dGPU_OPP# EC notify HW throttle over power protect PROJECT : ZQ0
dGPU_ALT# for ADPS circuit to infrom EC NV dGPU VPS Alert Size Document Number Rev
dGPU_OTP# VGA thrmtrip# => inform EC over temperature protect PWR Status & GPU PWR CRL & THRM 3A

1 2 3 4 5 6 7 8
5 4 3 2 1
Battery Mode
Support Deep Sx
3
+3VPCU
VIN 1
+5VPCU
VL
3 3
+3VPCU
5b
+3.3V_DSW
1
VIN BAT-V
43
3V_LDO 3V/5V 2
11 2 VR depend on A measure +3.3V_DSW
3 +5VPCU +5V_S5
+15V
result to implement EN CHARGER Battery
EN2
EN1
D
+3VPCU S5 PWR +3V_S5 10 4 for B test D
3
3
S5_ON 8 NBSWON# 5a DSW_ON +3VPCU or +3.3V_DSW
1 VIN Delay DSW power well 10ms DSW PWR

+3VCC_S5
PWR 6 DPWROK DPWROK
SUS PWR
DDR VDDQ +1.35V_SUS 18 BTN 13 RSMRST# +1.05V
RSMRST#
VR 7 14 SB_ACDC ASW PWR
DDR_VTTREF 19 EC ACPRESENT +3V_S5
30 DNBSWON#
15 PWRBTN#
HWPG SUSC# 16 SPI PWR
+DDR_VTT_RUN 23 SLP_S4# +V1.05DX_MODPHY
SUSB# 20 SLP_S3#
HSIO PWR
PCH_SUSACK# SUSACK +1.05V
HWPG_VDDR 24
PG PCH_SUSPWARN# SUSWRAN
PLL PWR
S5
S3
PCH_SLP_SUS# SLP_SUS# +1.05V

PCH
DDR_PG_CTRL APWROK CORE PWR
C
22 +3V C
31 EC_PWROK PCH_PWROK
MAINON
21 PCH_CLK SDIO PWR
35 +3V_S5
VRON
SUSON
S5_ON
MAINON
EC_PWROK
HWPG_1.05V_EC#
+0.75V_ON PLTRST#
+0.75V_ON
? PLTRST#
38 SYS_PWROK HDA PWR
SUSON SYS_PWROK
17 34 IMVP_PWRGD
+3VPCU 24 HWPG_VDDR
3 36
26 HWPG_1.05V 31 EC_PWROK 38
+1.5V 12 30a 31 32b 21 17 8
1.5V
PLTRST#
HWPG_1.5V
VR 29 29
HWPG_1.5V ?
PG
EN
+VCCIN
MAINON CORE PWR

21 +1.35V_SUS
RESET#
CPU
VDDQ PWR
+1.05V_VCCST
RUN PWR +1.05V
+1.05V_VCCST PROCPWRGD
B
3 +5VPCU +5V 28 VCCST PWR B
MOS1
SM_PG_CNTL1
VCCST_PWRGD
0 ohm
3 +3VPCU +3V 27
VR_READY
MOS2
VR_EN
10K ohm
SVID
+1.05V_S5 +1.05V
9 25
MOS3
G
HWPG_1.05V
1 VIN 12
MAINON
VRON_CPU
DDR_PG_CTRL
21
IMVP_PWRGD
VCCST_PWRGD_EN
SVID
33
+VCCIN EC_PWROK VCCST_PWRGD_EN
IMVP 31
VIN
1 9 VR
SYS_PWROK
+1.05V_S5 36
+1.05V_S5
VR 34
12 IMVP_PWRGD HWPG_1.05V_EC# 37 22 34 32a
HWPG_1.05V PG 30a
EN
PG
EN
A A
8 SVID VRON_CPU 32a HWPG+1ms

S5_ON
37 VRON 32b
PCH MAINON 21
CPU Quanta Computer Inc.
PROJECT : ZQ0
3A
Power Sequence
5 4 3 2 1
1 2 3 4 5 6 7 8
+3V_S5 +3V 44
SDRAM
2.2K 2.2K 4.7K 4.7K
+3.3V_RUN
AP2 SMB_PCH_CLK CLK_SCLK
A 2N7002DW A
AH1 SMB_PCH_DAT Level shift CLK_SDATA Touch PAD
+WL_VDD
XDP
4.7K 4.7K
+3V_S5
WLAN_CLK_SCLK
2N7002DW
Haswell Level shift WLAN_CLK_SDATA WLAN
ULT
+3V_S5
2.2K 2.2K
B B
AN1 SMB_ME0_CLK
AK1 SMB_ME0_DAT
+3V_S5
*2.2K *2.2K
+3V_S5
AU3 SMB_ME1_CLK
*2N7002DW
AH3 SMB_ME1_DAT Level shift
+3V_S5 3V3MISC
C C
10K 10K 4.7K 4.7K
+3V_GFX
116 2ND_MBDATA
2N7002DW
115 2ND_MBCLK Level shift dGPU
SIO +3VPCU
100
ITE8587
10K 10K Battery
D 100 D
110 MBCLK
111 MBDATA Charger

PROJECT : ZQ0
3A
Block Diagram
1 2 3 4 5 6 7 8
5 4 3 2 1
實實實defult
虛實實reserve
SYS_HWPG S5D
MDV1528Q +5V_S5 45
2 VGPU_PWRGD
9
3V_LDO PWRGD
1 +5VPCU MDV1528Q +5V
D
PWR EN! PWRGD
D
S5_Vout
3V/5V MAIND
VIN Vin
VGPU Core Vout
+VGPU_CORE
4 uP1642
TPS51225
3V_LDO EN
1 EN2 VGPU_EN
Vin S3_Vout +3VPCU 7
AO3404 +3V_S5 PCH
VIN
S5D
2
HWPG_1.5VGFX
AO3404 +3V 10
MAIND PWRGD
4
VIN Vin
+1.35V_GFX Vout
TPS51211
+1.35V_GFX
EC_FB_CLAMP EN
C
AO3404 +3V_GFX EC OR Gate FBVDDQ_EN
C
VGPU_PWRGD
dGPU_PWR_EN 9
PCH
VGPU_EN
7
HWPG_1.05V
MDV1528Q +1.05V
PWRGD
VIN +1.05V_S5 MAIND

Vin Vout +1.05V_S5 4
TPS51211
IMVP_PWRGD
EN
S5_ON MDV1528Q +1.05V_GFX
2 EC PWRGD
HWPG_1.5VGFX
10 1.05V_GFX_EN VIN CPU VCCIN +VCCIN
B B
AND Gate Vin Vout
MAINON TPS51622
4 EC VGPU_PWRGD EN
9 VRON_CPU
VRON
HWPG_VDDR
HWPG_1.5V
SUSON PWRGD
3 EC S5 EN
+1.35V_SUS
S5_Vout
+1.35V_SUS DDR_VTTREF PWRGD
TPS51216
+3VPCU Vin
+1.5V Vout
DDR_VTTT_PG_CTRL TPS54318
+1.5V
PCH S3 EN EN
Vin S3_Vout +DDR_VTT_RUN
MAINON MAINON
A 4 A
+0.75V_ON
EC
VIN
PROJECT : ZRQ
3A
ULT PWR CONTROL
5 4 3 2 1
5 4 3 2 1
Model Version CHANGE LIST

ZQ0 1A-1 1 2013/10/15 change pin define and add pwm IC.(page31)
2 2013/10/15 Change VGA ITE solution to NXP.(page 23)
3 2013/10/15 power board CN change to 6pin.(Page 23)
4 2013/10/15 U5017.12 change 27M crystal to VGA IC.(Page 23)
5 2013/10/15 U5017.14 add power rail +3V_RTC(page23)
6 2013/10/15 strap0 R672 DG 50k PU.(Page 19)
7 2013/10/15 Change AND gat to Q63 D-MOS.(Page 19)
8 2013/10/15 change pin define and add pwm IC U17.(Page 46)
9 2013/10/15 for GC6 stuff R228\R1013\R226\R1012.un-stuff Q24\Q26\R227\R1011. (Page19)
D D
10 20131015 For GC6 NV DG GC6_FB_EN PD.(Page10)
11 2013/10/15 following up acer define and swap USB3 and USB2 port.(Page9)
12 2013/10/15 swap CAP C8579/C8580 to Vrefo and resistor R5214/R5215 to Line in.(Page30)
13 2013/10/15 U27.30/U27.31 del fan Pwm signal.(Page32)
14 20131015 change LVDS\USB3\RJ45\FAN\TPD\USB DB CN\DC-IN CN\Power Button\Cardreader\KB BLK CN\Power board, footprint.
1 2013/10/16 JDIM5 Swap M_B_DQS2/M_B_DQS3 and swap M_B_DQS#2/M_B_DQS#3.(page15)

1A-2
2 2013/10/16 JDIM6 Chage net name M_B_DQS#[7:0] to M_A_DQS#[7:0].(page14)
3 2013/10/16 Add RTC charge circuit.(page8)
4 2013/10/16 BT1.1 Chage +3V_RTC_0 to VCCTC_2.(page8)
5 2013/10/15 change power rail from +3V_RTC_0 to VCCRTC_2.(page23)
1 2013/10/16 change R5285 from 330 to 100ohm for charge RTC battery.(page23)
1A-3
2 2013/10/16 2013/10/16 U58 add 0ohm R5322/R5323 for SMBus reserve for FW burnning.(page 23)
3 2013/10/16 U58 pin24/25 add 33ohm for HSYNC/VSYNC.(page23)
4 2013/10/16 U58.37 add 10 ohm for test pin avide i2c impact.(page 23)
5 2013/10/16 U24 ball K4/G2 BIOS suggestion change SMI/SCI to GPIO0~15.(page 10)
6 2013/10/16 Add U34 flash 4M ROM reserve for ZQ0D.(page8)
7 2013/10/16 change SMbus VGA to PCH SML0CLK/SML0DATA.(page 8)
1A-4 1 2013/10/17 Change EC pin define for 2014 GPIO table.(page32)

2 2013/10/17 Change All short pad to resistor.(All)
3 2013/10/17 Change U17 to G991P11U and PU U17 pin1.(page31)
4 2013/10/17 Remove Q25\R231\R232 because not support GPIO9 for ADPS circuit to infrom EC NV dGPU VPS Alert.(page19)
5 2013/10/17 remove Q5020 no IOAC support.(page26)
6 2013/10/17 remove R5224\R5225\R5226 no IOAC support.(page26)
7 2013/10/17 remove WLAN_OFF no IOAC support.(page26)
C C
8 2013/10/17 Del U22 becuse no support IOAC.(page32)
1 2013/10/18 Change CN21 Pin8 for I2C/PS2 TPD idendify.(Page31)

1A-5
2 2013/10/18 Change VGA NXP soltion to ITE.(page23)
3 2013/10/18 design change R5293 from 22ohm to 33ohm.(page23)
4 2013/10/18 Change Touch screen power rail from 5V to 3V.(page24)
5 2013/10/18 add 0ohm short TP interrap pin.(page24)
6 2013/10/18 change U27.87 for Touch pad ID for I2C/PS2 solution switch.(page 32)
1 2013/10/18 Change Q63 to MOS.(page19).
1A-6 2 2013/10/21 reversal PEG lan for layout.(page9).

3 2013/10/21 Del APWORK.(page5)
4 2013/10/19 Swap DDR so-ddim pin for layout request.(page14,15)
1 2013/10/22 change CN24 pin define based on spec.(page31)
1A-7 2 2013/10/22 change CN25 pin define for spec.(page31)

3 2013/10/22 Change CN4 to 6pin.(page23)
4 2013/10/22 change Y5004 to +/-10PPM(page23)
5 2013/10/21 add R5331 between 3V_GFX and 3V_MIN for not GC6 support.(page20)
6 2013/10/22 change PJ1 Pin define same as ZQN.(page33)
7 2013/10/22 Change LGND to GND.(page28)
8 2013/10/22 CN5006 pin9/10 add R5332/r5333 for ESD protect.(page28)
9 2013/10/22 Change CN5009\CN5013\Y7 footprint.
1 2013/10/22 change CN24 pin define based on spec based on ZRQ.(page31)

1A-8
2 2013/10/23 change CN25 footprint.(page31)
3 2013/10/23 Change DIMM1_SA0/SA1 to DIMM0_SA0/SA1.(page14)
B
4 20131022 Change GPIO83/84 GPU GC6 pin to GPIO2/3.(page10) B
5 2013/10/21 Swap PEG to nomroal mode.(page9)

6 2013/10/23 remove R5017 5V is duplicater.(page27).
7 2013/10/23 remove C5056 is duplicater.(page27)
8 2013/10/23 change CN5008\CN25 footprint to match DXF.
9 2013/10/23 add scrow Hole footprint.
1 2013/10/17 Change power LED from +3VPCU to +3V_S5.(page27)

1A-9 2 2013/10/24 add 100kohm on U5011 pin 26 with C5164 for discharge(page30)
3 2013/10/23 add 10k for vendor suggestion.(page28)
4 2013/10/23 add R5335 Isolate SLB9660 NC.(page23).
5 2013/10/24 Add alert on U17.1 for CPU themal tempture.(page31).
1 2013/10/25 remove 1.35GFX_PDG NET.(page20)

1A-10
2 2013/10/25 remove 1.35GFX_PDG (page20)
3 2013/10/25 remove 1.35GFX POWER(page20)
4 2013/10/25 reserve AV2 ball to GND.(page6)
5 20131025 reserve A5 ball to 100k PU 3VPCU.(page6)
6 2013/10/25 modify PJ2 footprint.(page33)
7 2013/10/25 change LED from 3pin to 4pin for acer reqeust,(page27)
1 2013/10/28 Change U5013.7 from +3V_S5 to +3V.(page23)

1A-11
2 2013/10/28 change LED from 4pin to 3pin and power LED to +3VPCU.(page27)
3 2013/10/28 U5013 Pin8,15,28 left NC.(page23)
1A-12 1 2013/10/29 Change CN21 power rail to S5,change Q42 direction and net name reseve PS2 PU to +3V.(page31)
2 20131029 Change GPIO45 to PU S5,duble GPIO58 one is GPIO56.(page10).
3 2013/10/28 reserve AV2 ball to TP.(page8)
A A
4 20131028 reserve A5 ball toTP.(page6)
5 2013/10/29 Change CN5008 to S0 of SMbus(page26)
6 2013/10/29 Swap U27 pin2 and pin128,add U27.68 for touch pad interrupt.(page32)
1A-13 1 20131030 add touch pad interrupt pin on gpio83.(page10)

2 2013/10/30 move Q42 to page02 change U24.U7 net name.(page2).
3 2013/10/30 CN5002.6 add USB touch screen on/off pin to EC.(page24)
4 2013/10/29 add U27.35 for touch pad on/off.(page32)
DOC NO.
PROJECT MODEL Quanta Computer Inc.
: ZQ0 APPROVED BY: DATE:
PROJECT : ZQ0
3A
PART NUMBER: DRAWING BY: REVISON: Change list-1
5 4 3 2 1
5 4 3 2 1
Model Version CHANGE LIST

ZQ0 1B-2 1 2013/12/04 change PQ24 to DFN 3x3 size.(page35)
2 2013/12/04 Change Cn14 PN and footprint.(page30).
3 2013/12/04 change LED from 3pin to 4pin..(page27)
4 2013/12/4 change cN6 to 4pin.(page23)
5 2013/12/04 change GPIO36/GPI037 to PU..(page9)
1 2013/12/10 change Cn20 Pin define.(page25)

1B-3
2 2013/12/10 change Q3.3 from +3V to +3VPCU.(page22).
3 2013/12/10 change CN6 footprint..(page21)
D D
1B-4 1 2013/12/12 Remove U9 Green CLK circuit.(page21)
1 2013/12/17 Change CN14 pin define.(page28)

1B-5
2 2013/12/17 Change R8051 to 0402 size.(page16)
1B-6 1 2013/12/18 Change USB port USB3.0 to port0,USB2.0 to port1 and port3,Fingerprint to usb port2.
2 2013/12/17 Change R8051 to 0402 size.(page16)
3 2013/12/18 U34 pin6 reserve 0402 resistor for power noise issue.(page28)
1B-7 1 2013/12/20 add U29 VSYNC and HSYNC by pass resistor.(page22)

2 20131220 Change +3VPCU to +3V_S5 non deep sx(page10).
3 2013/12/20 del c8521 and R8391..(page16)
1C-1 1 2014/1/06 add 0ohm pass 1.05V_Modphy to 1.05V.(page33)

2 2014/1/06 add PR224 PU to 3V.(page33).
3 2014/1/06 Change R351\R388 from 47ohm to 65ohm base on FAE request..(page28)
4 2014/01/10 Remove U29 and add U40 and U41..(page22)
1C-2 1 2014/01/13 Change TP power rail from +3V_S5 to +3V_SUS.(page29)

2 20140113 PU6\PU12 change footprint for SMT request.(page35).
3 2014/01/13 change CN14 sata net name and add C678~C681.(page25)
4 2014/01/13 add R678\R677 PU and R679 PD for ICT..(page19)
5 2014/01/131/13 Adding +3V_SUS power for touch pad (acer request).(page32)
1C-3 1 2014/01/14 change R654 to 0ohm.(page27)

2 2014/01/14 Change Cn11 Footprint.(page24).
1C-4 1 2014/01/15 reserve TP power rail +3V_S5..(page29)

2 2014/01/15 TPM CO-lay nuvoton(page21).
C C
3 2014/01/15 SWAP PCIE LAN TX single.(page26).
1 2014/03/01 change PR193 to 9.3K for +1.35V.(page38)

1C1-1
2 2014/02/17 Add U11.98 GPIO5 for PTP power en function.(page30).
3 2014/02/17 Add Q47 for PTP power EN and soft start R694\C713 and C712\C686.(page29)
4 2014/02/06 change Blue LED power rail to +5VPCU and add ESD and Change LED to lite-on and R379=820,R375=680 base on test result.(page25)
5 2014/02/6 add VGA_ALERT# PU 10K for FAE request.(page19)
6 2014/02/19 add R692 for SUSPWRACK# to EC.(page07)
7 2014/03/01 Change 0ohm to short pad.
8 2014/03/01 link L29 to +3V directly(meet IVDDO vs OVDD sequence)(page 21)
1 2014/03/08 add R696\R697 PU..(page30)

1C1-2
2 2014/03/08 ChangeU12 footprint to sot23 and add VC2\VC1 change C307 to 3528.(page27).
3 2014/03/08 Remove PCIE wake and stuff R642, un-stuff Q44..(page24)
4 2014/03/11 Add R698 for TS_EN short TP_INT,for issue debug.(page22)
B B
A A
DOC NO.
PROJECT MODEL Quanta Computer Inc.
: ZRQ APPROVED BY: DATE:
PROJECT : ZQ0
3A
PART NUMBER: DRAWING BY: REVISON: Change list-2
5 4 3 2 1

E5-471quanta Da0zq0mb6e0 MB PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

E5-471quanta Da0zq0mb6e0 MB PDF

Uploaded by

Copyright:

Available Formats

5 4 3 2 1

ZQ0_GDDR3 BWD ULT SYSTEM BLOCK DIAGRAM IV@

Quanta Computer Inc.

Haswell ULT (DISPLAY,eDP)

[23] INT_HDMITX1N DDI1_TXN1 EDP_TXN1 EDP_TXN1 [22]

[21] CRT_TXP0 DDI2_TXP0 EDP_AUXN EDP_AUXN [22]

1A-13 2013/10/30 move Q42 to page02

Quanta Computer Inc.

Change Data and DQS to interleave.

Quanta Computer Inc.

DRAM COMP XDP PU/PD DDR3L ODT GENERATION +1.35V_SUS

PU/PD of CPU DRAMRST

H_PROCHOT# R522 *62_4

CPU_DRAMRST# R227 *short_4 DDR3_DRAMRST# [14,15]

H_PWRGOOD_R R51 10K_4 C271

Size Document Number Rev

VDDQ Output Decoupling Recommendations

D Haswell ULT (POWER) VCCST_PWRGD R603 *short_4VCCST_PWRGD_R 4

C268 *MMBT3904-7-F C270 Q33

*1000p/50V_4 *1000p/50V_4 *DTC144EU

Date: Tuesday, April 08, 2014 Sheet 5 of 46

CFG3 DISABLED ENABLED CFG3 R549 *1K_4

CFG 8 DISABLED(DEFAULT); IN THIS CASE, NOA ENABLED; NOA WILL BE AVAILABLE

CFG9 NO VR SUPPORTING SVID IS PRESENT. THE CFG9

SYSTEM POWER MANAGEMENT

EC_PWROK R612 *0_4 SYS_PWROK_R

PCH PM PU/PD PLTRST# Buffer Deep Sx Circuit Non Deep Sx

SYS_RESET# R516 10K_4

DPWROK_R R598 100K/F_4 TC7SH08FU R175

PCH_BATLOW# R262 8.2K_4

R116 *10K_4 TC7SH08FU R615

RTC Clock 32.768KHz (RTC)

HDA_SYNC_R AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6 PCH_SPI_CLK AA3 SML1DATA/GPIO74

1A-22013/10/16 Chage +3V_RTC_0 to VCCTC_2. +3V V1 VGPU_EN VGPU_EN [37] 7 OF 19

R194 IO2/WP# CLK 5

Pin Name Strap description Sampled Configuration note

0 = Default SPI (iPD 20K) [10] GPIO86

confidentiality [30] PCH_SPI_SI_EC

0 = Enable an external display

VGA WLAN LAN

USB3RP1 USB3_RXP0 [27] [16] CLK_PCIE_VGA CLKOUT_PCIE_P4

[24] PCIE_RX4-_WLAN PERN4 CLKOUT_PCIE_P5

Quanta Computer Inc.

GPU power is control by PCH

+V1.05S_VCCUSBCORE R270 *SHORT_8 +1.05V

1A-1 2013/10/11 del LDO change to MOS.

+1.05V +V1.05S_APLLOPI L5 2.2uH/210mA_8

C121 C122 C99

PCH HDA Power L2 2.2uH/210mA_8

Haswell ULT (GND) 12

DC_TEST_AY2_AW 2 AY2 A3 DC_TEST_A3_B3

H_SYS_PWROK_XDP R287 *1K_4

[5] PWR_DEBUG XDP_RST_R_N R204 *1K_4

[8,14,15,24] CLK_SDATA XDP_TDO R395 *51_4 +1.05V_S5

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

+VREF_CA_CPU R382 *Short_6 R311 2/F_6

0.022u/16V_4 1.8K/F_4 470p/50V_4

C315 + C297 C321 C336 C299 C288

C314 C296 C294 C318 C316 2.2u/6.3V_6 2.2u/6.3V_6

SA1 SA0 Quanta Computer Inc.

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

1000p/50V_4 1000p/50V_4 *DTC144EU