B222L Microcontrollers and Programmable Logic

Problem Based Learning

Exploring Combinational and Sequential Logic with VHDL

The aim of this task is to design and implement two digital logic systems, one
combinational and the other sequential, using VHDL models targeted at a Xilinx
XCR3064XL CPLD, with Xilinx ISE PC based Synthesis and Simulation tools.
Both designs will be implemented using a general purpose CPLD board and a "traffic light" board to
provide switches and LEDs for inputs and outputs. Each task will be designed as a separate entity.

Combinational Logic Task:

Requirement - Using the yellow(amber) and green buttons as inputs the LEDs should light when the
when the buttons are pressed as shown in the table below. The Red button, when pressed should select
which set of three LEDs will be illuminated.

Sequential Logic Task:

Requirement: - The system will have two modes of
operation. In the first mode the LEDs will light in a
repeating shifting sequence as shown in the first
diagram. In the second mode the LEDs will flash in a
repeated sequence as shown in the second part of the
diagram.

The system will "free run" with a clock rate of 2Hz.

The system will default to Mode 1, with Mode 2
selected by pressing any of the buttons.

© University of Portsmouth - Dunn & Parchizadeh - February 2012

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 B222L Microcontrollers and Programmable Logic
Problem Based Learning
Exploring Combinational and Sequential Logic with VHDL

Timescales:
The VHDL related coursework covers the final 5 weeks (semester weeks 6 to 10) of the lab schedule.

Week 6 - 08 Mar - Introduction to Xilinx ISE VHDL Synthesis and Simulation Tools
Weeks 7 & 8 - 15/22 Mar - Combinational Logic VHDL Task
Weeks 9 & 10 - 29Mar/26Apr - Sequential Logic VHDL Task

Method of Working:
A key to the successful design, simulation and synthesis of a VHDL model is adopting a systematic
approach with an attention to detail. The best was of achieving this is by documenting the design process
as it takes place. Adopting this approach will avoid errors; time wasted re-designing, and confusion.

The logbook should therefore record - for each task

• Summary overview of the requirement
• Initial ideas and exploration of possible approaches for implementation
• Detailed design discussion, justification, development detail, expected outputs
• Commented VHDL listings for Model under development and VHDL Test-bench
• Verification/Simulation results highlighting area where behaviour is correct / incorrect
[+ detail of any modifications to solve problems and subsequent corrected simulation results]
• Synthesis results [+ detail of any modification to remove errors / warnings – and subsequent simulation results]
• Implementation Constraints File detail [mapping signal names to device pins]
• Implementation to target hardware results
• Results of system level testing.

Assessment:
Work on these tasks will be normally done in teams of two. A final mark will be awarded individually.
The VHDL tasks are together are worth 20% of the coursework for B222L.

The breakdown for marking the VHDL tasks will be as follows:

• Combinational Logic - Correctly working. 5% Marks "out of 5" scale:
• Combinational Logic - Individual development record in logbook 5% Excellent 5
• Sequential Logic - Correctly working. 5% Very good 4
• Sequential Logic - Individual development record in logbook 5% Good 3
Poor 2
Very poor 1
It should be possible with planning ahead and some background No real attempt 0
Where marks of 0 & 1
preparation to achieve a working system for demonstration by the second represent a fail
week for each of the tasks.

Logbooks will be marked at the end of the second task, or if there is insufficient time, handed in
for marking.

Late completion, non attendance, and/or non submission of a logbook will lead to reduced marks -
unless covered by a valid ECF.

© University of Portsmouth - Dunn & Parchizadeh - February 2012

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