1.

SENSE AMPLIFIER DESIGN

The sense amplifier is a differential sense amplifier, also known as voltage mode sense amplifier. It consists of a differential pair
with an active current-mirror load with a biasing current source. The bit lines are connected to the gates of the differential pair
transistors and the output is taken from the same side as Blb.

The design of the sense amplifier is a current mode differential input single ended amplifier in order to attenuate the common
mode noise and amplify the differential mode signals. The main reason for using this type of sense amplifier is to improve the
noise immunity and speed of the read circuit. The differential signal that changes between the two bit lines during read operation
is amplified by the differential pair current mode sense amplifier. The transistors are sized such that the differential voltage is
amplified suitably for read operation. The sense amplifier is designed to speed read operations by sensing a differential voltage
on the bitlines and reading the value without requiring rail-to-rail voltage swing on BL/BLB.

1.1 Sense Amplifier Operation

The circuit can be divided into three components: the current mirror, common source amplifier, and the biasing current source.
All transistors are initially place in the saturation region of operation so that the gain is large.
The two transistors, NI and N2, act to provide the same current to the two branches of the circuit. That is, the current flowing
through P1 is mirrored in P2:
𝐼𝑝1 = 𝐼𝑝2

Any difference in the two currents is due to differences in their Vds values. The transistor N3 sets the bias current, Iss, which
depends on the bias voltage, SE.

The two input transistors, N1 and N2, form a source-coupled differential pair. The two input voltages, BL and /BL, are connected
to the column lines.

1.1.1 Operation Specifics

The NMOS current source size is chosen differently than the other five MOSFETs. When the amplifier is enabled, this device
creates a constant current flow through the other transistors in the amplifier. One way of reducing the power consumption of the
sense amplifier as a whole is to limit the current that is allowed to flow through the system before the amplifier latches. In
order to do this, the MOSFET is sized so that the width (W) is larger than the length (L) which effectively limits the current and
reduces the power consumption.

2. ROW DECODER

The row decoder and column decoder are essential elements in all random-access memories. It is used to select the
particular cell onto which the data is to be written or from which the data is to be read. Time to access and power
consumption are largely determined by the decoder performance. Row decoders having an n-bit address data and
gives 2n outputs, one of which activates a cell of the SRAM (Mishra, Acharya, & Patra, 2014).

In this design, a 64X64 array is used creating a 4KB of SRAM. For this memory size, the addressing will used a 5-
bit row and 2 bit-column wide mode. The 5:32 decoder utilizes a predecoder and final decoder stage topology as
shown in Figure …… In this architecture, the predocoder stage generates intermediate signals that are used by
multiple gates in the final decode stage. It reduces the gate count, also the number of stages from input to output
which results in reduction in delay and power consumption.
The row decoder has to be sized precisely using logical effort based on the capacitance of the wordline. The gates
were sized as follows:

Unit Unit Unit Unit Unit

Stage 1 Stage 2 Stage 3 Stage4 Stage 5
width width Width width width
Cin 5.000E-01 0.828613504 2.746401 2.275705 7.543E+00
NMOS
Width 1 1.35E-07 4 5.4.E-07 1 3.71E-07 4 6.14E-07 1 1.02E-06
PMOS
Width 5 2.70E-07 2 2.7E-07 5 1.85E-06 2 3.07E-07 5 5.09E-06