Laboratory Report Cover Sheet

UET ABBOTABAD CAMPUS

Faculty of Department of Electronics Engineering

ELE-305
VLSI DESIGN
th
6 Semester spring 2021

Name: Sanaullah Hukam

Register No. : 18ABELT0793

Venue: Computer Laboratory # 1

Lab No. : 11

Lab Title: To study the Electrical Characteristics of PMOS and NMOS

Date of Conduction: June 29, 2021

Date of Submission: June 30, 2021

Particulars Maximum Marks Marks Obtained

Pre-lab 20

simulation 40

Data analysis 40

Total 100

REPORT VERIFICATION

Date:
Staff Name: Engr. Mehmoona Gul
Signature:
 ELE-305 VLSI DESIGN LAB-MANUAL

LAB #11

To study the Electrical Characteristics of PMOS and NMOS

11.1 Objective
➢ The purpose of this experiment is to analyze the changes in characteristic curve of pmos
and nmos by varying different parameters of MOSFET design.
➢ To study the effect on drain current by varying
o channel length L
o channel width W
o Channel Resistance RChannel
o Mobility of charge carriers 𝝁o
o Threshold voltage VTo
o Gate voltage Vg
o Bulk voltage Vb
o Source Voltage Vs
o Drain Voltage Vd

11.2 Theory
11.2.1 Cmos Technology:
In cmos technology the combination of P-mosfets & N-mosfets is used for the better results.
As it is understood that n-mosfets completely transmits logic 0 but partially logic 1 while p-
mosfets completely transmits logic 1 but transmit logic 0 with error. So to overcome this
problem p & n mosfets are used in combination called Complementary Mosfets (cmos)

There are certain advantages of cmos technology.

o High noise immunity property is possessed by cmos.

o CMOS has relatively less number of transistors where as TTL has a number of
transistors and a number of resistors to perform the same function. Therefore CMOS
has low static power consumption.
o Due to less number of components CMOS devices are also cheaper & affordable.
o It enables chips that are small in size to have features like high operating speeds and
efficient usage of energy.

11.2.2 n-channel Enhancement-type MOSFET

Figure 1a shows the transfer characteristics (drain-to-source current IDS versus gate-to-
source voltage VGS) of n-channel Enhancement-type MOSFETs. From this, it is evident that
the current through the device will be zero until the VGS exceeds the value of threshold
voltage VT. This is because under this state, the device will be void of channel which will be

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connecting the drain and the source terminals. Under this condition, even an increase in VDS
will result in no current flow as indicated by the corresponding output characteristics (IDS
versus VDS) shown by Figure 1b. As a result this state represents nothing but the cut-off
region of MOSFET's operation.
Next, once VGS crosses VT, the current through the device increases with an increase in IDS
initially (Ohmic region) and then saturates to a value as determined by the VGS (saturation
region of operation) i.e. as VGS increases, even the saturation current flowing through the
device also increases. This is evident by Figure 1b where IDSS2 is greater than IDSS1 as
VGS2 > VGS1, IDSS3 is greater than IDSS2 as VGS3 > VGS2, so on and so forth. Further,
Figure 1b also shows the locus of pinch-off voltage (black discontinuous curve), from which
VP is seen to increase with an increase in VGS.

11.2.3 p-channel Enhancement-type MOSFET

Figure 2a shows the transfer characteristics of p-type enhancement MOSFETs from which it
is evident that IDS remains zero (cutoff state) untill VGS becomes equal to -VT. This is
because, only then the channel will be formed to connect the drain terminal of the device with
its source terminal. After this, the IDS is seen to increase in reverse direction (meaning an
increase in ISD, signifying an increase in the device current which will flow from source to
drain) with the decrease in the value of VDS. This means that the device is functioning in its
ohmic region wherein the current through the device increases with an increase in the applied
voltage (which will be VSD).

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However as VDS becomes equal to –VP, the device enters into saturation during which a
saturated amount of current (IDSS) flows through the device, as decided by the value of
VGS. Further it is to be noted that the value of saturation current flowing through the device
is seen to increase as the VGS becomes more and more negative i.e. saturation current for
VGS3 is greater than that for VGS2 and that in the case of VGS4 is much greater than both of
them as VGS3 is more negative than VGS2 while VGS4 is much more negative when
compared to either of them (Figure 2b). In addition, from the locus of the pinch-off voltage it
is also clear that as VGS becomes more and more negative, even the negativity of VP also
increases.
11.3 PRE-LAB:
1. Draw the current characteristics curve of Mosfet.

Ans).

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2. Why the effective length is different from drawn values.

Ans).

The drawn channel length of a transistor is in general different from the electrical channel length.
We call the electrical channel length Leff while the drawn channel length is called drawn. Therefore
the transistor I V, curves should be represented by Iesat = "nox-(V-V) -MCoxW.

3. Define scaling theory

Ans).

Technology scaling results in reduction of the lateral and vertical dimensions of transistors. The
supply voltage (VDD) is scaled down to reduce power dissipation and to maintain device reliability
(avoid oxide breakdown). MOSFET scaling is the reduction in the parameters (like current, voltage,
electric field etc.) due to reduction in length of the transistor with the advancement in technology.
The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as scaling.

11.4 Software tools Requirement

➢ Microwindv2-7 installed PC.

Procedure:

➢ First of all open the software by clicking on-to the icon .

➢ For the specific gate select the required components by clicking the icon palette

.
➢ Micro wind software includes a comprehensive library, from this library (palette),
from palette we can select Metal Layers, Diffusion Layers, Polysilicon Layers,
Connectors, Clock Signals, Vdd for making the device layouts.
➢ Draw different layers by selecting the layer & then drawing by click & drag.
➢ We can also see the 2D look & 3D look of the layout by clicking the required icon
from icon menu.
➢ The components attributes can be changed by double clicking on-to the component
there by changing the required field.
➢ After completing the circuit diagram simulate the circuit by clicking & the figures
window will appear.

Pmos Characteristics:

➢ Click on to the icon to obtain the Characteristics of CMOS.

➢ A window will appear at the bottom of which we get to options ,

➢ From these to select option to analyze the pmos characteristics

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Characteristic Curve Between Drain Current "𝑰𝒅𝒔 " & 𝐷𝑟𝑎𝑖𝑛 𝑡𝑜 𝑆𝑜𝑢𝑟𝑐𝑒 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 "𝑽𝒅𝒔 ":

Figure # 1: 𝐼𝑑𝑠 𝑉𝑠 𝑉𝑑𝑠 Curve

Layout:

Analyze the value of current for varying channel length:

o Effect of Channel Length On Current:

Length Width Maximum Current

L=0.120µm W=10µm 11.4mA
L=0.3µm W=10µm 4.4mA
L=0.7µm W=10µm 1.8mA
L=1 µm W=10µm 1.325mA
L=2 µm W=10µm 0.675mA
L=3 µm W=10µm 0.440mA

Concluded the result from the observed values that current related to channel length:

𝟏
Ids ∝ 𝑳

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When we increase the channel length of MOSFET, current decreases. Reason for this
behavior is that when we increase the length of MOSFET, the electrons have to travel
for larger distance so amount of time required more, and also resistance becomes more
along the path. This more resistance being offered to electron flow results in lower
values of current. So, in conclusion Channel Length has indirect relation with current
and this was proved by the results of our experiment.

Effect of Channel Width On Current:

Length Width Maximum Current

L=0.120µm W=10µm 11.4mA
L=0.120µm W=13µm 14mA
L=0.120µm W=17µm 19mA
L=0.120µm W=20µm 21.5mA
L=0.120µm W=0.45µm 0.525mA
L=0.120µm W=0.240µm 0.265mA

Concluded the result from the observed values that current related to channel width:

Ids ∝ W
When we increase the channel width of MOSFET, current increases. This happens
because we the make MOSFET wider, there is larger room for electrons to flow
from one point to another. This increment in the area due to larger width results in
less resistance being offered to electrons flow. Thus, we get increased current. So, in
conclusion Channel Width has direct relation with current and this was proved by
the results of our experiment.

o Effect of Threshold Voltage & Channel Resistance On Current:

When we increase Threshold Voltage, Channel Resistance also increases as they have a direct
relation with each other. When the channel resistance increases, this result in the decreased drain
current. So, by increasing threshold voltage, we are decreasing drain current showing that
threshold voltage and drain current have indirect relation with each other. This was also proven by
the results of experiment performed above.

RChannel ∝ 𝑉𝑇
1
Ids ∝
𝑅𝐶ℎ𝑎𝑛𝑛𝑒𝑙

At L=1um and W=20um.

VT Current
-0.45 11.4mA

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-0.90 1.755mA
-1.10 0.20mA
-1.20 0mA

o Effect of Mobility of Charge Carriers On Current:

Mobility Maximum Current

0.010 5.51mA
0.015 8.2mA
0.020 11.4mA
0.005 2.75mA

Concluded Result: Ids ∝ µ𝒐

Mobility of charge carriers depends on the temperature. When we increase the
temperature, this results in increment in the mobility of charge carrier. As the mobility
of charge carrier increases, drain current also increases due to simple fact that a greater
number of electrons flowing through an area mean larger amount of current. So,
therefore mobility of charge carrier and drain current have a direct relation. This was
proved by the results of our simulation

o Effect of Bulk Voltage On Current:

Ids ∝ 𝑣𝑏
Due to the larger Vb, the depletion region between the channel and the substrate
becomes wider therefore more immobile charge (left behind when the mobile
carriers are repelled) becomes uncovered. This increases the current in the
channel. Which is proved by the result of experiment.

o Effect of Gate Voltage On Current:

1
Ids ∝ 𝑣𝑔
Here drain current increases with decrease in gate voltage because channel is
established after the gate voltage becomes greater than threshold voltage. By applying
gate voltage, it attracts more holes from substrate and channel becomes stronger and
stronger. So there is inverse relation between drain current and gate voltage. And also
proved by experiment.

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o Effect of Source Voltage On Current:

Ids ∝ 𝑉𝑠
Here drain current increases with increase in source voltage. Then potential difference
between source and drain increases, less resistance will be there in between source and
drain which will oppose the current flow. So there is direct relation between drain
current and source voltage. Which is further proved by experiment.

o Effect of Drain Voltage On Current:

Ids ∝ Vd
Drain current is increases with increase in drain voltage. For a given gate voltage
(e.g., VG = 0), the drain current initially increases linearly with drain voltage, indicating
that the conductive channel acts as a constant resistor. As the drain voltage increases,
however, the cross-sectional area of the conductive channel is reduced, causing an
increase in the channel resistance.(as pmos works on Vd) As a result, the current
increases at a slower rate and eventually saturates.

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11.5 Post LAB-Task.

Study and analyze the electrical characteristics of n-mosfet.
Characteristic Curve Between Drain Current "𝑰𝒅𝒔 " & 𝐷𝑟𝑎𝑖𝑛 𝑡𝑜 𝑆𝑜𝑢𝑟𝑐𝑒 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 "𝑽𝒅𝒔 ":

Layout:

Analyze the value of current for varying channel length:

o Effect of Channel Length On Current:

Length Width Maximum Current

L=0.120µm W=10µm 37.5mA
L=0.3µm W=10µm 14.5mA

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L=0.7µm W=10µm 6.25mA

L=1 µm W=10µm 4.5mA
L=2 µm W=10µm 2.25mA
L=3 µm W=10µm 1.5mA

Conclude the result from the observed values that current related to channel length:

𝟏
Ids ∝ 𝑳
When we increase the channel length of MOSFET, current decreases. Reason for this
behavior is that when we increase the length of MOSFET, the electrons have to travel
for larger distance so amount of time required more, and also resistance becomes more
along the path. This more resistance being offered to electron flow results in lower
values of current. So, in conclusion Channel Length has indirect relation with current
and this was proved by the results of our experiment.

Effect of Channel Width On Current:

Length Width Maximum Current

L=0.120µm W=10µm 36.1mA
L=0.120µm W=13µm 46.5mA
L=0.120µm W=17µm 61mA
L=0.120µm W=20µm 71.5mA
L=0.120µm W=0.45µm 1.7mA
L=0.120µm W=0.240µm 0.86mA

Conclude the result from the observed values that current related to channel width:

Ids ∝ W
When we increase the channel width of MOSFET, current increases. This happens
because we the make MOSFET wider, there is larger room for electrons to flow
from one point to another. This increment in the area due to larger width results in
less resistance being offered to electrons flow. Thus, we get increased current. So, in
conclusion Channel Width has direct relation with current and this was proved by
the results of our experiment.

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o Effect of Threshold Voltage & Channel Resistance On Current:

When we increase Threshold Voltage, Channel Resistance also increases as they

have a direct relation with each other. When the channel resistance increases,
this result in the decreased drain current. So, by increasing threshold voltage, we
are decreasing drain current showing that threshold voltage and drain current
have indirect relation with each other. This was also proven by the results of
experiment performed above.

RChannel ∝ 𝑉𝑇
1
Ids ∝ 𝑅
𝐶ℎ𝑎𝑛𝑛𝑒𝑙

At L=0.120um and W=20um.

VT Maximum Current
0.40 36.1mA
0.46 32mA
0.52 27mA
0.60 21.5mA
0.66 17mA
0.70 14mA

o Effect of Mobility of Charge Carriers On Current:

Mobility Maximum Current

0.010 11.9mA
0.015 17.9mA
0.020 23.9mA
0.005 5.9mA

Ids ∝ µ𝒐
Mobility of charge carriers depends on the temperature. When we increase the
temperature, this results in increment in the mobility of charge carrier. As the mobility
of charge carrier increases, drain current also increases due to simple fact that a greater
number of electrons flowing through an area mean larger amount of current. So,
mobility of charge carrier and drain current have a direct relation. This was proved by
the results of our simulation.

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o Effect of Bulk Voltage On Current:

Ids ∝ 𝒗𝒃
Due to the larger Vb, the depletion region between the channel and the substrate
becomes wider therefore more immobile charge (left behind when the mobile
carriers are repelled) becomes uncovered. This increases the current in the
channel.

o Effect of Gate Voltage On Current:

Ids ∝ 𝒗𝒈
Here drain current increases with increase in gate voltage because channel is
established after the gate voltage becomes greater than threshould voltage. By applying
gate voltage, it attracts more electrons from substrate and channel becomes stronger
and stronger. So there is direct relation between drain current and gate voltage. And
also proved by experiment.

o Effect of Source Voltage On Current:

𝟏
Ids ∝
𝑽𝒔
Here drain current decreases with increase in source voltage. Then potential difference
between source and drain decreases, more resistance will be there in between source
and drain which will oppose the current flow. So there is inverse relation between drain
current and source voltage. Which is further proved by experiment.

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o Effect of Drain Voltage On Current:

Ids ∝ 𝒗𝒅
Drain current is increases with increase in drain voltage. For a given gate voltage
(e.g., VG = 0), the drain current initially increases linearly with drain voltage, indicating
that the conductive channel acts as a constant resistor. As the drain voltage increases,
however, the cross-sectional area of the conductive channel is reduced, causing an
increase in the channel resistance. As a result, the current increases at a slower rate and
eventually saturates.

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