Prepare by;

CHAPTER 1: Mohaiyedin Idris

FKE UiTMPP
0124415995
1
LESSON OUTCOME
End of this lecture students able to;
➢determine the dc levels for the variety of important BJT/FET configurations.
➢measure the important voltage levels of a BJT/FET transistor configuration and use
them to determine whether the network is operating properly.
➢perform a load-line analysis of the most common BJT/FET configurations.
➢acquainted with the design process for BJT/FET amplifiers.
➢understand basic operating of BJT/FET amplifier for single and multistage amplifier.
➢design basic amplifier for both single and multistage amplifier encompass on
configuration for BJT and FET.

2
INTRODUCTION TO AMPLIFIER DESIGN - BJT

3
BJT AMPLIFIER DESIGN – SMALL SIGNAL DESIGN
➢DC AND AC CHARACTERISTIC
➢BIAS DESIGN and SMALL SIGNAL DESIGN

4
BJT AMPLIFIER: DC AND AC CHARACTERISTIC
The transistor is a three-layer semiconductor
device consisting of either two n- and one p-type
layers of material or two p- and one n-type
layers of material. The former is called an npn
transistor.
The p-type material consists of majority hole
while n-type consists of electron as majority
carrier.
When VCB voltage apply (Base-Collector), all the
electron will join with hole in p-type material and
become negative ion, this negative ion will attract
to positive potential of VCB, therefore electron
move from P to N, then when VBE voltage apply
to junction NP, where all the electron in n-type
material will push by negative potential in VBE
toward to collector. As movement electron
5
From the curve clearly indicate that the approximate
to the relationship between IE and IC in the active
region is given by;

6
7
 BJT AS VOLTAGE AMPLIFIER
To obtain output voltage as voltage amplifier, is by pass
output current (ic) through output resistor (Rc or Zout) and
take voltage across the resistor as the output.

Simple BJT amplifier with The voltage transfer characteristic (VTC)

Input vBE and output vCE of the amplifier

8
VTC - BJT
Biasing BJT is to obtain linear amplification from BJT.
The VBE is selected to obtain operation at a Q point on
the segment YZ of the VTC – Voltage Transfer Characteristic
(as show on figure).

The best Q point or bias point is the middle of YZ segment

9
BJT amplifier biased at a point Q with a small
voltage signal VBE.

The resulting output signal VCE appears with multiple

gain on the dc collector voltage VCE.

The amplitude of VCE is larger than VBE by the

voltage gain AV.

10
MULTISIM SIMULATION BJT - VTC

CLICK HERE FOR MULTISIM SIMULATION

11
MULTISIM SIMULATION VARIOUS OF DC CURRENT GAIN (β)

12
13
 VARIOUS OF DC CURRENT GAIN (β) USING
DATASHEET
TRANSISTOR : 2N2222A

TRANSISTOR: 2N2222A
min test current max min test current max
IC(mA) 0.05 0.1 0.15 min = test current - 50% of test current IC(mA) 75 150 225 min = test current - 50% of test current
choose β = 50 max = test current + 50% of test current choose βavg = 200 max = test current + 50% of test current

min test current max min test current max

IC(mA) 0.5 1 1.5 min = test current - 50% of test current IC(mA) 250 500 750 min = test current - 50% of test current
choose βavg = 200 max = test current + 50% of test current choose β = 30 max = test current + 50% of test current

min test current max

IC(mA) 5 10 15 min = test current - 50% of test current
choose β = 100 max = test current + 50% of test current
14
 IC (mA) Determine VTC by Graphical Analysis

It can be done by plotting IC vs VCE for both DC and AC load line

VO(MAX) ;
ICSAT AC LOAD LINE
It can be determine when either between GAP A or GAP B which one is smallest gap.
Example;
If GAP A smallest gap, then VO(MAX) = (VCEQ – 0 )Vp
If GAP B smallest gap, then VO(MAX) = (VCE’ – VCEQ)Vp

Q-POINT
ICQ

DC LOAD LINE

VCEQ VCE VCE CUTOFF

VCE (V)
GAP A

GAP B

15
16
 DETERMINE After determine IE, then calculate ib by refer  in datasheet/simulation
RESISTOR R1& R2 ib =

ic

set current iR 2 in the range of ;

iR 2 = ib  A
IR1

where A in range of 10,20,30...100

VR 2
R2 = ;VR 2 = VRE + VBE
iR 2

determine current iR1;

iR1 = ib + iR 2, then;
IR2

IE

VR1
R1 = ;VR1 = VCC − VR 2
iR1 17
BJT: BIAS SETUP
FIXED-BIAS SETUP

Provide relative straightforward and

simple bias setup. The current flow in base
provide enough condition to turn on npn-
transistor

18
EMITTER-STABILIZED SETUP

RE resistor connected in emmitter part of

transistor to improve the stability of fixed
bias configuration. With RE resistor, current
IE able to control for better requirement

19
VOLTAGE-DIVIDER SETUP

The combination resistor give complete way

to improve voltage control for biasing and
also the RE resistor give more stability
against the BETA effect (BETA very sensitive
with temperature)

20
HYBRID- MODEL FOR BJT

gmV  =  ib
IC  I E
VT
r = ; where VT = 26mV
IE

21
BJT AMPLIFIER: CONFIGURATION
COMMON EMITTER COMMON COLLECTOR COMMON BASE
AV HIGH (180° DIFFERENT ≈ 1 (SAME PHASE) HIGH (SAME PHASE)
PHASE)
AI HIGH HIGH ≈1
AP HIGH LOW MEDIUM
ZIN MEDIUM HIGH LOW
ZOUT MEDIUM LOW HIGH

22
 Start
DESIGN CONCEPT
Standardize Simulate circuit Analyse given
component with with calculate design
IEEE standard value specification

Simulate and Compare result Proposed

compare result from simulation suitable circuit
with given with given to meet all
specification specification criteria which
has been given

YES YES NO Analyse circuit

End Success Success
in dc and ac
aspect
NO 23
RESISTOR AND CAPACITOR E12 STANDARD

24
BJT-COMMON EMITTER DESIGN

Design Fixed Bias BJT emitter stabilized which given speciation;

RB RC
Transistor = BC107B
CO
ZIN ≤ 10kΩ OUTPUT

ZO ≤ 10kΩ INPUT
Q1
VCC
AV ≥ 40dB@100 BC107BP 20V

VCC = +20V

RE
CE

25
BC107A DC CURRENT GAIN(β)

COMMON EMITTER
AV HIGH (180° DIFFERENT
PHASE)
AI HIGH
AP HIGH
ZIN MEDIUM
ZOUT MEDIUM 26
 1) Given AV = 40dB @100 then IC (mA)

AVdB = 20 log AVdB

VIN VOUT Note that Gap B << Gap A
 40 
AV = log −1  
 20  ICSAT AC LOAD LINE
RB rpai RC AV  100
gmVpai
Set AV  100
Q-POINT
ICQ
ZIN
ZOUT
determine rπ from AV equation;
 −  RC  DC LOAD LINE
AV = 
 r  10V 12.6V 20V
VCE
VT VCEQ VCE CUTOFF
VCE (V)
where r = , thus; GAP A
ac parameter analysis for given circuit;
IE
2.6V 7.4V
VO  −  RC    GAP B
LOSSES
AV = = ;  −  RC 
VIN  r  AV = 
VT VT 
r =  
IE
;
 IE 
Zin = RB r ; RC  IE
AV = ; where VT = 26mV
ZO = RC ; VT
RC  IE
100 =
26m
2.6 = RC  IE; where RC  IE = VRC
VRC = 2.6V
set IE  IC = 2mA
VRC 2.6
RC = = = 1k 3 27
IE 2m
 VLOSSES =VRE = 7.4V   VT
Zin = RB r ; r =
VRE 7.4 IE
RE = = = 3k 7
IE 2m  290  26m 
RC Zin = 1.73M  
 2m
RB
Q1
as refer in datasheet,  =290 (typicall) Zin = 3.76k 
VCC
20V VCC − VRB − VBE − VE = 0
VCC − VBE − VE
BC107BP

RB = ZO = RC
IB
VCC − VBE − VE ZO = 1k 3
RE
RB =
IE

20 − 0.7 − 7.4
RB =
2m
290
RB = 1.73M 

28
Simulate with actual value Simulate with E12 resistor value

IE = 2.08mA IE = 1.97mA
VCE = 9.62V VCE = 9.6V

29
Based on the actual and standard resistor value, the gain which produced by using Multisim EDA tool
shown slightly achieve the targeted value.

30
BJT-COMMON EMITTER DESIGN

Design Voltage Divider Bias BJT emitter stabilized which given speciation;

Transistor = 2N2222A R1 RC

CO
ZIN ≤ 10KΩ OUTPUT

RL ≥ 50KΩ INPUT CIN

Q1
VCC
ZO ≤ 10KΩ RL

AV ≥ 33dB@44.67
VCC = +25V RE
CE

VOmax ≥ 3.5Vp R2

31
DC CURRENT GAIN (β)

COMMON EMITTER
AV HIGH (180° DIFFERENT
PHASE)
AI HIGH
AP HIGH
ZIN MEDIUM
ZOUT MEDIUM32
 VIN VOUT IC (mA)

1) Given that AV  33dB@ 44.67 then;

Note that Gap B << Gap A
R1R2 rpai RC RL

gmVpai determine rπ from AV equation;

ICSAT AC LOAD LINE
 −   RC RL 
AV =  
 r
VT
where r =
Q-POINT
and RC  RL  RC , thus; ICQ
IE
ZIN
ZOUT
  DC LOAD LINE
 −  RC 
AV = 
VT 
10V 15V 25V
VCE
 
VCEQ VCE CUTOFF
VCE (V)
 IE  GAP A
ac parameter analysis for given circuit; RC  IE 5 10V
AV = ; where VT = 26mV GAP B
VO  −   RC RL  VT
LOSSES
AV = =  ;
VIN  r AV  VT = RC  IE
VT
r = ; where RC  IE = VRC = VOMAX  3.5V ,choose VOMAX = 5V
IE
Zin = R1 R 2 r ; VRC = AV  VT
ZO = RC RL; VRC 5
AV = = = 192.3@ 45.68dB
VT 26m

as refer in datasheet, IC = 10mA and  = 100( set RL = 100k )

VRC 5
RC = = = 500
IC 10m
33
VLOSSES =VRE = 10V IR1 = IB + IR 2
VRE 10 IR1 = 0.1m + 5m
RE = = = 1k 
IE 10m IR1 = 5.1mA

VR 2 = VRE + VBE VR1 = VCC − VR 2

VR 2 = 10 + 0.7 VR1 = 25 − 10.7
VR 2 = 10.7V VR1 = 14.3V

IC 10m VR1 14.3V

IB = = = 0.1mA R1 = = = 2.80k 
 100 IR1 5.1m

  VT
IR 2 = A  IB Zin = R1 R 2 r ; r =
IE
A is multification factor, choose A = 50,thus;
100  26m 
IR 2 = 50  0.1m Zin = 2.81k 2.14k 
 10m 
IR 2 = 5mA Zin = 214.11

VR 2 10.7 ZO = RC RL
R2 = = = 2.14k 
IR 2 5m ZO = 500 ||100k
ZO = 497.51 34
 Simulate with actual value Simulate with E12 resistor value
IE = 10.1mA IE = 10.5mA
VCE = 9.7V VCE = 9.5V MULTISIM SIMULATION
Simulate with actual value

35
Based on the actual and standard resistor value, the gain which produced by using Multisim EDA tool
shown slightly achieve the targeted value.

36
BJT-COMMON EMITTER DESIGN UNBYPASS
CAPACITOR
Design Voltage Divider Bias BJT emitter stabilized with un-bypass
capacitor which given speciation;

Transistor = 2N2222A
ZIN ≤1kΩ
ZO ≤10kΩ
VOmax  3.5Vp
AV ≥ 5@13.97dB
VCC = +10V

37
DC CURRENT GAIN

COMMON EMITTER
AV HIGH (180° DIFFERENT
PHASE)
AI HIGH
AP HIGH
ZIN MEDIUM
ZOUT MEDIUM38
 Determine rπ from AV equation; where RC  IE = VRC = VOMAX = 3.5V
 −   RC RL  VOMAX
AV =   VE = − VT
 r +  RE  AV
VT 3.5
where r = and RC  RL  RC , thus; VE = − 26m
IE 5
  VE = 0.674V
 −  RC 
AV =  
VT
 +  RE 
 IE 
  set IE  IC = 5mA
 − RC  VE
ac parameter analysis for given circuit; AV =   ;where VT = 26mV and RE = as refer in datasheet the value of  =100,thus;
VT IE
VO  −   RC RL   + RE 
AV = =  IE 
VIN  r +  RE 
;
  VE = IE  RE
VT  − RC  VE 0.674
r = ; AV =  RE = =134.8 and;
IE VT VE  =
 +  IE 5m
Zin = R1 R 2 (r +  RE );  IE IE 
ZO = RC RL;  − RC  IE 
AV =  VOMAX 3.5
 VT + VE  RC = = = 700
IE 5m

39
 VR 2 = VRE + VBE IR1 = IB + IR 2
VR 2 = 0.674 + 0.7 IR1 = 50u + 5m
VR 2 = 1.374V IR1 = 5.05mA

IC 5m
IB = = = 50uA VR1 = VCC − VR 2
 100
IC (mA)
VR1 = 10 − 1.374
Note that Gap B << Gap A
ICSAT
IR 2 = A  IB VR1 = 8.626V
AC&DC A is multification factor, choose A = 100,thus;
LOAD LINE
IR 2 = 100  50uA VR1 8.626V
R1 = = = 1.71k 
IR 2 = 5mA IR1 5.05m
Q-POINT
ICQ
VR 2 1.374
10V R2 = = = 274.8
5.83V IR 2 5m
VCEQ VCE CUTOFF
VCE (V)
GAP A

GAP B
(3.5+0.674=4.17)V

40
   VT
Zin = R1 R 2 (r +  RE ); r =
IE
 100  26m  
Zin = 1.71k 274.8   (
+ 100  134.8 )
 5 m  
Zin = 232.82

ZO = RC RL
ZO = 700 ||100k
ZO = 695.13

41
Simulate with actual value Simulate with E12 resistor value
IE = 5.25mA IE = 5.23mA
VCE = 5.593V VCE = 5.693V MULTISIM SIMULATION

42
Based on the actual and standard resistor value, the gain which produced by using Multisim EDA tool
shown slightly achieve the targeted value.

43
BJT-COMMON COLLECTOR DESIGN

Design Voltage Divider Bias BJT emitter stabilized which given speciation;

Transistor = 2N4400
ZIN ≥ 1kΩ
ZO ≤ 500Ω
AV ≈ 1
VCC = +9V

44
2N4400 DC CURRENT GAIN

COMMON COLLECTOR
AV ≈ 1 (SAME PHASE)
AI HIGH
AP LOW
ZIN HIGH
ZOUT LOW 45
 VIN
 RE set AV  0.98 and AV  1
AV = VT  AV
gmVn
 RE + r VE =
R1//R2
rn VT VE 1 − AV
where r = and RE= 26m  0.98
IE IE VE =
VE 1 − 0.98

VOUT

AV = IE VE = 1.274V
VE VT
ZIN RE
 + VE = VOMAX = 1.274V
IE IE
VE
AV =
set IE  IC = 1.5mA
ZOUT
VE + VT
Gain calculation; Zin calculation where, VT thus as refer in datasheet the choosen  is;
VE = ;
ie =  ib move RE from base to emitter then; 1
−1  min =20,thus;
Zi = R1|| R 2 || (r +  RE ) AV
Vo Vi − Vo 
=
 r 
VT
RE VE =
1 − AV
 r  Zo calculation, where Vi s/c, then;
Vo   + = Vi AV
RE =
VE 1.274
= = 849.33
 RE  Zo =
r
|| RE VT  AV IE 1.5m
 VE =
Vo  1 − AV
= r r
Vi  + r Zo  ;since RE>>
RE  
Vo  RE
=
Vi r +  RE
46
 VR 2 = VRE + VBE IR1 = IB + IR 2
VR 2 = 1.274 + 0.7 IR1 = 75u + 0.75m
VR 2 = 1.974V
IR1 = 825uA

IC 1.5m
IB = = = 75uA VR1 = VCC − VR 2
 20
VR1 = 9 − 1.974
IC (mA) IR 2 = A  IB VR1 = 7.026V
A is multification factor, choose A = 10,thus;
ICSAT Note that Gap B << Gap A
IR 2 = 10  75uA VR1 7.026V
R1 = = = 8.52k 
AC&DC
LOAD LINE
IR 2 = 0.75mA IR1 825u

VR 2 1.974
Q-POINT R2 = = = 2.632k 
ICQ IR 2 0.75m

7.726V 9V
VCEQ VCE CUTOFF
VCE (V)
GAP A
1.274V
GAP B
47
Zin = R1 R 2 (r +  RE ); r =
  VT r
ZO = || RE
IE 
 20  26m  
Zin = 8.52k 2.632k   (
+ 20  849.33 ) where in the calculation the approximation
 1.5 m  
has been made, where;
Zin = 1.80k 
r r
ZO  ;since  RE
 
check;
r 346.67
= = 17.33
 20
RE = 849.33, thus;

r
ZO 

ZO  17.33

48
Simulate with actual value Simulate with E12 resistor value IE = 1.87mA
IE = 1.69mA MULTISIM SIMULATION VCE = 7.46V
VCE = 7.56V

49
Based on the actual and standard resistor value, the gain which produced by using Multisim EDA tool
shown slightly achieve the targeted value.

50
BJT-COMMON BASE DESIGN

Design Voltage Divider Bias BJT emitter stabilized which given speciation;

Transistor = 2N3019
ZIN ≤ 1k0Ω
ZO ≥ 10k0Ω
AV  150
VCC = +15V

51
2N3019 DC CURRENT GAIN (DATASHEET)

COMMON BASE
AV HIGH (SAME PHASE)
AI ≈1
AP MEDIUM
ZIN LOW
ZOUT HIGH
52
2N3019 DC CURRENT GAIN (SIMULATION)

53
 IC (mA)

1) Given AV  150@43.5dB then ICSAT

from AV equation;
AC&DC
  RC  LOAD LINE
AV = 
 r 
VT
where r = , thus; ICQ
Q-POINT
IE
ac parameter analysis for given circuit;
  15V
  RC  7.5V
VCE CUTOFF
VO  −  RC  VT AV =  
VCEQ
VCE (V)
AV = = ; r = VT
VIN  r  IE   GAP A
 IE 
GAP B
r r RC  IE
Zin = RE ;  RE AV = ; where VT = 26mV (3.9+3.5=7.5)V
  VT
r RC  IE For common base the DC&AC will overlap
Zin  150 =
 26m each other.
3.9 = RC  IE; where RC  IE = VRC
ZO  RC ; RC  RL VRC = 3.9V
set IE  IC = 0.12mA refer in the simulation
VRC 3.9
RC = = = 32.5k 
IE 0.12m

54
VRE = VCC − VRC − VCE
IR1 = IB + IR 2
VRE = 15 − 3.9 − 7.5
IR1 = 0.83u + 83u
VRE = 3.6V
IR1 = 83.83uA
VRE 3.6
RE = = = 30k 
IE 0.12m
VR1 = VCC − VR 2
VR 2 = VRE + VBE VR1 = 15 − 4.3
VR 2 = 3.6 + 0.7 VR1 = 10.7V
VR 2 = 4.3V
VR1 10.7
R1 = = = 127.64k 
By using  simulation,  = 144 IR1 83.83u
IC 0.12m
IB = = = 0.83uA r r
 144 Zin  ; where  RE
 
IR 2 = A  IB    26m  1
Zin    
A is multification factor, choose A = 100,thus;  0.12m  
IR 2 = 100  0.83u Zin  216.67
IR 2 = 83uA
ZO  RC
VR 2 4.3 ZO = 32.5k 
R2 = = = 51.81k  55
IR 2 83u
Simulate with actual value Simulate with E12 resistor value IE = 0.134mA
IE = 0.124mA MULTISIM SIMULATION VCE = 4.4V
VCE = 4.0V

56
57
FET AMPLIFIER DESIGN – SMALL SIGNAL DESIGN
➢DC AND AC CHARACTERISTIC
➢BIAS DESIGN and SMALL SIGNAL DESIGN

58
FET AMPLIFIER: DC AND AC CHARACTERISTIC
FET vs BJT

❑ FETs are voltage controlled devices where BJTs are current controlled devices
❑ FETs also have a higher input impedance, but BJTs have higher gain
❑ FETs are less sensitive to temperature variations and because their construction
they are more easily integrated on ICs.

59
 FET
JFET
D/E - MOSFET

N-Channel N-Channel
P-Channel P-Channel

60
JFET OPERATION
VGS = 0V and VDS less than “pinch off” voltage

The depletion region between p-gate and n-channel

increases as electrons from n-channel combine with
holes from p-gate. Increasing the depletion region,
decreases the size of the n-channel which increases
the resistance of the n-channel.
When VDS is applied into some positive voltage
value, the electron will be drawn to the drain
terminal, establishing the conventional current ID.

61
When a VDS voltage applied, current flow and the VGS from zero to some negative value and
channel react like a conventional resistor. When VDS VDS above “pinch off” voltage
increase toward “pinch-off” voltage the drain current
also increase and initially transistor working in the
“ohmic region”.
However as VDS increase, the depletion layer at the
gate junctions are also becoming thicker and
narrowing the N-type channel available for
conduction. Then come a point, know as “pinch-off”
where the conducting channel become narrow enough
to cancel out the effect of current increasing with the
applied voltage VDS which shown in figure.
Above the ohmic point, there is little further increase
in drain current and the transitor is said to operating
in "saturation mode“. With this effect, the JFET biased
in this way, a small change in VGS can be used to
control the current through the source−drain channel
from its maximum(saturated) value to zero current
62
JFET OUTPUT CHARACTERISTIC
As shown in figure, the drain current ID shows
very little change, and the curves are very
nearly horizontal at voltages greater than
the pinch off voltage. Almost all of the
expected increase in current, due to the
increase in voltage between Source and
Drain (VDS), is offset by the narrowing of the
conducting channel due to the growing
depletion layers.

63
JFET TRANSFER CHARACTERISTIC
The transfer characteristics defined by
Shockley’s equation are unaffected by the
network in which the device is employed

Schockley’s Equation

64
D-MOSFET OPERATION
The drain (D) and source (S) connect to the n-doped regions. These n-
doped regions are connected via an n-channel. This n-channel is
connected to the gate (G) via a thin insulating layer of SiO2. The n-
doped material lies on a p-doped substrate that may have an
additional terminal connection called substrate (SS).
The positive voltage applied on the gate and attracts more free
electrons into the conducing channel, while at the same time repelling
holes down into the P type substrate. The more positive the gate
potential, the deeper, and lower resistance is the channel. Increasing
positive bias therefore increases current flow. This useful
depletion/enhancement version has the disadvantage that, as the
gate area is increased, the gate capacitance is also larger than true
depletion types. This can present difficulties at higher frequencies.

65
D-MOSFET TRANSFER CHARACTERISTIC
Drain and transfer characteristic for an n-channel
depletion type MOSFET.

66
E-MOSFET OPERATION
The drain (D) and source (S) connect to the to n-doped regions. These n-
doped regions are connected via an n-channel. The gate (G) connects
to the p-doped substrate via a thin insulating layer of SiO2. There is no
physical channel. The n-doped material lies on a p-doped substrate
that may have an additional terminal connection called the substrate
(SS).

At VGS=0 V or VGS<VGS(TH)

ID = IS = 0, no current flow.

At VGS increate to some positive voltage value

▪ Positive potential of gate will pressure the holes in p-substrate
leaving behind electrons accumulated at the edge of SiO2.
▪ Electrons near the edge of SiO2 can’t absorbed to the metal and
gate because SiO2 as an insulator.

67
 At VGS > VTH
▪ Density of free electrons in the induce channel will increase.
▪ If VGS is constant and increase the level of VDS, the ID will reach
saturation
▪ Therefore, VD(sat) = VGS - VTH

68
E-MOSFET TRANSFER CHARACTERISTIC
Drain and transfer characteristic for an n-
channel depletion type E-MOSFET.

69
 FET AS VOLTAGE AMPLIFIER
To obtain output voltage as voltage amplifier, is by pass
output current (id) through output resistor (RD or Zout) and
take voltage across the resistor as the output.

Simple FET amplifier with The voltage transfer characteristic (VTC)

Input VGS and output VDS of the amplifier

70
VTC - FET
Biasing FET is to obtain linear amplification from FET transistor.
The VGS is selected to obtain operation at a Q point on
the segment AB of the VTC (as show on figure).

The best Q point or bias point is the middle of AB segment

71
The FET amplifier with a small time-varying
signal vgs(t) superimposed on the dc bias
voltage VGS.
The MOSFET operates on a short almost-linear
segment of the VTC around the bias point Q
and provides an output voltage;
VDS = AV(VGS)

72
 Determine VTC by Graphical Analysis
ID (mA)

It can be done by plotting ID vs VDS for both DC and AC load line

VO(MAX) ;
It can be determine when either between GAP A or GAP B which one is smallest gap.
IDSAT AC LOAD LINE Example;
If GAP A smallest gap, then VO(MAX) = (VDSQ – 0 )Vp
If GAP B smallest gap, then VO(MAX) = (VDS’ – VDSQ)Vp

Q-POINT
IDQ

DC LOAD LINE

VDSQ VDS VDS CUTOFF

VDS (V)
GAP A

GAP B

73
MULTISIM SIMULATION FET - VTC
R1
10kΩ
VDS VDS
20V
Q1
PN4416

VGS
5V

CLICK HERE FOR

MULTISIM SIMULATION

74
DETERMINE IDSS AND VP BASED ON SIMULATION

75
 Q1
PN4416 VDS

VGS

As refer in datasheet for;

VGS(off-max) = 6V at VDS=15V
and use these value for DC SWEEP
analysis

76
77
 Choosing method;

DETERMINE IDSS AND 1) typical value

2) max and min value, then calculate the average
VP BASED DATASHEET 3)if min value only then choose min value
4) if max value only then choose max value

As refer in datasheet (2n5484);

VGSOFF = VP;
VPMAX + VPMIN
VPAVG =
2

VPAVG =
( −3.0 ) + ( −0.3) = (−1.65V )
2

IDSS MAX + IDSS MIN

IDSS AVG =
2
5m + 1m
IDSS AVG = = 3mA
2
78
 The internal resistor of FET normally reach 500k, thus the
DETERMINE gate current reach at IG  0 A.

RESISTOR R1& R2 The current flow from resistor R1 and R2 is;

IR1 = IR 2 and R1+R2 >> 500k

Example;
set R1+R2  10M

R2
VR 2 =  VCC ;VR 2 = VG
R1 + R 2
VR 2  ( R1 + R 2)
R2 =
VCC

R1 = RT − R 2

79
FET-GENERAL RELATIONSHIPS DC PARAMTERS
For all FETs family; For E-MOSFET
IG  0 A I D = k (VGS − VT ) 2
ID  IS
where k ;
For JFET and D-MOSFET I D (ON )
k=
 V 
2
(VGS (ON ) − VT )2
I D = I DSS 1 − GS 
 VP 

80
FET-GENERAL RELATIONSHIPS AC PARAMTERS
The change in drain current that will result from a change in
gate-to-source voltage can be determined using the
transconductance factor “gm”

I D
gm =
VGS
The prefix trans - in the terminology applied to g m reveals that
it establishes a relationship between an output and an input
quantity.
The root word conductance was chosen because “gm” is
determined by a current-to-voltage ratio similar to the ratio that
defines the conductance of a resistor

81
From figure (as graphical method), the “gm” is actually the
slope of the characteristics at the point of operation

y ID
gm = m = =
x VGS

The mathematical approach the “gm” can be determined as below;

2 IDSS  VGS 
gm = 1 − Vp  Applicable for JFET and D-MOSFET
Vp  

gm = 2k (VGS(ON) − VTH )
where;
Applicable for E-MOSFET
I D (ON )
k=
(VGS (ON ) − VTH ) 2
82
Input impedance;
Zin = 

Output impedance;
1
Zout = rd =
yos
where yos is output admittance equivalentcircuit parameter which listed in FET datasheet

83
FET: BIAS SETUP
FIXED-BIAS SETUP
FET configurations that can be solved just
as directly using either a mathematical or
a graphical approach. Note that at
source, the resistor effect is neglected.

I G  0A
VRG = 0V
VGS = (−VGG ) Plotting Shockley’s equation Fixed-bias configuration to
determine Q-Point
84
SELF-BIAS SETUP
Self-bias configurations eliminated two(2)
dc supplies. The controlling gate-to-source
voltage is now determined by the voltage
across a resistor RS introduced in the
source leg of the configuration.

VRG = 0V
VGS = (− I D R S )

VDS = VDD − I D ( RS + RD )

Self-bias configuration to determine Effect of RS at different resistor value

Q-Point 85
VOLTAGE DIVIDER-BIAS SETUP
Voltage divider bias construction is same
with BJT construction but the dc analysis of
each is quite different.

R2
VG =  VDD
R1 + R2 Voltage divider-bias configuration Effect of RS on the resulting Q-Point
to determine Q-Point.
86
FET AMPLIFIER: CONFIGURATION
COMMON SOURCE COMMON DRAIN COMMON GATE
AV MEDIUM (180° ≈ 1 (SAME PHASE) HIGH (SAME PHASE)
DIFFERENT PHASE)
AI MEDIUM HIGH LOW
AP HIGH MEDIUM LOW
ZIN MEDIUM HIGH LOW
ZOUT MEDIUM LOW HIGH

87
FET-COMMON SOURCE DESIGN

Design Self-Bias FET common source with given speciation;

Transistor = 2N5556
ZO ≥ 1KΩ
ZIN ≥ 1MΩ
COMMON
AV ≥ 10dB@3.16
SOURCE
VCC = Between +10V to +20V
Vomax  2.5Vp AV MEDIUM (180°
DIFFERENT PHASE)
AI MEDIUM
AP HIGH
ZIN MEDIUM
ZOUT MEDIUM
88
2N5556 ELECTRICAL CHARACTERISTICS

IDSSmax = 0.5mA VGSoff = VP

IDSSmax = 2.5mA VP (min) = (−0.2V )

0.5mA + 2.5mA VP (max) = (−4V )

IDSS =
2 (−0.2) + (−4)
VP = = (−2.1V ) 89
IDSS = 1.5mA 2
 VIN VO AV = gmRD AV  Vp  VGS  VOMAX
= 1 − 
 VGS  2 IDSS  Vp    VGS  
2
2 IDSS  IDSS 1 − 
Where gm = 1- Vp  , thus;   VP  
Vp  
RG AV  Vp VOMAX
gmVgs rds RD =
2 IDSS   VGS  
 2 IDSS  VGS    IDSS 1 − VP  
AV =    
1 − Vp   RD
 Vp   AV  Vp VOMAX
=
AV  Vp  VGS  2  VGS 
ZIN ZO
= 1 − 1 − VP 
 RD
2 IDSS  Vp  VGS 2  VOMAX
Gain calculation; 1− =
VOMAX VP AV  Vp
gmVgs(rds RD)
Where RD = , thus;
AV = ID  2  VOMAX 
Vgs VGS = 1 −  VP
 AV  Vp 
AV = gm(rds RD)
AV  Vp  VGS  VOMAX
AV = gm( RD) since rds >> RD (ignore the rds effect) = 1 −
2 IDSS  Vp  ID
Input impedance;
Zin = RG
2
 VGS 
Where ID = IDSS 1-  ,thus;
Output impedance;  VP 
Zo = rds RD
Zo  RD since rds >> RD (ignore the rds effect)

90
 Determine ID where VGS = (-0.525V), thus;
 2  VOMAX   VGS 
2

VGS = 1 −  VP ID = IDSS 1 −
 AV  Vp   VP 
 −0.525 
2
 2  VOMAX  ID = 1.5m 1 −
Where  = 1 − −2.1 
 ID (mA)
AV  Vp  

ID = 0.84mA
VGS =   VP
VOMAX = VRD = 2.5V
set  = 0.25 where value of  cannot  1 Note that Gap B << Gap A
VGS = 0.25  VP VRD 2.5
RD = = = 2.98k 
ID 0.84m IDSAT AC LOAD LINE
VGS = 0.25  ( −2.1)
VGS = ( −0.525V )
VGS = (−0.525V )
determine how much gain required;
if VG  0V
Q-POINT
 2  VOMAX  VGS = VG − VS IDQ
 = 1 − 
 AV  Vp  VS = VG − VGS
 2  VOMAX  VS = 0 − (−0.525) DC LOAD LINE
0.25 = 1 − 
 AV  Vp  VS = 0.525V 11.98V 14.47V 15V
VDSQ VDS VDS CUTOFF
2  VOMAX Where VS = VLOSSES VDS (V)
AV =
1 −   Vp VRS = VLOSSES = 0.525V GAP A 2.5V
2  2.5 GAP B 0.535V
AV = VRS 0.525
RS = = = 625
1 − 0.25 2.1 ID 0.84m
LOSSESS

AV = 3.17 meet the specification

RG  10M 
ZIN = RG = 10M 
91
Simulate with actual value
ID = 1.06mA
ID = 1.02mA Simulate with standard value VDS = 10.91V
VDS = 11.35V MULTISIM SIMULATION

92
93
With same specification in self-bias, compute paramater
required for voltage divider bias;
VRS VS 5 ID (mA)
RS = = = = 5.95k 
ID = 0.84mA ID ID 0.84m
VGS = (−0.525V ) then;
VG = VR 2 = 4.475V

VOMAX = VRD = 2.5V Note that Gap B << Gap A

set R1+R2  15M IDSAT AC LOAD LINE
VRD 2.5
RD = = = 2.98k 
ID 0.84m VR 2  ( R1 + R 2)
R2 =
VDD
VGS = (−0.525V ) 4.475  (15M )
R2 = Q-POINT
Set VS = VOMAX  2 = 2.5  2 = 5V 15 IDQ
R 2 = 4.475M 
VGS = VG − VS
DC LOAD LINE
VG = VS + VGS R1 = 15M − R 2;( R1 + R 2 = 15M )
VG = 5 + (−0.525) R1 = 15M − 4.475M 7.5V 10V 15V
VDSQ VDS VDS CUTOFF
VG = 4.475V R1 = 10.525M VDS (V
GAP A 2.5V
ZIN = R1|| R 2 GAP B 5V
ZIN = 10.525M || 4.475M LOSSESS
ZIN = 3.14M 

ZO  RD
ZO  2.98k  94
Simulate with actual value ID = 0.8mA
Simulate with standard value VDS = 8.31V
ID = 0.8mA
VDS = 7.95V MULTISIM SIMULATION

95
96
FET-COMMON SOURCE DESIGN EXERCISE

Design self-bias FET common source with

given speciation;

Transistor = 2N5556
ZIN ≥ 10kΩ
ZO ≥ 10kΩ
AV ≥ 25dB
VCC = +20V
Vomax ≥ 2Vp
Modify self-bias into voltage divider bias and
compute all required parameters

97
FET-COMMON DRAIN DESIGN

Design voltage divider bias FET common drain with

given speciation;

Transistor = PN4416
ZIN ≥ 2MΩ
ZO ≤ 5kΩ
AV  1 COMMON DRAIN
VCC ≥ +20V
AV ≈ 1 (SAME PHASE)
AI HIGH
AP MEDIUM
ZIN HIGH
ZOUT LOW
105
PN4416 ELECTRICAL CHARACTERISTICS

IDSSmax = 15mA VGSoff = VP

VP = (−4.25V )
IDSSmax = 5mA
VP (min) = (−2.5V ) note that VGSoff is negative value for n-channel type
15mA + 5mA
IDSS = VP (max) = (−6V )
2
IDSS = 10mA (−2.5) + (−6)
VP =
2
106
 VIN VO io

R4 R3 VO
gmVgs1 RS
R1 R2
gmVgs rds RS

ZIN ZO
output impedance
input impedance set Vin → s/c and RS<<rds  RS
ZIN = R1 R 2 ZO =
VO
io
Gain calculation; VO
VO − io − gmVGS = 0
AV = RS
VIN  1 
VO io = VO  + gm 
− gmVGS = 0  RS 
RS
VO 1
VO =
− gm VO − VIN  = 0 io  1 
RS  RS + gm 
 1 
VO  + gm  = gmVIN VO 1
 RS  ZO = = RS
io gm
VO gm
= 1 1
VIN 1
+ gm ZO  ;  RS
RS gm gm
VO gm( RS )
=
VIN 1 + gm(RS) 107
 gm( RS )
AV =
1 + gm(RS)   2
AV (1 + gmRS ) = gmRS    VGS 
2  VS ID = IDSS 1 −
AV + ( AV  gmRS ) = gmRS Where  = 1 −  and  cannot  1, thus;  VP 
  AV   Vp 
 −2.125 
2
AV = gmRS (1 − AV )  1 − AV   ID = 10m 1 −
AV  −4.25 
gmRS =
1 − AV choose  = 0.5; ID = 2.5mA
VGS =   VP
2 IDSS  VGS  VGS = 0.5  −4.25
where gm = 1 − Vp  VS 20.19
Vp   RS = = = 8.08k 
2 VGS = ( −2.125V ) ID 2.5m
 VGS 
and ID = IDSS 1 − ,thus;
 VP 
Determine VS, where  = 0.5 and AV = 0.95, thus;
AV VS
= gm   
1 − AV ID  
2  VS
AV
=
2 IDSS  VGS 
1− 
VS  = 1 − 
1 − AV Vp  Vp   VGS 
2
  AV 
 Vp 
IDSS 1 −
 VP   1 − AV  
AV 2 VS AV
= 
1 − AV Vp  VGS  (1 −  )  Vp
1 − VP  VS = 1 − AV
2
AV 2  VS
= 0.95
1 − AV  VGS 
Vp  1 − (1 − 0.5)  4.25
 VP  VS = 1 − 0.95
    2
  2  VS   VS = 20.19V
VGS = 1 −    VP 
   AV   Vp   108
  1 − AV   
 
 ID (mA)
VDS = VCC − VS set R1+R2  20M
GAP B << GAP A VDS = 50 − 20.19
VR 2  ( R1 + R 2)
VDS = 29.81V R2 =
VDD
IDSAT
18.065  (20M )
R2 =
50
VGS = VG − VS R 2 = 7.226M 

Q-POINT VG = VGS + VS
IDQ R1 = 20M − R 2;( R1 + R 2 = 20M )
VG = −2.125 + 20.19
R1 = 20M − 7.226M
VG = 18.065V R1 = 12.774M 
DC&AC LOAD LINE
VG = VR 2 = 18.065V
50V
VDSQ VDS CUTOFF
VDS (V)
29.81V
GAP A 20.19V
GAP B

109
ZIN = R1 R 2
ZIN = 12.774M || 7.226M
ZIN = 4.62M 

1
ZO 
gm
where;
 VGS 
2 IDSS
gm = 1 − Vp 
Vp 
2 10m  −2.125 
gm = 1−
4.25  −4.25 
gm = 2.35mS

1
ZO 
gm
1
ZO 
2.35m
ZO  425.53 110
 MULTISIM SIMULATION
ID = 2.48mA ID = 2.46mA
VDS = 29.8V VDS = 29.8V

111
112
FET-COMMON GATE DESIGN

Design voltage divider bias FET common drain with

given speciation;

Transistor = E-MOSFET 2N6660

ZIN ≤ 500Ω
ZO ≥ 500Ω COMMON GATE
AV ≥ 10
AV HIGH (SAME PHASE)
AI LOW
AP LOW
ZIN LOW
ZOUT HIGH
113
2N6660 ELECTRICAL CHARACTERISTICS

Choose;
VTH = 1.5V (typ)

To determine k choose;
IDON = 1.7 A at VGSON = 10V
if the datasheet is not given the IDON ,
then only choose VDSON row, then
choose the given of IDON & VGSON 114
 AV = gmRD
given that;
ID = k (VGS − VTH ) 2
IDON
k=
(VGSON − VTH ) 2
gm = 2k (VGS − VTH )
then;

VIN VO VO AV = gmRD
ZIN = ZO = where vin is s/c AV =
in in VIN AV = 2k (VGS − VTH ) RD
VRD
and RD = , then;
VIN ID
−in + − gmVgs = 0 −io +
VO
+ gmVgs = 0 VO
RS RD + gmVgs = 0 AV = 2k (VGS − VTH ) RD 
VRD
VIN RD ID
in = − gm(Vg − Vs ) VO
io = + gm(Vg − Vs ) VO
RS
RD = − gm(Vg − Vs ) AV = 2k (VGS − VTH ) RD 
VRD
in =
VIN
− gm(0 − VIN )
RD  k (VGS − VTH ) 2 
VO
RS io = + gm(Vg − VIN ) VO
RD = − gm(0 − VIN ) 2  VRD
VIN 1 AV =
= RS || VO RD (VGS − VTH )
in gm io = + gm(0 − 0) VO
RD = gmRD  2  VRD 
1 VGS = VTH +  
ZIN = RS || VO VIN  AV 
gm = RD
io
1 1
ZIN  ; RS  115
gm gm
Set AV = 20@26.02dB and VRD = 6V ; VRD ID (mA)
RD =
 2  VRD  ID
VGS = VTH +  
 AV  6
RD =
 2 6  8.47m
VGS = 1.5 +  
 20  RD = 708.38
VGS = 2.1V (VGS >> VTH;statisfy) IDSAT

Set VRS = 3V, then; GAP B << GAP A

ID = k (VGS − VTH ) 2

VRS
IDON RS =
k= ID
(VGSON − VTH ) 2 Q-POINT
3 IDQ
k=
1.7 RS =
(10 − 1.5) 2 8.47m
A RS = 354.19 DC&AC LOAD LINE
k = 23.53m 2
V
20V
VDSQ VDS CUTOFF
ID = k (VGS − VTH ) 2 VDS (V)
11V
ID = 23.53m(2.1 − 1.5) 2
GAP A (6+3=9)V
ID = 8.47mA GAP B

116
VGS = VG − VS 1
ZIN  ,where;
VG = VGS + VS gm
VG = 2.1 + 3 gm = 2k (VGS − VTH )
VG = 5.1V gm = 2(23.53m)(2.1 − 1.5)
VG = VR 2 = 5.1V gm = 28.24mS

set R1+R2  20M 1

ZIN 
5.1 ( R1 + R 2) gm
R2 =
VDD 1
ZIN 
5.1 (20M ) 28.24m
R2 =
20 ZIN  35.41
R 2 = 5.1M 
ZO = RD
R1 = 20M − R 2;( R1 + R 2 = 20M ) ZO = 708.38
R1 = 20M − 5.1M
R1 = 14.9M 

117
 MULTISIM SIMULATION
ID = 8.41mA
ID = 8.75mA VDS = 11.52V
VDS = 10.7V

118
119
SIMPLE MULTISTAGE AMPLIFIER DESIGN
❑ Multistage amplifier consists of two or more amplifiers
cascode to form a single amplifier with the desired
characteristic.
❑ In discrete form it could be BJT‐BJT, BiFET, FETFET or some
other combinations.
❑ In IC design it’s always be a combinations of single type of
transistors.

120
AVT = AV1  AV2  AV3  AVn
AVT = 5 10  6  8
AVT = 2400
Then;
VO = AVT  VIN
VO = 2400  5mV
VO = 12V

121
Purposes of multistage
❑ Increasing the gain beyond the single stage amplifier gain.
❑ Modifying the impedance parameter.
Type of Multistage Amplifier
❑ BJT‐BJT cascode for pre-amplifiers.
❑ BiFET cascode for a good linear amplifier.

122
Coupling
❑ Purpose : The circuitry used to connect the output of one
stage to the input of the next stage in multistage amplifier.
Types of coupling
❑ Capacitive coupling/RC coupling
✓ Adv ‐ to block the flow of dc current
✓ Disadv – It affects the lower frequency response of the
amplifier
123
❑ Direct coupling
✓ Adv ‐ to reduction in the number of components
❑ Transformer coupling
✓ Adv ‐ low power dissipation
✓ Disadv - poor frequency response characteristics

124
CASCODE CONNECTION
❑ Cascade connections provides stages in series which is a
popular connection.
❑ The output of one amplifier stage is connected to the input
of another amplifier stages.
❑ There are 2 types;
✓ BJT & BJT
✓ BiFET

125
 CASCODE-BJT&BJT DESIGN

Design cascade BJT&BJT with

given speciation;

Transistor Q1 = 2N2222A
Transistor Q2 = BC107B
ZIN ≥ 1kΩ
ZO ≤ 1kΩ
AV = 500 – 2000
Vomax = 0.5Vp – 2.5Vp
VCC = +10V

126
 VIN VOUT

R11//R12 gmVn2
RC1 R21//R22 rn2 RC1
rn1 gmVn1

ZIN ZOUT

To determine gain distribution for each stage, the AV1

stage must be set to minima gain in order to archieve
−  2 ( RC 2 RL ) −  2  ( RC 2 || RL) the lowest RC1 value.
AV 2 = AV 2 =
r 2 r 2
Set RC2<<RL,  RC2, thus; −  2  RC 2 VOMAX
AV 2 = , where RC 2  RL AV 1 = AV 2 = ; set VO1MAX = 0.5 for AV1
−  2  RC 2 r 2 VT
AV 2 = , then; 0.5
r 2 AV 1 = = 19.23
ZIN = R11 R12 r 1 26m

−  1( RC1 R 21 R 22 r 2) AVT = AV 1 AV 2
AV 1 = ZO = RC 2
r 1 AVT
Set RC1<< R 21 R 22 r 2,  RC1, thus; AV 2 = ;Set AVT = 1000@60dB
AV 1
−  1 RC1 1000
AV 1 = AV 2 = = 52 and
r 1 19.23
VO 2MAX = AV 2  VT
VO 2MAX = 52  26m
VO 2MAX = 1.352V for AV2 127
BC107A DC CURRENT GAIN(β)

128
 IC (mA)

As refer in datasheet(BC107B), IC = 2mA and  = 290( set RL = 100k )

VO 2MAX VRC 2 1.352
RC 2 = = = = 676
IC 2 IC 2 2m
ICSAT AC LOAD LINE
VRE 2 = VLOSSES = 3.648V
VRE 3.648
RE 2 = = = 1.82k 
IC 2 2m
Q-POINT
ICQ IC 2 2m
IB 2 = = = 6.90uA
 2 290
DC LOAD LINE
IR 22 = A  IB 2
IR12 = IR 22 + IB
5V 10V A is multification factor, choose A = 50,thus;
VCEQ VCE 6.352V VCE CUTOFF IR12 = 345u + 6.90u
VCE (V) IR 22 = 50  6.90u
IR12 = 351.9uA
GAP A IR 22 = 345uA
1.352V
3.648V VR12 = VCC − VR 22
GAP B VR 22 = VRE 2 + VBE 2
LOSSES
VR 22 = 3.648 + 0.7 VR12 = 10 − 4.348
VR 22 = 4.348V VR12 = 5.652V
VR 22 4.348 VR12 5.652
R 22 = = = 12.60k  R12 = = = 16.06k 
IR 22 345u IR12 351.9u

129
2N2222A DC CURRENT GAIN(β)

130
 As refer in datasheet(2N2222A), IC = 10mA and  = 100
VO1MAX VRC1 0.5
RC1 = = = = 50
IC1 IC1 10m

VRE = VLOSSES = 4.5V

VRE1 4.5
RE1 = = = 450
IC (mA) IC1 10m

IC1 10m
IB1 = = = 100uA
 1 100
ICSAT AC LOAD LINE
IR11 = IR 21 + IB
IR 21 = A  IB1
IR11 = 5m + 100u
A is multification factor, choose A = 50,thus;
IR 21 = 50 100u IR11 = 5.1mA
Q-POINT
ICQ IR 21 = 5mA
VR11 = VCC − VR 21
DC LOAD LINE VR 21 = VRE1 + VBE1 VR11 = 10 − 5.2
5V 10V VR 21 = 4.5 + 0.7 VR11 = 4.8V
VCEQ VCE 5.5V VCE CUTOFF
VCE (V) VR 21 = 5.2V VR11 4.8
GAP A R11 = = = 941.18
VR 21 5.2 IR11 5.1m
0.5V R 21 = = = 1.04k 
4.5V IR 21 5m
GAP B
LOSSES
131
ACTUAL VALUE

132
STANDARD VALUE

133
134
 CASCODE-BJT&FET (BIFET) DESIGN

Design cascade BJT&FET with

given speciation;

Transistor Q1 = 2N4400
Transistor Q2 = JN310
ZIN ≥ 5kΩ
ZO ≥ 1kΩ
AV = 1000 – 5,000
VCC = Choose correct power supply

135
AV 2 = gm( RD) To determine gain distribution for each stage, the AV1
stage must be set to minima gain in order to archieve
−  1( RC R 21 R 22) the lowest RC value.
AV 1 =
r
Set RC1<< R 21 R 22  RC , thus; AV 1 =
VOMAX
;set VO1MAX = 0.65 for AV1
VT
−  1 RC
AV 1 = 0.65
r AV 1 = = 25
26m

ZO = RD AVT = AV 1 AV 2
AVT
AV 2 = ; Set AVT = 1,000@60dB
ZIN = R11|| R 21|| r AV 1
1000
AV 2 = = 40
25
136
JN310 DATASHEET

IDSS = 42mA
VP = (−4.25)
137
  2  VOMAX  VOMAX = VRD = 17V VG = VR 2 = 1.6VE;Set voltage source = 45V
VGS = 1 −  VP
 AV 2  Vp  VRD 17
RD = = = 10.12k  set R12+R22  15M
 2  VOMAX  ID 1.68m
Where  = 1 − 
 AV 2  Vp  VGS = (−3.4V ) R 22 =
VR 22  ( R12 + R 22)
VGS =   VP VDD
VGS = VG − VS 1.6  (15M )
set  = 0.25 where value of  cannot  1 R 22 =
VG = VGS + VS ;VS = VLOSSES  VGS 45
VGS = 0.80  VP R 22 = 533.33k 
VG = (−3.4) + 5
VGS = 0.80  ( −4.25 )
VG = 1.6V
VGS = ( −3.4V ) R12 = 15M − R 22;( R12 + R 22 = 15M )
R12 = 15M − 533.33k
determine how much VOMAX required;
VRS = VLOSSES = 5V R12 = 14.47 M 
 2  VOMAX 
 = 1 −  RS =
VRS
=
5
= 2.98k 
ID (mA)

 AV 2  Vp  ID 1.68m ZO  RD
(1 −  )  ( AV 2  Vp ) ZO  10.12k 
VOMAX =
2
(1 − 0.8)  ( 40  4.25 )
IDSAT AC LOAD LINE Note that Gap B << Gap A
VOMAX =
2
VOMAX = 17V
Q-POINT
IDQ

Determine ID where VGS = (-0.525V), thus;

2 DC LOAD LINE
 VGS 
ID = IDSS 1 −
 VP  23V 40V
VDS
45V
VDSQ VDS CUTOFF
VDS (V)
−3.4 
2

ID = 42m 1 − GAP A 17V
 −4.25  GAP B 5V
ID = 1.68mA LOSSESS
138
2N4400 DC CURRENT GAIN(β)

139
 IC (mA)
As refer in datasheet(2N4400), IC = 1mA and  = 20
VOMAX VRC 0.65
RC = = = = 650
IC IC 1m

VRE = VLOSSES = 15.35V

ICSAT AC LOAD LINE
VRE 15.35
RE = = = 15.35k 
IC 1m

IC 1m
Q-POINT IB = = = 50uA
ICQ  20

IR 22 = A  IB 2
DC LOAD LINE IR11 = IR 22 + IB
A is multification factor, choose A = 50,thus;
IR11 = 2.5m + 50u
29V 45V IR 22 = 50  50u
VCEQ VCE 29.65V VCE CUTOFF IR11 = 2.55mA
VCE (V) IR 22 = 2.5mA
GAP A
0.5V VR 21 = VRE + VBE VR11 = VCC − VR 22
15.35V
GAP B VR 21 = 15.35 + 0.7 VR11 = 45 − 16.05
LOSSES
VR 21 = 16.05V VR11 = 28.95V
VR 21 16.05 VR11 28.95
R 22 = = = 6.42k  R11 = = = 11.35k 
IR 21 2.5m IR11 2.55m

140
 141
ACTUAL VALUE
STANDARD VALUE

142
143