CAD for VLSI Design - I

Lecture 37
V. Kamakoti and Shankar Balachandran

1
Overview
• New Paradigms in Computing
– Reconfigurability
• Field Programmable Gate Arrays
– Their role in modern computing arena
– Generic FPGA architecture

2
Paradigms in Computing
ISP or μP based execution

Flexibility Power

Cost Custom hardware

Performance
Fault Tolerance

Test Reliability

3
Temporal Execution on ISP
• Load
• Control
– Decode
• Execute
• Load/Store
Instr1 Load/Decode
C
o
• Enabled language and Instr2 n
compiler technology. t
Instr3 Execute Φ
• Supports upward r
compatiblity o
Instr4 l
– sort of forces a
contract Load/Store
Instr5
• Re-use of static hardware
resources.

4
Spatial Execution on Hardware
• No Control.
• Computing is through communication on
interconnected logic.

Custom
Load/Store
Expensive Logic I/C
(Data)
High Performance

5
Reconfigurable Computers

RSP Domain

ISP Like Hardware Domain

Instr1
Instr2
Load/Store
Instr3 Configuration Logic I/C
(Data)
Instr4
Instr5

6
ISP based computing: Cons
• Performance
– temporal execution not the best idea.
– Mold application to hardware
• actually it should be mold hardware to application.
• Financial
– design time and development cost
– design challenges
– yield and process
– complexity and verification
– test cost

7
Design Methodologies

Design Methodologies

Full Custom Semi-Custom

Standard Cell Gate Arrays Programmable

PLDs FPGAs

Our Focus

8
Programmable Devices
• Pre-fabricated silicon.
• Logic implemented by programming the
interconnects and basic cells.
• Very fast turnaround time.
• Good design flexibility.
• Low development time and cost.

9
 Programmable Logic Device (PLD)
• PLDs with AND/OR logic structure:
• PAL: Programmable AND array, Fixed OR array.
• ROM: Fixed AND array, Programmable OR array.
• PLA: Programmable AND array, Programmable OR array.
• Product lines can be any input combination and flip-flops can be fed back to
input.
• Programmable element can be fuse or a transistor.
• Densities range from 1,000 to 10,000 gates.

10
 Field-Programmable Gate
•Arrays (FPGAs)
A successful marriage of PLDs and MPGAs
• Densities range from 2K to 10,000K+ gates.
• Array of Logic blocks and programmable interconnect.
• Logic block made of universal gates, multiplexers, RAMs, NAND gates,
transistors etc.
• Programmable element made of
– SRAM,
• SRAM bits can be programmed many times.
• High area overhead – five transistor pass transistor based SRAM cell.
– EEPROM, or
• Frequently used for PALs and EPLDs
• Low area overhead – only one transistor per programming point.
– Antifuse.
• One time programmable, high performance
• Low area overhead.

11
Why FPGAs
• Glue logic (replace SSI and MSI parts)
– This is where it all started for FPGAs.
• Rapid turnaround and Low risk
• Emulation
• Custom and super computing
• Dynamically changing hardware

12
Changing Dynamics

13
Time to Market is Critical

14
Cost Structuring

15
FPGAs versus ASIC

16
Field Programmable Gate Array

I/O Block

Configurable
Logic Block

Programmable
Horizontal Wiring
Switches
Channel

Vertical Wiring
Channel
17
A Generic FPGA

Switchbox
FS = 3

Connection box
FC = 3

18
Questions and Answers

Thank You

19