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CAD VLSI Lab2 PDF
CAD VLSI Lab2 PDF
Homework #2
The module interfaces for a few circuits are described below. Use appropriate Verilog design style to
model these circuits. For all these designs, indicate the nature of the circuit that is implied from your
Verilog code. Draw figures if necessary.
Problems:
1. A parity generator circuit takes 8 bit data as input and gives one output. If there is odd number of
ones in the input, the circuit drives a 1 in the output and it drives 0 otherwise. Model the circuit in
Verilog. The module interface is provided below for consistency across the class.
2. Design a 2:1 multiplexer using Verilog. Use these multiplexers and design a 4:1 multiplexer. Module
interface is shown below.
3. Design a circuit in Verilog that takes a 4 bit number and which counts the number of one’s in the
input. Circuit must have the following interface:
4. Design a binary comparator that compares two 5-bit unsigned numbers a and b and generates the
following code : 00 if both are equal, 01 if a < b and 10 if a > b.