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ADVANCED LEVEL DIGITAL ELECTRONICS
07-2011
YILDIRIM ELECTRONICS
DİJİTAL ELEKTRONİK–2 1
CONTENTS PAGE
CONTENTS 2
INTRODUCTION OF DIGITAL ELECTRONIC SET 4
USING OF THE CIRCUITS IN THE DIGITAL ELECTRONIC TRAINING SET 5
GENERAL INFORMATION 6
TEST NAME SCHMITT-TRIGGER gates (Preliminary information) 13
TEST NO-1: The examination of SCHMITT-TRIGGER gate 15
TEST NAME: The examination of ASYNCHRONOUS counters 17
TEST NO-2: The examination of Up ASYNCHRONOUS counters made of JK FFs 20
TEST NO-3: The examination of Down ASYNCHRONOUS counters made of JK FFs 23
TEST NO-4: The determination of the counting range of ASYNCHRONOUS counter 25
TEST NAME: The examination of SYNCHRONOUS counters made of JK FFs 27
TEST NO-5: The examination of Up SYNCHRONOUS counters made of JK FFs 29
TEST NO-6: The examination of Down SYNCHRONOUS counters made of JK FFs 31
TEST NO-7: The changing of the counting limit of SYNCHRONOUS counter 33
TEST NAME: BINARY COUNTER preliminary information 35
TEST NO-8: The examination of 4024 Counter Integrated 36
TEST NAME: 4520 BINARY COUNTER (preliminary information) 39
TEST NO-9: The using of 4520 Integrated as the counter 40
TEST NO-10: The using of 4520 Integrated as 3 Bit Counter. 42
TEST NO-11: The using of 4520 as BCD Counter 44
TEST NAME: BCD Counters (Preliminary information) 46
TEST NO-12: UP/DOWN BCD Counter 48
TEST NO-13: The working of BCD Counter by programming. 50
TEST NAME: The examination of DECADE- JOHNSON COUNTER INTEGRATED
52
preliminary information.
TEST NO-14: The test of examination of DECADE- JOHNSON COUNTER INTEGRATED 53
TEST NAME: The examination of 8 To 3 Encoder 55
TEST NO-15: The examination of 8 To 3 Encoder 56
TEST NAME: The examination of DECIMAL TO BCD ENCODER 58
TEST NO-16: DECIMAL TO BCD ENCODER 59
DECODERS (Preliminary Information) 61
TEST NAME: 3 TO 8 DECODER 62
TEST NO-17: 3 TO 8 DECODER Test 63
TEST NAME: BCD TO DECIMAL DECODER 65
TEST NO-18: BCD TO DECIMAL DECODER Test 66
TEST NAME: 7 SEGMENT DISPLAY 68
TEST NO-19: COMMON ANODE 7 SEGMENT DISPLAY TEST 71
TEST NO-20: COMMON CATHODE 7 SEGMENT DISPLAY TEST 73
CONTENTS PAGE
TEST NAME: BCD TO 7 SEGMENT DISPLAY DECODER TEST 75
TEST NO- 21: BCD TO 7 SEGMENT DISPLAY COMMON DECODER TEST 76
TEST NO-22: HEXADECIMAL TO 7 SEGMENT DISPLAY DECODER TEST 78
TEST NAME: The examination of Multiplexer (MUX.) circuits (preliminary information) 80
TEST NO-23: The examination of 4051 Multiplexer (MUX.) integrated 82
TEST NAME: The examination of 8-Bıt DEMULTIPLEX (DEMUX) circuit 84
TEST NO-24: The using of 4051 integrated as Demultiplexer 85
TEST NAME: The examination of serial data communication (preliminary information) 87
TEST NO-25: The examination of serial data communication 88
TEST NAME: The examination of full adder 90
TEST NO-26: The Full Adder Examination Test 92
TEST NO-27: The using of 4008 as one-digit adder with MODE selection and one-digit
94
subtracter
TEST NAME: COMPARATOR circuits (preliminary information) 96
TEST NO-28: COMPARATOR circuits tests 98
TEST NAME: UNIVERSAL SHIFT REGISTER 100
TEST NO-29: TO THE RIGHT SHIFT REGISTER test 103
TEST NO-30: TO THE LEFT SHIFT REGISTER test 105
TEST NO-31: PARALLEL INPUT-PARALLEL OUTPUT SHIFT REGISTER test 107
TEST NAME: RANDOM ACCESS MEMORIES 109
TEST NO-32: 6116 RAM integrated examination test 112
TEST NAME: The examination of Analogue- Digital convertor (ADC) 116
TEST NO-33: ADC 0804 Analogue -Digital convertor (ADC) examination Test 120
TEST NAME: The examination of Digital-Analogue convertor (DAC) 122
TEST NO-34: The examination of AD 558 Digital-Analogue convertor (DAC) 124
TEST NAME: The examination of 555 Integrated timer integrated 127
TEST NAME: The examination of the working of 555 timer as ASTABLE multivibrator
128
(Preliminary Information)
TEST NO-35: The test of the examination of the working of 555 timer as ASTABLE
129
multivibrator
TEST NAME: The working of 555 as MONOSTABLE multivibrator 130
TEST NO-36: The test of the 555 as MONOSTABLE multivibrator 131
TEST NAME: The working of 555 as BISTABLE multivibrator 132
TEST NO-37: The test of the examination of the working of 555 as BISTABLE
133
Multivibrator
INTRODUCTION OF DIGITAL ELECTRONIC SET
11 10 9
1 6
2 7
3
8
1. Power ON/OFF,
2. DC +5V power supply,
3. 12 BIT LOGIC LED indicating Switch group,
4. PULSE Switch Circuit,
5. 2 Phase 1Hz-1KHz Oscillator,
6. 12 BIT HIGH Level LED Indicator Circuit,
7. 12 BIT LOW Level LED Indicator Circuit,
8. ADVANCED LEVEL Digital Circuits.
9. 2x4 BIT HEXADECIMAL Decoder Display
10. 5x7 DOT MATRIX Display
11. BREADBOARD for External Applications
THE USING OF THE CIRCUITS IN THE DIGITAL ELECTRONIC TRAINING
SET
1- POWER ON-OFF SWITCH:

It is used to energize the circuit. The ON is open position and the OFF is closed
position. It controls +5V. The lamp on it shows the connection state.
2- DC +5V POWER SUPPLY:

It is for the use of external +5Volt. It is designed in the way that it can give max. 1A.
It is short-circuit protected.
3- 12 BIT LOGIC LED INDICATING SWITCH GROUP:

It is used to obtain the logic ‘0’ and ‘1’ information. 12 switches have been used for 12
bit information. LED indicating lamp has been used for switch positions and output
information.
4- PULSE SWITCH CIRCUIT:

It is used to obtain logic PULSE. In each pressing to the switch both positive PULSE and
negative PULSE can be obtained. The PULSES can be received from the desired output
terminal.
5- 2 PHASE 1Hz-1KHz SQUARE WAVE OSCILLATOR:

High and low frequency phase and frequency regulated clock pulse unit, made of 555
Integrated. It produces pulse between 1Hz and 35Hz in the LOW side of the switch and
between 32Hz and 1Khz in the HIGH side.
6- 12 BIT HIGH LEVEL LED INDICATOR CIRCUIT:

It is good to show the binary information, coming from the digital circuits, through 12
LED lamps. LED is on when the information is in “1” position. In “0” position it is off. It
works according to the positive logic principle. Because it is 12 pieces, it can show 12
BIT information.
7- 12 BIT LOW LEVEL LED INDICATOR CIRCUIT:

It is good to show the binary information, coming from the digital circuits, through 12
LED lamps. LED is on when the information is in “0” position. In “1” position it is off. It
works according to the negative logic principle. Because it is 12 pieces, it can show 12
BIT information.
8- ADVANCED LEVEL DIGITAL CIRCUITS:

It is the section that the Advanced Level Digital tests take place.
Here there are various special circuits in the case that the supply voltage are given.
9- 2x4 BIT HEXADECIMAL DECODER DISPLAY:

It shows the Coded Digital information as Hexadecimal in 2x4 bit two Display.
10- 5x7 DOT MATRIX DISPLAY:

Dot matrix display. For marquee and similar applications.
11- BREADBOARD FOR EXTERNAL APPLICATIONS:

BREADBOARD for the application of the circuits that does not take place in the set.
GENERAL INFORMATION
INTEGRATED CIRCUITS
The integrated circuits arise from a lot of systems that get together and
integrate.
The integrated is a semi conductor crystal, called chip, and contains the circuit
components such as transistor, resistance, condenser and diode that are used in the
electronical circuits. These components generates a circuit by connecting to each other
in the chip. The counterforts (pins) are taken out from the proper points of this circuit
generated. Then the chip is covered with a metal or plastic sheath and protected
against the external factors. Therefore an integrated is obtained.
The sizes and at the same time costs of this obtained integrated decrease
considerably. The integrated circuits have a very important place by the development of
today's technology. The decrease of the costs and sizes of the integrateds day by day
and having very high working speeds have increased the usage area in the industry.
The integrateds are symbolized shortly with IC letters, the initials of Integrated
Circuit. ICs have generally standard packages and their counterfort numbers, taken
out, varies between 8 and 400. There are numeric codes on all integrated (IC)
packages. Through these codes we can learn the type of integrated and the
specifications of the circuit in it. The integrated circuits are generally classed in two
categories.
These are Logic integrateds and lineer integrateds:
Lineer integrateds: Are used generally in processes such as voltage rising,

straightening... etc. ( for example op-amps )
Logic integrateds: Are composed of gate circuits. (digital integrateds)
The logic integrateds are used today in the digital (1–0) circuits. Because of the
low cost and incapacious specification of the integrateds they are used widely in the
electronics industry. Some of these circuits are these; Power amplifiers, counters,
arithmetic units, voltage regulators, radio and TV circuits, operational amplifiers... etc.
They are used in a lot of electronic circuit.
The integrateds are also classified according to their structures. They are divided
into three groups according to their external sheathes as metal, plastic and ceramic.
However the ceramic cased integrateds are brittle and expensive. So they are not used
today.
When the integrateds are destroyed, they are generally not repaired. The
destroyed integrated is removed and a new one is installed. The standard sockets are
manufactured for the purpose that this type processes can be made more practically.
The integrateds in some circuits are installed on the sockets. Therefore the demounting
and mounting processes will be more practical.
The logic integrateds are also classified according to the gate numbers included
in.
These are;
SSI (Small Sized Integrated) : It includes in logic gate between 1 and 20. For
example, in 7400 model integrated there are 4 nand gates.
MSI (Medium Sized Integrated) : It includes in logic gate between 20 and
100. For example, flip-flops, counters.
LSI (Large Sized Integrated) : It includes in logic gate between 100 and
10000. For example 4 and 8 bit microprocessors.
VLSI (Very Large Sized Integrated) : It includes in more than 10000 logic
gates. For example, 16-32 bit microprocessors, memory circuits, computer circuits.
Today, the integrated chips, included in more than 200 thousand logic gate, can
be made. There are minimum 2 transistors in each logic gate. In this case we can say
that hundreds of thousands transistors can be generated in a logic integrated. For
example, Pentium microprocessor includes in 5,5 million transistors. The integrateds in
various types are seen in the following pictures.
Figure.1
Integrated Circuit Parameters
There are some important specifications to compare digital integrated circuit

groups to each other and to select the optimum group for the definite application.
These are called as integrated parameters. The most important ones of these
parameters are;
1. Power supply voltage:

It determines the power supply voltage of the integrated. In some integrateds
the tolerance of the power supply voltage can also be determined.
2. Propagation delay:
It shows the change rate of the output in terms of nano second according to the
information given to the input of a logic circuit. A logic gate does not respond
immediately to the change, occuring in its input, in other words there is a time
delay. This delay is called propagation delay. It is 5nsec for TTL. In places such as
PLC, computer etc. the circuits, of which propagation speed is maximum, are
preferred.
3. Power dissipation:
It shows the power quantity that the circuit has dissipated. The power shaft
dissipated is in terms of watt. It changes in direct proportion to the working speed of
the circuit. (The ICs, dissipating minimum power in battery powered circuits, are
preferred.)
4. Output Capacitance (Fan out):

It determines the maximum load quantity to be connected to the output of the
circuit. The value of the output capacitance determines the number of gate to be
connected to the output of the logic gate.
5. Noise Immunity:
The noise quantity determines the error rate of the information in the circuit
output. In other words the situation such as 1 valued signal or 0 valued signal on
output or simulation as reverse of this. How low the noise quantity (in terms of
millivolt) is, more accurate the output information is. The ability of the gate to
suppress the noise is called noise tip of their gate.
6. Pulse frequency (Clock frequency):

It determines the frequency of the trigger pulse to be applied to digital circuit
input in terms of Hz.
The main circuit in each integrated is the NAND or NOR gate. The logic integrated
receives its name from the electronic material used in the manufacturing of the gate
circuits. Some integrated types that are used today are these;
1. RTL - Resistance - Transistor Logic

2. DTL - Diode Transistor logic
3. HTL - High Level Logic
4. TTL -Transistor - Transistor logic
5. ECL - Emitter - Coupling logic
6. DCTL - Direct - Coupling Transistor logic
7. MOS - Metal- Oxide semi conductor logic
8. CMOS - Complement - Metal semi conductor
Logic Family Types of the Integrated Circuits:
Resistance transistor logic (RTL): RTL type integrateds are the commercial
type integrateds manufactured firstly. The integrated circuits are the method used
mostly because they are cheap at first. The working voltage of RTL type integrateds are
between 3V and 3.6V. The propagation delay is approximately 12nsec, the power
dissipations are 10mwatt per gate. They are coded with 700 and 900s numbers.
Diode transistor logic (DTL): The using of the diode transistor logic is limited
in the integrated due to its limitations. There is internal voltage decrease even if just a
bit in diodes. And this leads to a decrease in the logic level. At the same time no event
to make negative performs in the circuit.
To remove these limitations an amplifier that makes negative is used. The
negative process is provided as well as the voltage decreases are compensated and it
keeps the logic level within a definite tolerance. They are the integrateds that removes
slowly. This type of integrateds is better than RTL type integrateds in terms of speed,
power and determination.
The working voltages of DTL type integrateds are about 5V. The noise immunity is
low. They are coded with 830 and 930s numbers.
Transistor Transistor Logic (TTL):
TTL integrateds are the developed kind of DTL type integrateds. A multi emitter
input transistor takes place of the input diodes in DTL integrateds. Because of this, the
TTL integrateds works very fast and because of their high speeds they are used
commonly. It is the integrated group used today most commonly. Their usage area is
the computers.
TTL integrateds are divided into 5 subgroups:
1. Standard TTL: It is the first kind of TTL group. The power dissipation per
gate is 10mw, the propagation delay is 10 nsec, the propagation speed is 35
MHz.
2. Low-Power TTL: The power dissipation per gate is 1mw, the propagation
delay is 33 nsec, the propagation speed is 3MHz.
3. High-Speed TTL: The power dissipation per gate is 22mw, the propagation
delay is 6 nsec, the propagation speed is 50MHz.
4. Schottky TTL(STTL): It is the fastest working of TTL group. The power
dissipation per gate is 19mw, the propagation delay is 3 nsec, the
propagation speed is 125MHz.
5. Low-Power schottky TTL (LSTTL): It is the newest developed model of
TTL group. The power dissipation per gate is 2mw , the propagation delay is
20nsec , the propagation speed is 35MHz.
Figure.2
TTL group is coded with 7400 and 5400s numbers. The most used one is 7400s
integrateds. 5400 series is military designed. 7400 series shows the integrated groups
working between 0°C and 70°C. 5400 series works between -55°C and +125°C. The
letters, coming from the numbers 74 and 54, indicates to which sub group a TTL
integrated belongs. For example, 74L00 belongs to low-powered TTL group or 7400
standard TTL...
Emitter Coupling Logic (ECL):
ECL family is not as common as TTL family. They have the highest speed. In
1962 it is started to fabricate by Motorola company. It is more expensive than TTL and
it is cooled harder. It is difficult to make interconnection and it is claimed that its noise
immunity is less. Because ECL gate is necessary in a lot of applications, it can be faster.
On the other hand, super fast computers and very fast special-purpose computers use
ECL. ECL integrated has developed instantly until today.
Figure.3
There are 4 main ECL subgroups.
1- MECL 1 Group: The propagation delay per gate is 8nsec, the propagation
speed is 30MHz and the power dissipation per gate is 35mW. They are coded with 300
and 350s numbers.
2- MECL 2 Group: It is the type of developed MECL 1. The propagation delay per
gate is 4nsec, the propagation speed is 75MHz and the power dissipation per gate is
22mW. They are coded with 1000 and 1200s numbers.
3- MECL 10K Group: It is the type of ECL subgroup that is used commonly. The
propagation delay per gate is 2nsec , the propagation speed is 125MHz and the power
dissipation per gate is 25mW. They are coded with 10000s numbers.
4- MECL 3 Group: It is the fastest one within the ECL subgroup. The propagation
delay per gate is 1nsec, the propagation speed is 400MHz and the power dissipation per
gate is 60mW. They are coded with 1600s numbers.
For ECL logic gates the logic 1 level is -0.75V and logic 0 level is -1.55 V.
Metal-Oxide Semi Conductor Logic (MOS): Through the development of field
effect transistor (FET) technique the manufacture of MOS type integrateds has begun.
The transistors in these integrateds are named as MOSFET.
Because they are slow, they are broken quickly and their driver powers are low,
they are not preferred in some applications, however, because it is easy to fabricate
them, their sizes are small and they dissipate little power, they are used in a lot of
applications.
The working voltages of MOS integrateds are between 3V and 15V. They appear
similar to CMOS integrateds through their other specifications. It should be careful of
static discharges in these integrateds and when you working;
· Do not touch the integrated counterforts with bare hands,
. Do not use grounded or DC soldering iron in solders,
· Do not leave the unused integrated counterforts in neutral, connect them to +V'
or chassis.
Complementary Metal -Oxide Semi Conductor Logic (CMOS):
Firstly a series of MOSFET circuit were developed that were designed to use in
space and sea applications. And these circuits are named as complement MOS (CMOS).
CMOS integrateds were generated according to the FET MOSFET logic. They are the
more developed types of TTLs. These circuits dissipate very little power and do not
affect from the noise much. When compared to high speed logic circuits, it is seen that
the CMOS circuits are slower. But the circuits, generating with a large number of
transistors, can be placed on a single chip and the power source to be used can be
selected in a maximal range.
The fabrication of such integrated circuits can be more economical than others.
The newest developed CMOS circuits are faster than previous generations and they are
used commonly in every place such as from electronic watch to calculating machine and
microprocessors. CMOS integrateds form from 40 XX series. Their supply voltage is 3-
18V. Their propagation delay is pretty much, maximum voltage supply is about 5MHz.
In other words it is not proper to work in high frequencies.
Figure..4
Integrated Injection Logic (IIL):
Having of IIL logic gates single input and a lot of outputs requires following a
different way in design. The advantages of this technology predominate the design
problems. And IIL memories and microprocessors are available on the market. In
recent years the IIL technology has paled behind the developments in CMOS technology
and fell from grace. Except of some differences, IIL logic gates show similar working
specifications with RTL logic gates. No resistance is used in their structures, and this
enables more circuits to be placed on a chip and makes the cost much low.
Output capacitance:
This value is 10 for TTL. In other words, other 10 TTL circuit inputs can be
supplied from a TTL output. This number in CMOS, having high output impedance, is
50.
Unused Tips:
The unused tips of TTL and CMOS integrateds must certainly not be left in
neutral. The unused tips in applications are connected to (+) or (-) tip of the source. In
the contrary case, undesired cases occur on the outputs of the integrateds. The
interconnections and specification comparison of the TTL and CMOS integrateds, having
the same specifications, are seen in the following Figure.
Figure.5
SPECIFICATIONS TTL CMOS

Supply voltage 5V DC 3 V -18 V DC
Required current Milliampere Microampere
Input Impedance Low Too High
Switching rate Fast Slow
Output capacitance 10 50
Exertion 20mW 2mW
Trigger pulse 50MHz 25MHz
Supply tolerance 20% 50%
Table.1
TEST NAME :
SCHMITT-TRIGGER GATES
TEST PURPOSES:
A- The examination of SCHMITT-TRIGGER circuit,
B- The observation of the working systems,
C- The recognition of 4093 integrated.
PRELIMINARY INFORMATION :
Figure 1.1 Figure 1.2 Figure 1.3
Figure 1.4
The structure of a Schmitt trigger circuit is seen in the Figure 1.1. So be the input
voltage firstly in 0 V or in a negative value, in this case TR1 is in section state and TR2
is in the saturation state. It is Vo <Vcc. When the input voltage increases, TR1 in a V1
value determined by the circuit components goes to saturation and TR2 goes to
section. It is Vo=Vcc.
No matter how much the input voltage is increased after that, there will be no
change in the output voltage. If the output voltage is decreased toward "0", TR1 in a
SCHMITT TRIGGER 13
certain V2 value of the input voltage moves to the section and TR2 moves to the
saturation. The output is Vo <Vcc.
V1=V2 can be made on condition of changing the components in the circuit. The
diversity of the V1 and V2 voltage levels is called "Hysteresis" and it is the most
important feature of the Schmitt trigger. (Figure.1.2) For example, if a RELAY is
connected to the output of Schmitt trigger and V1=V2 is made, the circuit gives an
output in the way of vibration because of noise, etc. to be on the signal. However
when V1 and V2 is not in the same point, but in the different points, they will create a
definite difference between warning point and warning removing point. So the circuit
will not be affected from such small changes. Consequently vibration does not occur in
the RELAY.
Because of the feature of the above circuit the smoother square wave than other
oscillators is obtained through the Schmitt trigger. Because indefinite region is less in
the Schmitt trigger.
In practices the Schmitt triggers with logic gate structure is used mostly. (
Figure.1.3)
4093 integrated counterfort connection, comprising four SCHMITT-TRIGGER gates

in its internal structure, is seen in the Figure 1.4.
SCHMITT TRIGGER 14
TEST NO : 1
TEST NAME: THE EXAMINATION OF SCHMITT-TRIGGER GATE
Elements To Be Used In The Test:

1- Y-0020-02 Digital Test Set
2- Oscilloscope
Steps of the Test:

1-Set the circuit in the Figure.1.5.
Figure. 1.5
NOTE: When R resistance is not used and the resistance is approximately "0"
ohm in the min. position of P, R inactivates. The output wave shape is alienated from
the square wave. For this purpose the value of R resistance has been given in the min.
value of P in the way that it will not deform the output wave shape. (R=6.9K)
R will be included in calculating in the frequency calculations.
1
F
1,09.R  P .C
2- R=6K9, C=470nF and bring the potentiometer to min. position. Connect the
oscilloscope to the output of the circuit. Calibrate in the way that it will measure the
output wave voltage. Apply the power.
3- Write down by measuring the output wave frequency with oscilloscope. In

addition to this, calculate the R,C values by placing them in the formula. Compare the
value that you have calculated and the value that you have measured and explain the
difference between them. Explain the reason of the difference between them.
When it is measured with oscilloscope, the approximate frequency has found as
281 Hz. The value calculated with the formula is 282,89 Hz. The difference between
them is due to the tolerances of the components.
4- Write down by measuring and calculating the output frequency when R is in

6K9, C is in 470nF and P is in max. position.
SCHMITT TRIGGER 15
The frequency value is 122 Hz with the oscilloscope and 115,5 Hz with the
calculation.
5- Explain the effect of the resistance value change on the output frequency.
As long as the resistance value increases, the output frequency decreases.
6- Bring R in 6K9 position, C in 680 nF position and P in minimum position.

Write down the output wave frequency by calculating with oscilloscope and
formula...
It is approximately 186 Hz with the oscilloscope and 195,53 Hz with the formula.
7- Bring R in 6K9 position, C in 680 nF position and P in maximum position. Write

down the output wave frequency by calculating with oscilloscope and formula...
It is approximately 81 Hz with the oscilloscope and 79,83 Hz with the formula.
8- Explain the effect of the capacity value (by accepting R as stable) on the output
frequency.
The changing of the capacity value changes the output frequency of the circuit.
The increase of the capacity value decreases the output frequency.
9-Can the square wave in desired frequency be obtained with definite resistance
and capacitive values according to the above results?
It can be obtained approximately.
10- Explain the difference of the square wave, obtained with Schmitt trigger, from
the square wave, obtained with other oscillator circuits.
The square wave, obtained with Schmitt Trigger, is smoother than the square
wave, obtained with the other oscillators. The indefinite region is less.
SCHMITT TRIGGER 16
TEST NAME :
THE EXAMINATION OF ASYNCHRONOUS COUNTERS
TEST PURPOSES :
A- The examination of the working of asynchronous counters,
B- The examination of down and up counting,
C- The determination of counting limits.
The counters are divided into two groups:
1* Asynchronous (wavy clk) counters,
2* Synchronous counters
FF output in the asynchronous counter is used to trigger the next FF. In other
words, clk inputs of all other FFs, except of the first FF, are triggered through the
changing of state of previous FF. The input impulses in synchronous counters are
applied to clk inputs of all FFs. To change state of a FF depends on the state of other
FFs. The synchronous counters works in TOGGLE Mode.
Figure 2.1
An asynchronous counter circuit with four JK / FF (*) is seen in the Figure 2.1. FF,
keeping bit with the lowest value, receives the Clk pulses. Clk inputs of FFs means that
they are triggered in a transition going to negative and change state.
(*) JK-FFs here work in T type (toggle) mode. The output in each Clk pulse that is applied
when JK input is "1" is reverse of the former one (its complement).
ASENKRON COUNTER 17
Figure 2.2
Q1(A)=0 , Q2(B)=0 , Q3(C)=0 , Q4(D)=0

When number "0" first Clk impulse passes to "0" after "1", A-FF is triggered and
its output goes to "1". Q outputs of other FFs are "0". Because no proper pulse has
applied to Clk inputs.
Q1=1 , Q2=0 , Q3=0 , Q4=0
In the falling side of number “1" Clk pulse A-FF is triggered again and Q1 output
falls to "0". The falling sided pulse has applied to the Clk input of B-FF depending on
this output. B-FF is triggered and Q2 output rises "1". (Q1 output is the trigger input of
B-FF.) Therefore while Q1 output of A-FF falls "0" in number "1" Clk impulse, Q2 output
of B-FF rises "1". There is no change in other FFs.
Q1=0 , Q2=1 , Q3=0 , Q4=0
A-FF is triggered again in the number "2" Clk impulse and Q1 output is "1". Other
FFs hold their ground.
Q1=1 ,Q2=1 ,Q3=0 , Q4=0
A-FF changes state in number "3" Clk impulse again and Q1 output is "0". This
transition provides B-FF to be triggered and Q2 output to be "0". The falling of Q2 to
"0"provides C-FF to be triggered and Q3 output is "1".
Q1=0 , Q2=0 , Q3=1 , Q4=0
The processes after that continues in this way.
All FFs are initialized in number "15" Clk impulse.
Q1=0 , Q2=0 , Q3=0 , Q=0
When the wave figures in the Figure 20.2 are examined, the sign frequency in the
output of A-FF is half of the Clk frequency, the sign in the output of B-FF is 1/4 of it,
the sign in the output of C-FF is 1/8 of it, the sign in the output of D-FF is 1/16 of it.
Consequently the counters can be used as frequency divider.
All of the outputs in the down counters are "1" in the first state. The counting is
decreased 1 through each input impulse. The counting of 4 bit binary down counter
begins with 15. It continues to 14, 13, 12, 11 ....... 0 and returns to 15 again. In the
circuit in the Figure 2.1 when the Clk inputs of other FFs, except of the first FF, are
taken from the Q' outputs of the former FF and their counting outputs are taken from
Qs, the counter becomes the down counter circuit.
ASENKRON COUNTER 18
Being Counted of the Counter in the Desired Counting Range :
A lot of counter circuit in asynchronous structure can be performed. If the

counting is desired except of 2n one of the methods is the initialization process
according to the modes.
In this method the binary counter balance of the numbers to the number to be
countered are determined. The number after the last number to be countered is
determined. According to this the FF number and type are determined. Consequently
the initialization gate is connected.
For example, let's design the mode-10 counter with the initialization method
according to the modes. The mode-10 counter counts from 0 to 9 and resets the
system in 10 counting and return to beginning. "1010" In this counter circuit 4 FFs
should be used. Because minimum 4 FFs should be used for 10 counting (from 0 to 9).
Figure 2.3
When the counting passes from 9 (QD=1, QC=0, QB=0, QA=1) to 10 (QD=1,
QC=0, QB=1, QA=0), the output of NAND gate will be 0 and activate the Clear inputs
of FFs. The counters are reset in the 10. counting moment (initialized). The counting
returns to beginning. The cost of asynchronous counter is low but its speed is also low.
It is preferred in the points that the speed is not important.
ASENKRON COUNTER 19
TEST NO : 2
TEST NAME: THE EXAMINATION OF UP ASYNCHRONOUS COUNTER MADE
OF JK FFs
The Set To Be Used In the Test :

Figure 2.4
ASENKRON COUNTER 20
Steps of the Test :
1. Set the circuit as in the Figure 2.4. Make R and S tips "0" and do not activate.
2. Make the R tip "1" and initialize the outputs. Make the R tip "0" again. QA
output corresponds to LSB bit and QD output corresponds to MSB bit. J-K FFs are within
T type working. Why?
When J and K inputs are combined and "1"is applied, its J-K FFs works as T type
FF.
3. Make the S tips (A switch) "1" and inactivate the S. Make the R tips ( D switch)
"1" temporarily and initialize the FF outputs. Why is this process necessary? How is the
LED's state in the alphanumeric display and between LED-3 and LED-0?
The counters should be initialized to count again. For this purpose the CLEAR'
input is stimulated. "0" number is seen in the alphanumeric display. LEDs between LED-
3...LED-0 are off.
4. Press the PULSE button once. Explain the change in the outputs.
The outputs are from MSB towards LSB :
QD=0, QC=0, QB=0 and QA=1. "1" value is seen in the display.
5. Fill the table according to the pulse sequence in the Table 2.1.
OUTPUTS HEX DECIMAL

CLOCK
QD QC QB QA EQUIVALENT EQUIVALENT
0 0 0 0 0 0 0
1 0 0 0 1 1 1
2 0 0 1 0 2 2
3 0 0 1 1 3 3
4 0 1 0 0 4 4
5 0 1 0 1 5 5
6 0 1 1 0 6 6
7 0 1 1 1 7 7
8 1 0 0 0 8 8
9 1 0 0 1 9 9
10 1 0 1 0 A 10
11 1 0 1 1 B 11
12 1 1 0 0 C 12
13 1 1 0 1 D 13
14 1 1 1 0 E 14
15 1 1 1 1 F 15
16 0 0 0 0 0 0
17 0 0 0 1 1 1
Table 2.1
ASENKRON COUNTER 21
6. Why are the outputs "0" after the 15. pulse in the Table 2.1? Which number
does the modulo of counter has?
Because the modulo of the counter is 4 (24=16)* the counter counts to 16. (from
0 to 15 total 16 ) After 16. counting the counter comes to its first state again.(0000)
7. Did the counter work as up counter according to this?
The counter worked as up counter.
8. What was the change if 4511 (BCD DECODER) was used instead of
(HEX_DECODER) used in the alphanumeric display?
Because the BCD counter counts from 0 to 9, the BCD decoder counts normally
from 0 to 9. If it was from 10 to 15, the figures that cannot be defined as number was
occurred.
* When 4 FFs without feedback are connected in sequence and used as counter, they
counts to 16. If the 5. FF was available, it would count to 32.
ASENKRON COUNTER 22
TEST NO : 3
TEST NAME : THE EXAMINATION OF DOWN SYNCHRONOUS
COUNTER MADE OF JK FFs
The Test Set To Be Used In The Test :

Figure 3.1
ASENKRON COUNTER 23
Steps of the Test :
1. Set the circuit as in the Figure 3.1 and apply the power. Make the R tip "0".
2. Make the S input firstly "1" then "0". How is the state of the outputs? Why?
The outputs are like that: QD=1, QC=1, QB=1, QA=1. Because when Pr' input is
activated, FF outputs are "1".
3. Apply the first clk pulse to the counter input by pressing the PULSE button.
Explain the state of outputs.
The outputs have passed from the state of 1111 to the state of 1110 (QD=1,
QC=1, QB=1, QA=0).
4. Fill the Table 3.1. What kind of counting does the counter make? Why?
Because the counter makes downward counting, it is Down Counter. Because
the Q' outputs are used to trigger FFs, the counter makes downward counting process.
5. Which number does the modulo of counter have?

The modulo of the counter is 16.
OUTPUTS HEX DECIMAL

CLOCK
0 0 0 0 0 0 0
1 1 1 1 1 F 15
2 1 1 1 0 E 14
3 1 1 0 1 D 13
4 1 1 0 0 C 12
5 1 0 1 1 B 11
6 1 0 1 0 A 10
7 1 0 0 1 9 9
8 1 0 0 0 8 8
9 0 1 1 1 7 7
10 0 1 1 0 6 6
11 0 1 0 1 5 5
12 0 1 0 0 4 4
13 0 0 1 1 3 3
14 0 0 1 0 2 2
15 0 0 0 1 1 1
16 0 0 0 0 0 0
17 1 1 1 1 F 15
Table 3.1
ASENKRON COUNTER 24
TEST NO : 4
TEST NAME : THE DETERMINATION OF THE COUNTING RANGE OF
ASYNCHRONOUS COUNTER
The Circuit Components Used In The Test :

Figure 4.1
ASENKRON COUNTER 25
Steps of the Test :
1. Combine the Gnds of the Sets. Set the circuit as in the Figure 4.1 and apply
the power.
2. Make the SET input (A switch) "0".
3. Press the PULSE button until the FF outputs are initialized.
4. Fill the Table 4.1. What kind of counting does the counter make?
The counter counts upward.
5. What is the modulo of the counter? Why?

The modulo of the counter is 10. It counts from 0 to 9. When the counter counts
1010, 4081 AND gate output is "1" and the FF outputs is initialized through being "1" of
the neutral RESET' input. The counting begins again.
8. What is the necessary change for the modulo of the counter to be 12?
When the outputs are 1100, the counter is connected to the 4081 AND gate
inputs by taking one from QD and QC outputs in the way that it will reset itself. The
output is connected to RESET input. Because 12 counting is made totally, the modulo is
12.
ÇIKIŞLAR HEX DECIMAL

CLOCK
0 0 0 0 0 0 0
1 0 0 0 1 1 1
2 0 0 1 0 2 2
3 0 0 1 1 3 3
4 0 1 0 0 4 4
5 0 1 0 1 5 5
6 0 1 1 0 6 6
7 0 1 1 1 7 7
8 1 0 0 0 8 8
9 1 0 0 1 9 9
10 0 0 0 0 0 0
11 0 0 0 1 1 1
Table 4.1
ASENKRON COUNTER 26
TEST NAME :
THE EXAMINATION OF THE SYNCHRONOUS COUNTERS MADE BY JK FFs
TEST PURPOSES:
A- The examination of the workings of synchronous counters

B- The examination of the up synchronous counter
C- The examination of the down synchronous counter
D- The determination of the counting limits of synchronous counter
The synchronous counters do not have the disadvantages of the asynchronous
counters. In this type of counter the main component is FF and in addition the gates are
also used. Therefore their costs are higher than asynchronous counters. However the
pulse input in the asynchronous counters is firstly from FF, after the pulse applied firstly
to FF, the last transition to FF is made alternately after the state changes of all FFs.
Because this causes FFs to change state in a long counting time, it leads to time loss
and the counting speed decreases. In the cases that the counting speed is requested to
be high the synchronous counters are used.
In the synchronous counters the trigger pulse for FF in counter is given from a
common pulse input, the changing state of FFs does not depend on the JK inputs of JK-
FF. Therefore the counter speed is increased significantly. Because the clock pulse
triggers all FFs in the same time.
4 bit (mode 16) synchronous counter circuit is seen in the Figure 5.1.
Figure 5.1
At first all FFs (*1) are in the "0" position; JK inputs of B, C, D and FFs (*2) will be
"0" (low) and will not change state with the 1. clock pulse. However, because JK input
of A-FF is connected to "1", it will change the state firstly with the Clk pulse. (The
output passes from "0" to "1") In this case JK inputs of B-FF have been "1".
With the second Clk impulse both its A-FF (from "1" to "0") and its B-FF (from "0"
to "1") will change the state. The counter shows "2". Because being "0" of A-FF output
will keep JK input of B-FF in "0", only A-FF will change state in the third Clk pulse (it will
be "1").
SENKRON COUNTER 27
In this case QA=1 , QB=1 , QC=0 , QD=0 has been. The counter shows 3.
Because both outputs of QA and QB are "1", the output of AND gate is "1", therefore JK
input of C-FF is also "1".
A-FF and B-FF will reach "0" position in the 4. clock pulse, C-FF reaches "1"
position. The counter continues its counting process similarly. The showing "7" of the
counter in the position the QA, QB and QC outputs are "1" provides to change DFF state
to "1" to make the AND gates counting "8".
All FF outputs change their position in the Clk impulse, coming after the counting
15, it comes to "0" position.
The working of synchronous 2 down counting circuit is in a similar way.
(*1) All FFs work as T type. (*2) Its A-FF is LSB , D-FF is MSB.
SENKRON COUNTER 28
TEST NO : 5
TEST NAME : THE EXAMINATION OF UP SYNCHRONOUS COUNTER
CONSISTING OF JK FFs
The Test Sets Used in the Test :

Figure 5.2
SENKRON COUNTER 29
Steps of the Test :
1. Set the circuit as in the Figure 5.2, combine the GNDs of both sets and apply
the power.
2. Make the SET tip (A switch) "0" and not activate. Bring the RESET tip (D switch)
to "1" position temporarily and then make it "0". Was "0" seen in display? Why?
"0" was seen in display. When RESET input is activated, FF outputs are "0"
(Qs=0). "0" value, applied to the decoder input and corresponded of 0000 value is
seen.
3. Apply the first Clk pulse to FFs with PULSE button. Explain the change in the
outputs.
During the decline of the 1. FF Clk impulse, one of the FFs working T-type with
the first trigger, from 1 to 0 it changes its state and its output will be "1". Therefore
the outputs:
QD=0 QC=0 QB=0 QA=1 "1" number is seen in display.
4. Fill the Figure 5.1 according to the pulses applied.

5. What kind of counting does the counter make according to the results in the
Table 5.1? Why?
Because the outputs are taken from Qs, the counter make counting upward.
6. Is the principle of synchronous counter, given in the preliminary information,

suitable with the changes to LED-3...LED-0 depending on the outputs when each pulses
are applied?
It is suitable.
OUTPUTS HEX DECIMAL

CLOCK
0 0 0 0 0 0 0
1 0 0 0 1 1 1
2 0 0 1 0 2 2
3 0 0 1 1 3 3
4 0 1 0 0 4 4
5 0 1 0 1 5 5
6 0 1 1 0 6 6
7 0 1 1 1 7 7
8 1 0 0 0 8 8
9 1 0 0 1 9 9
10 1 0 1 0 A 10
11 1 0 1 1 B 11
12 1 1 0 0 C 12
13 1 1 0 1 D 13
14 1 1 1 0 E 14
15 1 1 1 1 F 15
16 0 0 0 0 0 0
17 0 0 0 1 1 1
Table 5.1
SENKRON COUNTER 30
TEST NO : 6
TEST NAME : THE EXAMINATION OF DOWN SYNCHRONOUS
COUNTER CONSISTING OF JK FFs
The Components Used in the Test :
Figure 6.1
SENKRON COUNTER 31
Steps of the Test:
1. Set the circuit as in the Figure 6.1, combine the GNDs of the Sets and apply
the power.
2. Bring the RESET input (D switch) to "0" position. Bring the SET input to "1"
position temporarily and then make it "0". In the meantime the RESET input is in "0"
position. Explain the process applied. What happened to the state of the outputs?
Q outputs of all FFs have reached to "1" position.
QD QC QB QA
1 1 1 1
3. Fill the Table 6.1 in accordance with the pulses applied.
4. What kind of counting has the counter made according to the results in Table
6.1? Why?
The counter has worked as down counter. Because the triggering of FFs is taken
from Q' outputs, the counting is downward.
5. What is the modulo of the counter?

The modulo of the counter is "16". It counts between 0 - 15.
OUTPUTS HEX DECIMAL

CLOCK
0 0 0 0 0 0 0
1 1 1 1 1 F 15
2 1 1 1 0 E 14
3 1 1 0 1 D 13
4 1 1 0 0 C 12
5 1 0 1 1 B 11
6 1 0 1 0 A 10
7 1 0 0 1 9 9
8 1 0 0 0 8 8
9 0 1 1 1 7 7
10 0 1 1 0 6 6
11 0 1 0 1 5 5
12 0 1 0 0 4 4
13 0 0 1 1 3 3
14 0 0 1 0 2 2
15 0 0 0 1 1 1
16 0 0 0 0 0 0
17 1 1 1 1 F 15
Table 6.1
SENKRON COUNTER 32
TEST NO : 7
TEST NAME : THE CHANGING OF THE COUNTING LIMITS OF
SYNCHRONOUS COUNTER
The Test Sets Used in the Test:
Figure 7.1
SENKRON COUNTER 33
Steps of the Test :
1. Set the circuit as in the Figure 7.1, combine the GNDs of the Sets and apply
the power.
2. Bring the SET input (A switch) to "1" position and not activate. Bring the RESET
input (D Switch) to "0" position temporarily. Then bring it to "1" position.
3. Find the modulo of the counter by pressing the PULSE button. How is the
modulo?
The counter is designed according to the MODE-5. It counts from 0 to 4, resets in

the 5. pulse and starts over again.
4. Can the counting process be made to the desired number?
Yes, it can be made.
OUTPUTS HEX DECIMAL

CLOCK
0 0 0 0 0 0 0
1 0 0 0 1 1 1
2 0 0 1 0 2 2
3 0 0 1 1 3 3
4 0 1 0 0 4 4
0 0 0 0 0 0 0
1 0 0 0 1 1 1
Table 7.1
SENKRON COUNTER 34
TEST NAME :
THE EXAMINATION OF 4024 BINARY COUNTER INTEGRATED
TEST PURPOSES :
A- The examination of 4024 Counter Integrated,

B- The observation of working systems,
C- The recognization of 4024 integrated.
*4024 is binary counter and counts to 127.

(1111111)2=(127)10
*After the counter has made 127 countings, it is reset itself and returns to
beginning. The counter can be arranged in the way that it will count in the demanded
counting range by using one or a few of 7 outputs (on condition that "0" is the sub
limit). For example; if Q4 output is connected to the reset input, the counter counts
from "0" to "7" and then returns to "0". The reset process performs in that way.
*Because RESET will be "1" when Q4 output is "1", the counter returns to "0".
*When total 20 countings are requested by the counter, Q3 and Q5 outputs are
connected with AND gate to RESET tip. Q5=1 , Q4=0 , Q3=1 , Q2=0 , Q1=0 Counter
is reset in 20. pulse and returns to zero.
*4024 binary counter is also used as frequency divider. For example; When 1 KHz
clock pulse is applied to the Clk input, Q1 output will be 500 Hz, Q2 output will be 250
Hz, Q3 output will be 125 Hz.......etc.
Figure 8.1
4024 BINARY COUNTER 35

TEST NO : 8
TEST NAME : THE EXAMINATION OF 4024 COUNTER INTEGRATED
The Test Sets to be Used in the Test:

Figure. 8.2

INPUTS OUTPUTS
CLK MR Q7 Q6 Q5 Q4 Q3 Q2 Q1
0 1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
2 0 0 0 0 0 0 1 0
3 0 0 0 0 0 0 1 1
4 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 1
6 0 0 0 0 0 1 1 0
7 0 0 0 0 0 1 1 1
8 0 0 0 0 1 0 0 0
9 0 0 0 0 1 0 0 1
10 0 0 0 0 1 0 1 0
11 0 0 0 0 1 0 1 1
12 0 0 0 0 1 1 0 0
13 0 0 0 0 1 1 0 1
14 0 0 0 0 1 1 1 0
15 0 0 0 0 1 1 1 1
“ “ “ “ “ “ “ “ “
“ “ “ “ “ “ “ “ “
“ 0 1 1 1 1 1 1 1
Table 8.1
Steps of the test :
1. Set the circuit as in the Figure 8.2 and apply the power by combining the
GNDs of Sets.
2. Press the PULSE button and examine to which number the counter counts.
The counter counts to 31 (Binary 11111, Decimal 31).
3. Why does not the counter count 32 and higher?

Because Q6 output is connected to RESET input, 32 countings performs in Q6
output. Because Q6 output is "1" and this output tip is connected to the reset input, the
reset process performs when Q6 is "1".
4. Connect Q1 and Q7 output to an AND gate and the AND gate output to RESET
counterfort of the counter. Press the PULSE button and examine to wihch number the
counter counts and when it is reset.
When both Q1 and Q7 is "1", the output of AND gate is "1". The counter is reset
in that moment. The moment that Q1 and Q7 is "1" is the moment that the counter
counts to 65. When it is 65 as decimal, the counter is reset.
Q7 Q6 Q5 Q4 Q3 Q2 Q1
64 32 16 8 4 2 1
(1 0 0 0 0 0 1)2 =(65)10

5. Explain the process that should be made for the counter to count to 127.
The output taken from the Q8 tip of the counter is connected to the reset tip of
the counter. The counter is:
Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1
128 64 32 16 8 4 2 1
(0 1 1 1 1 1 1 1)2 =(127)10.
When all from Q1 to Q7, except of Q8, are "1", the counter counts as 127.
6. Explain the process that should be made for the counter to count to 32.
It is connected to Q6 reset input of the counter. When the counter counts 31, Q6
is "1" and the counter is reset.
7.To which number the counter counts totally and in which number it is initialized?
The counter has total 7 outputs, therefore when ( 27 = 128 ) and all of 7 outputs
are "1", it counts to 127 and the counter is reset automatically after 127 and the
counting from "0" begins again.
8. Separate the CLOCK input of the counter from PULSE and connect to VARIABLE
CLOCK output. Make the PRESENT CLOCK frequency 500 Hz by connecting the 1. canal
of oscilloscope to VARIABLE CLOCK output. Connect the 2. canal of the oscilloscope in
the way that it will measure Q1 output. Measure Q1, Q2, Q3, ....,Q7 frequencies and
explain the relationship between them.
500 Hz CLK pulse applied to 4024 input is obtained from Q1 output of the counter
as 250 Hz. Half Q1 from Q2 output 125 Hz ...... etc. continues.
9. Can we use the counter outputs by using them as frequency divider according
to the result in the 8. step to obtain desired oscillator frequency?
Yes, we can use.

TEST NAME:
4520 BINARY COUNTER
TEST PURPOSES:
A- The examination of binary counter,
C- The recognization of 4520 BINARY COUNTER integrated.
PRELIMINARY INFORMATION:
Counters:
They are logical circuits that are positioned in a certain place according to the
impulses applied to their input. There are a lot of application areas in digital electronics.
Some of them are digital clock, frequency counter, frequency divider, decoder, digital
alarm, street traffic control lights etc.
The fundamental structures of the counters are the logical circuits and flip-flops.
The counters are generally obtained by being connected of FFs properly and in
sequence. The counter changes over through each impulse applied to input. Without
any feedback they can position differently in 2n number according to the blow count
applied to a counter circuit input, consisting of F-F in n number. For example; if 4 F-F
has been used in the counter structure, 24 = 16 can position differently. In other
words, it can counter fromm 0 to 15.
The state amount that a counter can count without recursion is called MODULO of
that counter. The counter given in the example above is Mode-16 counter.
If the counter is requested to count except of 2n, either the initialization process
according to the modes or direct reset counter design method may be used.
Figure 9.1
4520 (*) is the binary counter. It is the asynchronous type counter integrated. The
pin identifications are given in the Figure 9.1 and internal logic circuit is given in the
Figure 9.2. Some pins are not used. These are marked as NC (nonconnected).
Figure 9.2
BINARY COUNTER 39
TEST NO: 9
TEST NAME: USING OF 4520 INTEGRATED AS COUNTER
The Test Set Used in the Test :

1- Y–0020–02 Digital Test Set
Figure. 9.3
BINARY COUNTER 40
Steps of the test:
1. Set the circuit as in the Figure 9.3 and apply the power.. Position the switches
in A=1 and B=0, Explain the result by pressing the pulse button.
Each pulse changes the state of the outputs. The counting begins from “0000” and
continues to “1111” state and then continues by returning to beginning.
3. Position the A switch to "0" during counting. Press the PULSE button. Is there
any change in LED? Then position the B switch to "1". Explain the change in LED.
The positioning of A switch to “0” prevents the counting allowance state and the
counting stops. When it is positioned to “1” again, it is allowed and the counting
resumes.
The positioning of B switch to “1” means that the circuit is RESET. The counting
returns to beginning as “0000”.
INPUTS OUTPUTS
CLK E MR Q4 Q3 Q2 Q1 HEX
0 1 1 0 0 0 0 0
1 1 0 0 0 0 1 1
2 1 0 0 0 1 0 2
3 1 0 0 0 1 1 3
4 1 0 0 1 0 0 4
5 1 0 0 1 0 1 5
6 1 0 0 1 1 0 6
7 1 0 0 1 1 1 7
8 1 0 1 0 0 0 8
9 1 0 1 0 0 1 9
10 1 0 1 0 1 0 A
11 1 0 1 0 1 1 B
12 1 0 1 1 0 0 C
13 1 0 1 1 0 1 D
14 1 0 1 1 1 0 E
15 1 0 1 1 1 1 F
16 1 0 0 0 0 0 0
Table 10.1
BINARY COUNTER 41
TEST NO : 10
TEST NAME: THE USING OF 4520 BINARY COUNTER AS 3 BIT
COUNTER
The Test Set Used in the Test:

Figure. 10.1
BINARY COUNTER 42
Steps of the test :
1. Set the circuit as in the Figure 10.1 and apply the power.
2. POSITION the A switch to "1”. Is it necessary to do this stage?
It is necessary. The input should be "1" for the purpose that the counter can take
the counting allowance.
3. Press the PULSE button a few times. Explain the result.

The counter begins to count when pressing the button.
4. To which number does the counting continue and from which number does it
return to beginning?
The counting continues until three outputs is “111” in other words “7”, after it is
“111”, it returns to beginning, because the 4. output is connected to RESET tip, it
RESETs the pulse counter after “111”.
INPUTS OUTPUTS
CLK E Q4 Q3 Q2 Q1 HEX
0 1 0 0 0 0 0
1 1 0 0 0 1 1
2 1 0 0 1 0 2
3 1 0 0 1 1 3
4 1 0 1 0 0 4
5 1 0 1 0 1 5
6 1 0 1 1 0 6
7 1 0 1 1 1 7
8 1 1 0 0 0 8
9 1 1 0 0 1 9
Table 10.2
BINARY COUNTER 43
TEST NO : 11
TEST NAME : THE USING OF 4520 AS BCD COUNTER
The test set used in the test :

Figure 11.1
BINARY COUNTER 44
Steps of the test:
1. Set the circuit as in the Figure 11.1 and apply the power.
2. If the output does not show the zero in the binary system, press the PULSE
button until you see the zero (all leds are off).
3. Follow the counting of the counter by continuing to press the PULSE button.
4. To which number has the counter count? Why?
The counter has counted to 9. 4081 AND gate output, determining the counting
range of the counter should be “1”. The counter will in the state to count "1010" after
"1001". Because "11" will be applied to the AND gate at that moment, the counter will
be reset. Therefore the counting will continue as "0000" after "1001".
INPUTS OUTPUTS
CLK E MR Q4 Q3 Q2 Q1 HEX
0 1 1 0 0 0 0 0
1 1 0 0 0 0 1 1
2 1 0 0 0 1 0 2
3 1 0 0 0 1 1 3
4 1 0 0 1 0 0 4
5 1 0 0 1 0 1 5
6 1 0 0 1 1 0 6
7 1 0 0 1 1 1 7
8 1 0 1 0 0 0 8
9 1 0 1 0 0 1 9
10 1 1 0 0 0 0 0
11 1 0 0 0 0 1 1
12 1 0 0 0 1 0 2
Table 10.3
BINARY COUNTER 45
TEST NAME :
UP-DOWN COUNTERS
TEST PURPOSES :
A- The examination of UP-DOWN counters,
C- The recognition of 4510 UP-DOWN COUNTER integrated.
D- The examination of the counterfort connections of 4510 UP-DOWN COUNTER
integrated.
Hexadecimal counters follows a 16 stated sequence and return 0 after 15
countings. This type of counter should have at least 4 FF to represent each Hex. step.
Because a step is shown with a binary code having at least 4 bit. The counting
sequence in hexadecimal counter is determined with binary code, used to show the
decimal step. This counter looks like binary counter except that the state after "1111"
(Hex. F code) is "0000" (Hex. 0 code).
According to this a decimal counter follows a sequence with 10 states and returns
0 after 9 countings. This type of counter should have at least 4 FF to represent each
decimal steps. Because a step is shown with a binary code having at least 4 bit. The
counting sequence in decimal counter is determined with binary code, used to show the
decimal step. This counter looks like binary counter except that the state after "1001"
(Decimal 9 code) is "0000" (Decimal 0 code).
BCD asynchronous counters :
The logical schema of a BCD asynchronous counter has been given in the Figure
12.1.
Figure 12.1
FFs are triggered in the negative side, in other words, when the Clk signal comes
from "1" to "0", J and K inputs are connected to either a stable signal or FF outputs as
seen in the schema, when Clk passes from "1" to "0" if J=1, remember that FF is set
(Q=1), if K=1, remember that FF output (Q=0) is deleted, if J=K=1, remember that the
output works in TOGGLE mode (the output in each clk impulse is reverse of the former
one and completed) and if J=K=0, remember that the output remains same.
UP-DOWN COUNTER 46
For each FF state transition ;
a) Q1 changes its state in the negative side of each counting impulse.
b) Q8=0 and Q1 pass from "1" to "0", Q2 changes its state. If Q8=1 and Q1
passes from "1" to "0", the output of Q2 is deleted.
c) If Q2 passes from "1" to "0", Q4 changes its state.
d) When Q4=1 and Q2=1 and when Q1 passes from "1" to "0", Q8 changes its
state. When Q4 and Q2 is "0" and Q1 passes from "1" to "0", the output of Q8 is
deleted.
Take a look at the subject of counter design with FFs (Test 12 the section of
counter design with karnaugh) to set BCD synchronous counter. The design method
should be applied as it is made here.
In this test the working of 4510 integrated, which is programmable BCD up / down
counter will be examined. 4510 is a 16-leg integrated and;
1- counts up or down from "0000" to "1001".
2- can be programmed in the way that the counting will make from a desired
value between 0 and 15 to up 15 or down zero by using load tip.
3- A modulo can be programmed as -N counter.
4- Co output starts at "1001" in up counting and at "0000" in down counting.
5- The counting can be stopped through Enable tip.
7- The counterfort connections of 4510 BCD COUNTER integrated are shown in
the Figure 12.2.
8- BCD 4510 integrated has 4 data entry ( A1, A2, A3, A4 ) tips. When it is
requested to begin to count from any value, this value is given through the input tips
and PE (load) input is made "1" for a while. The information in the data entries is
loaded to BCD counter.
9- Has 4 outputs (QA,QB,QC,QD). Is QA LSB , QD MSB bit.
10- U / D’ input tip is used to program to count up ( U ), down ( D ). When "1" is
applied to U / D’ input, it is programmed to count up, when "0" is applied, it is
programmed to count down.
Figure 12.2
UP-DOWN COUNTER 47
TEST NO : 12
TEST NAME: UP/DOWN BCD COUNTER
The Test Set To Be Used in the Test :

1- Y-0020-02 Digital Test Set.
Figure 12.3
UP-DOWN COUNTER 48
Steps of the test :
1. Set the circuit as in the Figure 12.3, make UP'/DOWN tip (D switch) "1" and PE
(A switch) "0" and apply the power.
2. "0" should be seen in display. If it is not seen, press the PULSE button until it is
seen.
3. Press the PULSE button once. What is the change in the display state?
"1" is seen in the display, the outputs are alternately QD=0, QC=0, QB=0 and
QA=1.
4. Increase counting by pressing the Pulse button. Fill the Table 12.1.
5. Why is the counting upward?
Each pulse changes the BCD counter. Because U'/D tip is "0", the selection is
upward. When U/D is "1", the counting is downward.
6. Make the U'/D tip (D switch) "0". Press the PULSE button in sequence. What is
the result?
This action provides to count downward instead of upward.

7. Make the PE tip (A switch) "1", press the pulse button. What happened?
Being "1" of PE tip causes the counter no to count. Because the word ENABLE
means allowance, it is not permitted to count.
8. Make the PE tip (A switch) "0" again, press the PULSE button. What happened?
Because it is permitted the counter has begun to count again.
CLK PE (Ci)’ MR U/D’ OUTPUT CLK PE (Ci)’ MR U/D’ OUTPUT

1 0 0 0 1 0 1 0 0 0 0 0
2 0 0 0 1 1 2 0 0 0 0 9
3 0 0 0 1 2 3 0 0 0 0 8
4 0 0 0 1 3 4 0 0 0 0 7
5 0 0 0 1 4 5 0 0 0 0 6
6 0 0 0 1 5 6 0 0 0 0 5
7 0 0 0 1 6 7 0 0 0 0 4
8 0 0 0 1 7 8 0 0 0 0 3
9 0 0 0 1 8 9 0 0 0 0 2
10 0 0 0 1 9 10 0 0 0 0 1
11 0 0 0 1 0 11 0 0 0 0 0
Table 12.1 Table 12.2
UP-DOWN COUNTER 49
TEST NO : 13
TEST NAME : THE WORKING BCD COUNTER BY PROGRAMMING
The Test Set Used in the Test :

Figure 13.1
UP-DOWN COUNTER 50
Steps of the test :
1. Prepare the circuit as shown in the Figure 13.1.
2. Bring the A1, A2, A3, A4 tips ( E, F, G, H switches) in "0" position and apply the
power.
3. Make the LOAD (PE) tip (A switch) firstly "0" and then "1".
4. Display should show zero. Press the PULSE button alternately and explain how
the counting has performed.
The counting has performed from 0 to 9.
5. Press the PULSE button in the way that the display will show a different value
from zero.
6. Bring the LOAD (PE) tip (A switch) firstly "0", then "1" again. Explain what
happened.
The state, determined with A1. A2. A3. A4 inputs, is loaded to the counter when
LOAD is made "0".
7. Initialize the display by pressing the Pulse button. Adjust the related switches in
the way of A1=1, A2=1, A3=1, A4=0. Make the PE switch firstly "0" then "1". Explain
what happened. Complete the counting through the PULSE button. From which number
has the counting begun?
When LOAD' is made "0" temporarily, the value determined with A1. A2. A3. A4
tips is loaded to the counter. The counting has begun from 7.
UP-DOWN COUNTER 51
TEST NAME : THE EXAMINATION OF DECADE - JOHNSON COUNTER
INTEGRATED
TEST PURPOSES:
A-To learn the principle of the Johnson counter,
B-To make the Johnson counter applications and the accuracy table.
C-To recognize CD 4017integrated.
1* JOHNSON counter is another type of synchronous counter. A FF has been used
for each counting. If the counter, counting 11, is demanded, 11 FF should be used.
Only one output of these FF is "1" in a while, the output of others is "0".
The counterfort connection is seen in the figure 14.1.
Figure 14.1
4017 INTEGRATED ACCURACY TABLE
INPUTS OUTPUTS
CLK RST CE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
1 0 0 1 0 0 0 0 0 0 0 0 0
2 0 0 0 1 0 0 0 0 0 0 0 0
3 0 0 0 0 1 0 0 0 0 0 0 0
4 0 0 0 0 0 1 0 0 0 0 0 0
5 0 0 0 0 0 0 1 0 0 0 0 0
6 0 0 0 0 0 0 0 1 0 0 0 0
7 0 0 0 0 0 0 0 0 1 0 0 0
8 0 0 0 0 0 0 0 0 0 1 0 0
9 0 0 0 0 0 0 0 0 0 0 1 0
10 0 0 0 0 0 0 0 0 0 0 0 1
11 0 0 1 0 0 0 0 0 0 0 0 0
12 0 0 0 1 0 0 0 0 0 0 0 0
Table 14.1
RING-COUNTER 52
TEST NO : 14
TEST NAME : THE EXAMINATION OF DECADE -JOHNSON COUNTER
INTEGRATED
The Components to be used in Test:

1-Y-0020-02 Test Set.
Figure 14.2
RING-COUNTER 53
Steps of the test:
1- Set the circuit as in the Figure 14.2 and apply the power.
2- PULSE or VARIABLE CLOCK can be used in the test. If VARIABLE CLOCK will be
used, switch to min. position.
3- Place B switch to “1” position and then to "0" position again. Explain the process
carried out.
4017 outputs are RESETED.
4- Is “1” information obtained in outputs alternately? Does it work within the

information given in the priliminary information?
Yes, “1” information has obtained from outputs alternately. It has worked as the
priliminary information.
5- Does the circuit works in 12. impulse return to beginning?
Yes, “1” information has obtained from outputs alternately. It has worked as the
priliminary information.
6- Connect Q9 output to the RESET input of 4017. Explain the system working.
4017 counts 9 countings and the system is reset in 10. Impulse and the working
returns to beginning.
7- Increase the frequency of VARIABLE CLOCK. Has the working of 4017 changed?
How has it changed?
Yes. The counting speed has increased.
INPUTS OUTPUTS
CLK RST CE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
10 0 0
11 0 0
12 0 0
Table 14.2
RING-COUNTER 54
TEST NAME : THE EXAMINATION OF 8 TO 3 ENCODER
TEST PURPOSES :
A-To learn the principle of the encoders,
B-To make the encoder applications and the accuracy table.
C-To recognize 4532 integrated.
The 8 to 3 encoder is made with 4532 and 74148 integrateds. Although this type
of circuits is designed with logic gates, they are not preferred due to the cost and place
problem.
The encoder integrated counterfort connections and accuracy table are seen in the
following table. The 8 input is coded in the circuit and transformed into 3 output.,
because it is the priority encoder, only the last big input is coded to the output. Ei input
is used to activate the output. E0 shows that the output is active, if GS output is “0”, it
is active.
Figure 15.1
INPUTS OUTPUTS
Ei D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 E0 GS
0 X X X X X X X X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 0 0 0 0 0 1 0 0 0 0 1
1 0 0 0 0 0 0 1 0 0 0 1 0 1
1 0 0 0 0 0 1 0 0 0 1 0 0 1
1 0 0 0 0 1 0 0 0 0 1 1 0 1
1 0 0 0 1 0 0 0 0 1 0 0 0 1
1 0 0 1 0 0 0 0 0 1 0 1 0 1
1 0 1 0 0 0 0 0 0 1 1 0 0 1
1 1 0 0 0 0 0 0 0 1 1 1 0 1
Table 15.1
8 TO 3 ENCODER 55
TEST NO: 15
THE EXAMINATION OF 8 TO 3 ENCODER
The components to be used in test:
1- Y-0020-02 Test Set
Figure 15.2
8 TO 3 ENCODER 56
Steps of the test :
2- Apply the states in the table.
3- Save the states to the table by observing the output.
4- Has the coding process carried out according to the results in table 15.2?
INPUTS OUTPUTS
Ei D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 E0 GS
0 X X X X X X X X
1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1 0
1 0 0 0 0 0 1 0 0
1 0 0 0 0 1 0 0 0
1 0 0 0 1 0 0 0 0
1 0 0 1 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
Table 15.2
8 TO 3 ENCODER 57
TEST NAME :
THE EXAMINATION OF DECIMAL TO BCD ENCODER
Standard integrateds are used by coding from DECIMAL system to BCD system.
The commonly used of these is 74HC147 integrated. This integrated has inputs between
D0-D9 and works with “0” logic, its outputs works with “0” logic. This case means the
extinction of LEDs, connecting to the output and being on normally. This causes
disorder in the test circuit and the students not to understand the case. So the output
signals will be examined from LOW LED (GREEN LED) inputs. Because the circuit is
priority encoder, it works in the way of the highest case selection. Only one of the
switches is in the selected position and this case is in the way of the highest value
acceptance.
The counterfort connection schema and accuracy table has been seen in the
following figure.
Figure 16.1
INPUTS OUTPUTS
NUMBER D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Q3 Q2 Q1 Q0
0 1 1 1 1 1 1 1 1 1 1 0 0 0 0
1 1 0 1 1 1 1 1 1 1 1 0 0 0 1
2 1 1 0 1 1 1 1 1 1 1 0 0 1 0
3 1 1 1 0 1 1 1 1 1 1 0 0 1 1
4 1 1 1 1 0 1 1 1 1 1 0 1 0 0
5 1 1 1 1 1 0 1 1 1 1 0 1 0 1
6 1 1 1 1 1 1 0 1 1 1 0 1 1 0
7 1 1 1 1 1 1 1 0 1 1 0 1 1 1
8 1 1 1 1 1 1 1 1 0 1 1 0 0 0
9 1 1 1 1 1 1 1 1 1 0 1 0 0 1
Table 16.1
10 TO BCD ENCODER 58
TEST NO: 16
DECIMAL TO BCD ENCODER

1- Y-0020-02 Test set
Figure 16.2
Steps of the test :
INPUTS OUTPUTS
NUMBER D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Q3 Q2 Q1 Q0
0 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1
2 1 1 0 1 1 1 1 1 1 1
3 1 1 1 0 1 1 1 1 1 1
4 1 1 1 1 0 1 1 1 1 1
5 1 1 1 1 1 0 1 1 1 1
6 1 1 1 1 1 1 0 1 1 1
7 1 1 1 1 1 1 1 0 1 1
8 1 1 1 1 1 1 1 1 0 1
9 1 1 1 1 1 1 1 1 1 0
Table 16.2
DECODERS
PRELIMINARY INFORMATION
Decoder circuits are the circuits that transforms the codified knowledge, coming
from the line in n number, into the putput in 2n number. In some circuits the output in
2n number may not be demanded, for example, BCD code comes from 4 lines but is
converted in 10 lines instead of 16.
The decoding may be varied as the trasform of input in n number into the output
in m number or into indicator, having 7 parts . The indicator having 7 parts
transformers can make transformation process from BCD or 4. n-m transformers can be
made as 2-4, 3-8, 4-BCD or 4-16 transformer.
Logic "1" and logic "2" states may occur according to the output state in the
decoders.
If the output is “1”, the logic is “1”, if the output is “0”, the logic is “0”.
3 TO 8 DECODER 61
TEST NAME :
3 TO 8 DECODER
3 to 8 decoder circuits is made generally through the integrated circuits. There

are a few types of integrated, produced for this purpose. The commonly used of these
are 74137-38 and 74237-38 integrateds. When the integrated input is active “1”,
74137-38 integrated outputs are active “0”, 74237-38 integrateds give active “1”
output. In our test circuit the active “0” outputs have been used and the observation of
control has been provided through the glowing of LEDs.
There are three control inputs in 74237 integrated. The LE and E2 is active “0”,
E1 is active “1”. D0, D1 and D2 inputs provide the necessary output to occur by
controlling the input.
The counterfort connections of integrated and the output table are seen in the
following figure.
Figure 17.1
INPUTS OUTPUTS
NUMBER LE’ E2’ E1 D2 D1 D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 X x x x X 1 1 1 1 1 1 1 1
X 1 X X x x 1 1 1 1 1 1 1 1
x x 0 x x x 1 1 1 1 1 1 1 1
0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0 1 0 0 0 0 0 0
2 0 0 1 0 1 0 0 0 1 0 0 0 0 0
3 0 0 1 0 1 1 0 0 0 1 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 1 0 0 0
5 0 0 1 1 0 1 0 0 0 0 0 1 0 0
6 0 0 1 1 1 0 0 0 0 0 0 0 1 0
7 0 0 1 1 1 1 0 0 0 0 0 0 0 1
3 TO 8 DECODER 62
Table 17.1
TEST NO: 17
3 TO 8 DECODER TEST

1- Y-0020-02 Testing set
Figure 17.2
3 TO 8 DECODER 63
Steps of the test :
INPUTS OUTPUTS
NUMBER LE’ E2’ E1 D2 D1 D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 X x x x X
X 1 X X x x
x x 0 x x x
0 0 0 1 0 0 0
1 0 0 1 0 0 1
2 0 0 1 0 1 0
3 0 0 1 0 1 1
4 0 0 1 1 0 0
5 0 0 1 1 0 1
6 0 0 1 1 1 0
7 0 0 1 1 1 1
Table 17.2
3 TO 8 DECODER 64
NAME OF THE TEST:
DECIMAL DECODER FROM BCD TO 10
Decimal decoder from BCD to 10 circuits are 74x42, 74x45 and 4028 integrates.
Inputs of the integrate of 74x42 are active “1”, outputs are active “0”. Both inputs and
outputs of the integrate of 4028 are active “1” dir. They transfer the BCD code coming
from 4 lines to DECIMAL information.
When the information of 8421 duality is applied, numbers between the information
of 0000 and 1001 are transmitted to output.
In the figure below, foot connections of integrate of 4028 and table of accuracy are
seen.
Figure 18.1
INPUTS OUTPUTS
NO D C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 1 0 0 0 0 0 0 0 0
2 0 0 1 0 0 0 1 0 0 0 0 0 0 0
3 0 0 1 1 0 0 0 1 0 0 0 0 0 0
4 0 1 0 0 0 0 0 0 1 0 0 0 0 0
5 0 1 0 1 0 0 0 0 0 1 0 0 0 0
6 0 1 1 0 0 0 0 0 0 0 1 0 0 0
7 0 1 1 1 0 0 0 0 0 0 0 1 0 0
8 1 0 0 0 0 0 0 0 0 0 0 0 1 0
9 1 0 0 1 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Table 18.1
BCD TO 10 DECODER 65
TEST NO: 18
DECIMAL DECODER FROM BCD TO 10
Elements to be used in the test:

1- Y-0020-02
Figure 18.2
Steps of the test:
1- Apply the power by installing the circuit as shown in figure 18.2.

2- Apply the situations on the table.
3- Note the occurring situations on the table by observing the output.
4- Is the coding achieved according to the results on the table18.2?
INPUTS OUTPUTS
NO D C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
0 0 0 0 0
Table 18.2
NAME OF THE TEST:
7 SEGMENT DISPLAY
TEST PURPOSES:
A- Observation of 7 Segment Display,
B- Observation of operation systems,
C- To know HEXADECIMAL DECODER.
PRIOR KNOWLEDGE :
Figure 19.1
Seven-segment display is the extended version of a simple Led. By using 7 pieces
of Led each piece of which is like short sticks, depending on which part is stimulated,
letters from A to F with numbers from 0 to 9 (numbers of 16) are attained. (Figure19.1)
Figure 19.2
Seven-segment indicators are produced as common anoded and common

cathoded for using with different circuits. The structure of indicator with common anode
and cathode is shown in figure 19.2. Here, cathode of each Led is connected commonly
while anodes are independent from each other. Common cathode (K) is connected to
the soul. While the Leds whose anodes are given positive voltage illuminate, other Leds
are dim. Each anode should be connected circuit delimiter resistance. For example; if a,
b, c, d, g edges are connected to positive voltage on resistances, the number 3is
attained.
7 SEGMENT DISPLAY DECODER 68

Figure 19.3
Seven-segment indicator can show 4-bit binary datum as BCD and 16th number
with the help of suitable Decoder / Driver (Figure 19.3). Decoder / driver is an
integrated circuit including jointed logic circuit. This circuit converts the 4-bit binary
input to a 7-bit code used to drive the seven parts of the indicator.
In our test circuit, 2 decoder circuits which can drive common anode and cathode
are used. While the logic is the same for both of the two, both two circuits are included
in the set to let the outputs be opposite to each others.
7447 gives negative output. 4511 integrate, on the other hand, gives positive
output. Both integrates convert the BCD code into a 7 segment display input.
Output accuracy table of the two integrates is given in the table below.
INPUTS OUTPUTS
7447 4511
BCD A B C D
a b c d e f g a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1
1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 1
2 0 1 0 0 1 1 0 1 1 0 1 0 0 1 0 0 1 0
3 1 1 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 0
4 0 0 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0
5 1 0 1 0 1 0 1 1 0 1 1 0 1 0 0 1 0 0
6 0 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0
7 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1
8 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
9 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0
Table 19.1

In our test set, there is also a 2-bit decoder applying the 8421 information entered
into the input to 7 segment display by HEXADECIMAL decoding.
Figure 19.4
th
The circuit is a 16 system decoder/driver. In this circuit input, the number wanted to
be created on the indicator is applied in the form of Binary Coded Decimal. The
circuit, by transforming the code applied to its input transforms into a suitable form to
be applied to 7th indicator input. For example; to attain the number of “1” on the
indicator, “0001” is applied into the circuit input. On the output, (g-f-e-d-c-b-a)
"0000110" is attained. Thus, the anodes of the sticks of b-c Leds give light as they took
(+). By this means, the number 1 is formed on the indicator.
The set of test is composed of 2 Letter-Number reader circuit and 2 seven-
segment Led indicators. Below is the table of accuracy of this circuit.
INPUTS OUTPUTS
DEC HEX A B C D a b c d e f g
0 0 0 0 0 0 1 1 1 1 1 1 0
1 1 1 0 0 0 0 1 1 0 0 0 0
2 2 0 1 0 0 1 1 0 1 1 0 1
3 3 1 1 0 0 1 1 1 1 0 0 1
4 4 0 0 1 0 0 1 1 0 0 1 1
5 5 1 0 1 0 1 0 1 1 0 1 1
6 6 0 1 1 0 0 0 1 1 1 1 1
7 7 1 1 1 0 1 1 1 0 0 0 0
8 8 0 0 0 1 1 1 1 1 1 1 1
9 9 1 0 0 1 1 1 1 0 0 1 1
10 A 0 1 0 1 1 1 1 0 1 1 1
11 B 1 1 0 1 0 0 1 1 1 1 1
12 C 0 0 1 1 1 0 0 1 1 1 1
13 D 1 0 1 1 0 1 0 1 1 1 1
14 E 0 1 1 1 0 1 1 1 1 0 1
15 F 1 1 1 1 1 0 0 0 1 1 1
Table 19.2

TEST NO: 19
TEST OF 7 SEGMENT DISPLAY WITH COMMON ANODE

1- Y-0020-2 Test Set.
Figure 19.5

Steps of the test:
1- Apply the power by installing the circuit to BREADBOARD on the set as shown in
the figure 19.5. Look at figure 19.2 for Display connection.
2- First, apply the L switch with 470 OHM resistance to the common point by
attaching common ANODE display.
3- Apply the positions of switches according to the situations on the table.
4- Save the occurring situations on the table by observing the output.
5- Has the display output been attained according to the results on Table19.3?
INPUTS DISPLAY
a b c d e f g OUTPUT
0 0 0 0 0 0 1 0
1 0 0 1 1 1 1 1
0 0 1 0 0 1 0 2
0 0 0 0 1 1 0 3
1 0 0 1 1 0 0 4
0 1 0 0 1 0 0 5
1 1 0 0 0 0 0 6
0 0 0 1 1 1 1 7
0 0 0 0 0 0 0 8
0 0 0 1 1 0 0 9
Table 19.3

TEST NO: 20
TEST OF 7 SEGMENT DISPLAY WITH COMMON CATHODE

1- Y-0020-2 Test Set.
Figure 20.1

Steps of the test:
1- Apply the power by installing the circuit to BREADBOARD on the set as shown in
the figure 20.1. Look at figure 20.1 for Display connection.
2- First, apply the L switch with 470 OHM resistance to the common point by
attaching common CATHODE display.
3- Apply the positions of switches according to the situations on the table.
5- Has the display output been attained according to the results on Table19.3?
INPUTS DISPLAY
a b c d e f g OUTPUT
1 1 1 1 1 1 0 0
0 1 1 0 0 0 0 1
1 1 0 1 1 0 1 2
1 1 1 1 0 0 1 3
0 1 1 0 0 1 1 4
1 0 1 1 0 1 1 5
0 0 1 1 1 1 1 6
1 1 1 0 0 0 0 7
1 1 1 1 1 1 1 8
1 1 1 0 0 1 1 9
Table 20.1

NAME OF THE TEST:
DECODER FROM BCD TO 7 SEGMENT DISPLAY
GENERAL INFORMATION:
Decoders from BCD to 7 segments are made with two reasons in practice. One of
these is the reason of COOMON ANODE and the integrate of 7447 works with this logic.
Normally, apart from the edges of input and output, LT, RBI and BI/RBO edges are also
available for controlling. In our test circuit, normal operation position of the circuit is
applied by pulling these edges to the level of VCC.
The figure of connection is given according to the ISIS program in the circuit
below.
Figure 21.1
The other of these is the reason of COMMON CATHODE and the integrate of 4511
works with this logic. Normally, in this integrate, apart from the edges of input and
output like 7447, edges of LT, RBI and BI/RBO are also available for control. In our test
circuit, these edges are connected as suitable for the normal operation position of the
circuit.
The figure of connection is given according to the ISIS program in the circuit
below.
Figure 21.2

TEST NO: 21
TEST OF COMMON CATHODE DECODER FROM BCD TO 7 SEGMENT
DISPLAY

1. Y-0020-02 Test Set.
Figure 21.3

Steps of the test:
1- Apply the power by installing the circuit as shown in the figure 21.3.
2- Apply the situations on the table.
4- Has the coding been achieved according to the results on table 21.1?
INPUTS OUTPUTS
DEC HEX A B C D a b c d E f g
0 0 0 0 0 0
1 1 1 0 0 0
2 2 0 1 0 0
3 3 1 1 0 0
4 4 0 0 1 0
5 5 1 0 1 0
6 6 0 1 1 0
7 7 1 1 1 0
8 8 0 0 0 1
9 9 1 0 0 1
Table 21.1

TEST NO: 22
TEST OF DECODER FROM HEXADECIMAL TO 7 SEGMENT

1. Y-0020-02 Test Set.
Figure 22.1

Steps of the test:
1. Install the circuit as shown in figure 22.1.
2. Position the switches between 1 and 8 to “0”, apply the power.
3. As indicated in table 22.1, set the switches to let it show the numbers and
digits.
4. Has each of the segments been controlled by its corresponding switch during
the operations?
5. Are the results of the operation suitable with the table?
Yes . Suitable.
Table to be expected
INPUTS OUTPUTS
DEC HEX D1 C1 B1 A1 D0 C0 B0 A0 DEC HEX

0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 1 0 0 0 1 1 1
2 2 0 0 1 0 0 0 1 0 2 2
3 3 0 0 1 1 0 0 1 1 3 3
4 4 0 1 0 0 0 1 0 0 4 4
5 5 0 1 0 1 0 1 0 1 5 5
6 6 0 1 1 0 0 1 1 0 6 6
7 7 0 1 1 1 0 1 1 1 7 7
8 8 1 0 0 0 1 0 0 0 8 8
9 9 1 0 0 1 1 0 0 1 9 9
10 A 1 0 1 0 1 0 1 0 10 A
11 B 1 0 1 1 1 0 1 1 11 B
12 C 1 1 0 0 1 1 0 0 12 C
13 D 1 1 0 1 1 1 0 1 13 D
14 E 1 1 1 0 1 1 1 0 14 E
15 F 1 1 1 1 1 1 1 1 15 F
Table 22.1

NAME OF THE TEST:
TEST OF THE MULTIPLEXES (MUX)
TEST PURPOSES:
A- Examining the circuit of Multiplexes (MUX),
B- Observing the operation systems,
C- Recognizing the integrate of 4051 MULTIPLEXER-DEMULTIPLEXER.
PRIOR KNOWLEDGE:
Numerical multiplex circuit is the circuit transferring, in a fixed order, the
numerical information on more than one input to a single output; numerical
demultiplex circuit is the circuit transferring, in a fixed order, the numerical
information entered from a single input to more than one outputs.
The integrate of 4051 is MUX-DEMUX integrate with 8 channels. It can work

in both ways. The figure of foot connection and figure of interior connection with the
table of accuracy are seen in the figure below.
Figure 23.1
MUX-DEMUX 80
When INH input of 4051 is at the level of "1", whatever is the selection inputs,
outputs are at the level of "0". INH control works as a authorization signal. C, B, A
selection lines select the inputs to be multiplied and applied to the output. When the
INH input is at the level of "0" (authorization), the information at the input selected
according to the condition of C, B, A selection lines is transferred to Y output. W
output gives the opposite (complementary) of the information at the Y output.
For example;
If the inputs of Strobe "0", C, B, A are "0 1 1 " (C=0, B=1, A=1), the
information at D3 input is seen at Y output. If the inputs of C, B, A are "1 1 1", the
information on D7 input is transferred to output.
This integrate, numerically, can be used at numerical communication by

transforming parallel information into serial information.
INHIBIT SELECTION OUTPUTS

INH C B A Y W
1 x x x 0 1
0 0 0 0 D0 D0’
0 0 0 1 D1 D1’
0 0 1 0 D2 D2’
0 0 1 1 D3 D3’
0 1 0 0 D4 D4’
0 1 0 1 D5 D5’
0 1 1 0 D6 D6’
0 1 1 1 D7 D7’
Table 23.1
MUX-DEMUX 81
TEST NO : 23
NAME OF THE TEST: EXAMINATION OF THE INTEGRATE OF 4051
MULTIPLEXER ( MUX )
Test sets to be used:

Figure 23.2
MUX-DEMUX 82
Steps of the test :
1. Apply the power by installing the circuit as shown in figure 23.2.

2. Position the switches as (D0-D7) and (A-C) "0". What is Y output?
As the position of the switches connected to SELECT edge are I=0, J=0 and K=0,
the information connected to D0 input is transferred to Y output. As the information on
D0 is "0", the information on Y output is also "0".
3. Position the switches on C, B, A as "1". Make D7 (H) switch as “1”. What is the
situation of outputs?
As SELECT edges are "1 1 1", D7 information input is selected. The information on
D7 information input is transferred to Y output. Y output becomes "1".
4. Fill the table according to the situations on Table 23.2.
SELECTION
INH INFORMATION INPUTS OUTPUT
EDGES
PERMISSION D0 D1 D2 D3 D4 D5 D6 D7 C B A Y
1-0 1 0 0 0 0 0 0 0 0 0 0 1
2-0 0 1 0 0 0 0 0 0 0 0 1 1
3-0 0 0 1 0 0 0 0 0 0 1 0 1
4-0 0 0 0 1 0 0 0 0 0 1 1 1
5-0 0 0 0 0 1 0 0 0 1 0 0 1
6-0 0 0 0 0 0 1 0 0 1 0 1 1
7-0 0 0 0 0 0 0 1 0 1 1 0 1
8-0 0 0 0 0 0 0 0 1 1 1 1 1
Table 23.2
5. Make INH input as "1". Position the switches to positions in 6th step in Table
23.2. Explain the results.
While the output is “1” on Table 23.2, Y output became “0” upon INH is made "1".
Because, when INH input is "0", the information suitable to inputs are transferred to
output as being suitable to selection switches. If INH input is "1", whatever the inputs
are, outputs are always "0".(Y output)
6. Does the operation principle of MUX given in the prior knowledge conform with
the results attained on Table 23.2?
Conforms.
MUX-DEMUX 83
NAME OF THE TEST:
EXAMINATION OF 8-BIT DEMULTIPLEX (DEMUX) CIRCUITS
TEST PURPOSES:
A- Examining DEMUX circuits

B- Examining 4051 integrate operating as DEMUX.
PRIOR KNOWLEDGE:
On MUX circuits, it was aimed, according to the positions of information selective
switches, to select only one of the information, from the output, given from 8 pieces of
inputs.
But on DEMUX circuits, the information given from the input is distributed to
outputs according to input row. So that, the information is distributed to outputs in the
order in which it came. This order heads towards the output according to the situation
of selection edges.
The integrate of 4051 also operates as DEMUX. On our test circuit, again 4051
integrate was used.
Below is the DEMUX circuit output table.
INH DATA SELECTION EDGES INFORMATION OUTPUTS

PERMISSION Y C B A D0 D1 D2 D3 D4 D5 D6 D7
0 1 0 0 0 1 0 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 1 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 1 0 0 0
0 1 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0
0 1 1 1 1 0 0 0 0 0 0 0 1
Table 24.1
MUX-DEMUX 84
TEST NO: 24
NAME OF THE TEST: USAGE OF 4051 INTEGRATE AS
DEMULTIPLEXER
Test set used in the test:

Figure 24.1
MUX-DEMUX 85
Steps of the test:
1. Apply the power by installing the circuit as shown in Table 24.1.
2. Make INH' input (A switch) as "0”. Program the Table 24.2 according to the
situations of D, E and F switches and save the outputs on the table.
SELECTION
INH DATA INFORMATION OUTPUTS
EDGES
0 1 0 0 0 1 0 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 1 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 1 0 0 0
0 1 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0
0 1 1 1 1 0 0 0 0 0 0 0 1
Table 24.2
4. How is 4051 operating according to the results on Table 24.2? Explain shortly.
4051 is operating as DEMOX according to the results on Table. According to the

situation of selected inputs, one of 8 outputs is selected and this output transfers only
the information on D to output.
MUX-DEMUX 86
NAME OF THE TEST:
EXAMINATION OF SERIAL DATA COMMUNICATION
TEST PURPOSE: Examining that the data are sent in a serial way.
PRIOR KNOWLEDGE:
In many applications, results come out while transferring analog information.

Transforming and transferring analog information to the form of numerical information
is both cheaper and more secure.
Transferring numerical information is done in two ways as serial and parallel.
While serial transfer is slower, it requires less line. For this reason, it costs less.
Parallel transfer is faster. (The number of information sent at the same time is more).
But it rises the cost as it requires more lines. At the places where speed is not
important, serial transfer is preferred as being cheap.
4520 (Binary Counter) is used to address synchronically MUX and Addressable

Latch. One of the 8 inputs of Mux is selected at the same time and the output of the
Addressable Latch corresponding to selected input is selected with Binary Counter. The
information on 8-bit binary form at the input of Mux comes to the input of 4051 as
bits; and is again transferred to the output of 4051 in conformity with the order at the
input of Mux.
MUX-DEMUX values are seen in the tables below.
INH INFORMATION INPUTS SELECTION EDGES OUTPUT

0 1 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 0 0 1 0 0 0 0 0 1 1 1
0 0 0 0 0 1 0 0 0 1 0 0 1
0 0 0 0 0 0 1 0 0 1 0 1 1
0 0 0 0 0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0 1 1 1 1 1
SELECTION
INH INPUT INFORMATION OUTPUTS
EDGES
0 1 0 0 0 1 0 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 1 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 1 0 0 0
0 1 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0
0 1 1 1 1 0 0 0 0 0 0 0 1
MUX-DEMUX 87
Table 25.1 and Table 25.2
TEST NO : 25
NAME OF THE TEST: EXAMINATION OF SERIAL DATA COMMUNICATION
Test set used in the Test:

Figure 25.1
MUX-DEMUX 88
Steps of the test :
1. Apply the power by installing the circuit as shown in figure 25.1.

2. Make both of the INH edges of the integrates of 4051 as “0”.
3. What is the reason that Q4 output of 4520 Binary Counter is connected to MR
edge?
It is used to reset the counter when counting reaches to 8 while counting from 0
to 7. To make 8 counting in total.
4. Selection edges (A, B, C) of MUX and DEMUX are connected to the outputs of
Binary Counter as common. Write the reason.
This situation is used to let MUX and DEMUX to operate synchronically.
5. Make the input switches as “1”. Explain the result by observing the outputs of
MUX.
In this situation, the information at the 8 inputs of MUX is respectively selected by
the counter and is transferred to Y output. At the same time, the outputs of 4051 are
also selected as parallel with MUX by the counter and the 8-bit information coming
from Y comes respectively to Y input of 4051 and is respectively placed on the selected
outputs.
6. Have the data on Table 25.3 and Table 25.4 been attained? In this situation,
was 8-bit datum transferred serially according to the occurring results?
Attained, 8 bit datum was transferred serially.
SELECTION
INH INFORMATION INPUTS OUTPUT
EDGES
0 1 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 0 0 1 0 0 0 0 0 1 1 1
0 0 0 0 0 1 0 0 0 1 0 0 1
0 0 0 0 0 0 1 0 0 1 0 1 1
0 0 0 0 0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0 1 1 1 1 1
SELECTION
INH INPUT INFORMATION OUTPUTS
EDGES
0 1 0 0 0 1 0 0 0 0 0 0 0
0 1 0 0 1 0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 1 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 1 0 0 0
0 1 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0
0 1 1 1 1 0 0 0 0 0 0 0 1
Table 25.3 and Table 25.4
MUX-DEMUX 89
NAME OF THE TEST:
EXAMINATION OF TOTAL ADDER AND EXTRACTOR
TEST PURPOSES:
A- Examining total adder,
B- Observing the operation systems of the integrate of 4008,
C- Examining total extractor.
PRIOR KNOWLEDGE:
This can be made by extracting the number as dual, get the complementary
2 of the output number and adding to the extracted one. Complementary 2 can be had
by getting complementary 1 and adding 1. To make the operation of A-B, we complete
4-bit of B and sum up with 4-bit of A then we add “1” with input in hand.
For the substruction, in case the omitted one is big, the true answer can be found
by getting the complementary 2 of the result.
For example;
Examine the display of the number of +14 and -14 via the method of
complementation to 2 in Table 26.1.
DECIMAL NUMBER BINARY NUMBER
+14 00001110
-14 11110001
Table 26.1
FULL ADDER 90
Figure 26.1
4008 integrate is a total adder integrate with 16 pin and it can be identified as a
function integrate. Total adder of 4008 finds the sum of two numbers of 4- bit and bit of
one in hand input (Co).
In the process, by summing the numbers of A1, A2, A3, A4 (8 4 2 1) and B4, B3,
B2, B1 (8 4 2 1)
The total (result) is attained in dual form as S1, S2, S3, S4 and Co (in hand
output).
With the integrate of 4008, BCD or numbers of 16 base can be summed by using
numbers of 4 bit.
Besides, integrate of 4008 can be arranged as extractor by being used with EXOR
doors as shown in Figure 26.1.
FULL ADDER 91
TEST NO: 26
NAME OF THE TEST: EXAMINATION OF TOTAL ADDER
Test set to be used:

1- Y-0020-02 Test set
Figure. 26.2
FULL ADDER 92
Steps of the test:
1. Install the circuit as shown in Figure. 26.2.

2. Apply the power by positioning all the switches as "0". Display should also
be"0".
3. Position the switches between A and D as 0010 (D=0, C=0, B=1, A=0) and
position the switches between I and L as 0110 (E=0, F=1, G=1, H=0). What is the
value shown on Display and situation of Co?
On the Display, sum of the binary values of 0010 and 0110 are available.”8” is
available as result HEX. Co (in hand) output is "0". That is, on the second display, “0”
is seen.
4. Position the switches between A and D as 1010 and position the switches
between E and H as 1001. What is the value seen on output? Has the in hand output
been formed?
AS there is the value of 3 as HEX. on the display and it formed an in hand, Co is

illuminated. It corresponding as DECIMAL is 19.
5. Fill the output both as HEX. and DECIMAL by positioning the switches between
A and H according to the values on Table 26.2.
6. Make Co in hand input as "1". Position the switches between A and D as 0011
and position the switches between E and H as 0001.What is the value seen on Display?
Why?
The value of 5 (DECIMAL 5) is seen as HEX. Because the sum of 0011 and 0001 is
"4" and there is one in hand; so the total is "5".
BINARY HEXADECIMAL Co RESULT

1.NUMBER 2.NUMBER 1.NUMBER 2.NUMBER (IN DECIMAL HEXADECIMAL
HAND)
0000 0000 0 0 0 0+0=0 0

0001 0000 1 0 0 1+0=1 1
0001 0001 1 1 0 1+0=2 2
0010 0001 2 1 0 2+1=3 3
0011 0110 3 6 0 3+6=9 9
0111 0111 7 7 0 7+7=14 E
1001 0011 9 3 0 9+3=12 C
0111 1111 7 F 1 7+15=22 6
1010 1011 A B 1 10+11=11 5
1100 1110 C E 1 12+14=26 A
1101 0001 D 1 0 13+1=11 E
1111 1111 F F 1 15+15=30 E
Table 26.2
FULL ADDER 93
TEST NO: 27
NAME OF THE TEST: USE OF 4008 AS HALF ADDER AND HALF EXTRACTOR
VIA MODE SELECTION
Test sets to be used:

1- Y-0020-01 Digital Test set,
2- Y-0020-02 Digital Test set.
Figure 27.1
FULL ADDER 94
Steps of the test:
1. Install the circuit as shown in Figure 27.1.Apply the power by joining the
Gnd’s of the sets.
2. Make M=0 (L switch). Make A4, A3, A2, A1=1 0 0 1 and B4, B3, B2, B1= 0 1 0
1. What is the situation of the outputs? Has in hand been formed? What did 4008 work
like?
It is S4, S3, S2, S1=1 0 0 0. In hand (Co) bit is not formed.

The circuit worked as half adder.
3. M=0. Make A4, A3, A2, A1=1 0 0 1, B4, B3, B2, B1= 1 0 0 1. What is the
situation of outputs and what is in hand output?
It is S4, S3, S2, S1= 0 0 1 0. In hand (Co) bi is formed.(As the total exceeded
15.)
4. How has 4008 worked according to the results above? Why?
4008 has worked as half adder. Because, in hand input was made as Co = 0.
Use of 4008 as half extractor:
5. Make M=1 A4, A3, A2, A1 = 1 0 0 0, B4, B3, B2, B1 = 0 1 0 1. What is the
situation of outputs and BORC output (Co)?
It is S4, S3, S2, S1= 0 0 1 1. BORC (Co) bit is formed. Result=3 and Co=”1”
6. Make M=1. Make A4, A3, A2, A1= 0 1 0 0, B4, B3, B2, B1= 0 1 1 1. What is
the situation of outputs and BORC output (Co)?
It is S4, S3, S2, S1= 0 0 1 1. BORC (Co) bit is not formed. Result=3 and Co=”0”
FULL ADDER 95
NAME OF THE TEST:
EXAMINATION OF COMPARATORCIRCUITS
TEST PURPOSES:
A- To know the comparative circuits and to verify its experimental function,

B- To examine various features.
C- To know comparative integrates.
PRIOR KNOWLEDGE:
Comparing two numbers is a process which determines whether one of the

numbers is equal to the other one, is smaller than the other or is bigger than it. Bigness
comparator is a combined circuit comparing two numbers like A and B and determining
their relative bigness. The result of the comparison is determined by three dual
variables showing the situation of A>B, A<B and A=B.
Let’s consider two numbers each of which has four digits and like A and B.
Coefficients of the numbers with their decreasing values will be:
A= A3 A2 A1 A 0
B= B3 B2 B1 B0.
If all valanced place pairs are equal, that is they are A3 = B3, A2 = B2, A1= B1, A 0
= B0, the two numbers are equal.
To designate whether A or B is bigger or smaller, beginning from the most
valanced position, relative bigness of valanced digit pairs are looked. If the two digits
are equal, we compare the next low valanced digit pair. This comparison continues till
reaching an unequal place pair.
If the related digit of A is “1” and the related digit of B is “0”, A>B result is
reached; if the related digit of A is “0” and related digit of B is “1”, A<B result is
reached. Shortly; comparator circuits compare binary numbers. They designate
whether Binary numbers are equal to each other and their smallness, bigness
situations.
Figure 28.1
COMPARATOR 96
Foot connections of the integrate of 74 HC 85:
While cascading inputs are “x” (not important):

If A word is bigger than B word; A>B output is “1” ,
If A word is smaller than B word; A<B output is “1”,
If A word is equal to B word; A=B output is “1”.
If A word is equal to B word, in this case, outputs are positioned according to the
situations of cascade inputs. For example, while compared A word is equal to B word
and A>B input from cascade inputs is “1”, others are (AB output is “1” and other outputs are “0”.
CASCADING
COMPARED INPUTS OUTPUTS
INPUTS
A3,B3 A2.B2 A1,B1 A0,B0 A>B AB AB3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2<B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L
A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L
A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H
A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H
A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L
A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L
Table 28.1
The table above is the table of accuracy of the comparator integrate of 74 HC 85.
74 HC 85 comparator integrate is an amplitude comparator integrate.
COMPARATOR 97
TEST NO: 28
NAME OF THE TEST: EXAMINATION OF COMPARATOR CIRCUITS
Set and measurement devices used in the test:
1- Y-0020-02 Test set
Figure 28.2
COMPARATOR 98
Steps of the test:
1- Install the circuit in the figure 28.2. Position all switches as passive (“0”). After
controlling, apply power to the system.
2- A, C, E, G switches are the inputs comparing A word as a representative; B, D,

F, H switches are the inputs comparing B word as a representative. J, K, L switches will
be used for cascade inputs.
3- Position A3 as “1” and B3 as “0” while all switches are positioned as “0”.
Observe the situation of the outputs. Explain the result.
A > B output is “1”. A word is bigger than B word.
4- While A and B words (A3, A2, A1, A0 and B3, B2, B1, B0) are equal (all of them are
“1” ), make A > B from cascade inputs as “1” and the others as “0”. What has the
situation of outputs been?
A > B output is “1”.
Observe the situation of outputs by applying inputs on Table 28.2. Do the outputs
confirm Table 28.2?
Yes, confirms.
COMPARED INPUTS CASCADING

OUTPUTS
INPUTS
A3,B3 A2.B2 A1,B1 A0,B0 A>B AB AB3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2<B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L
A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L
A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H
A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H
A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L
A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L
Table 28.2
COMPARATOR 99
NAME OF THE TEST:
UNIVERSAL SHIFT REGISTER
TEST PURPOSES:
A- To learn how SHIFT-REGISTERS are used as shifter to right.
B- To learn how SHIFT-REGISTERS are used as shifter to left.
C- To learn the principles of Parallel input, parallel output.
D- To know the integrate of 74 HC 194 L-R SHIFT REGISTER.
PRIOR KNOWLEDGE:
Shift registers have the feature of storing information in Binary form and shifting
information. Thanks to this feature, they are used at the processes of storing
information on computer, binary adder, extractor, keeping information and transferring
information. At the same time, they are also used at multiplying and dividing binary
numbers. Process of multiplying and dividing is a way of shifting for binary numbers.
For example; if a value on binary form is shifted to left, that value gives the same
result as multiplied with two. If a value on binary form is shifted to right, that value
gives the result of two fractions.
Shift registers are digital circuits formed by adding more than one FF consecutively
(output of one, input of the other) and they have common clock (CLK). Information
transfer is made synchronic with clock pulses. The reason that they operate on a
common clock is to enable the transfer of information (l or 0) from a FF to the other to
be happen at the same time with all FFs. Information transfer, depending on the
feature of register, happens at the rising or decreasing edge of clock sign.
Shift registers are classified according to the number of bits they put to operation,
the type of input-output processes and direction of shifting of bits.
Number of FFs on a register depends on the number of stored or processed bits
(Each FF stores1-bit information). Like 4 bit, 8 bit, l6 bit.
Figure 29.1
SHIFT REGISTER 100

Registers have 4 types of input-output (I/O) relations.
a) Serial input / Serial output (SISO)

b) Serial input/ parallel output (SIPO)
c) Parallel input/ parallel output (PIPO)
d) Parallel input/ serial output (PISO)
Movement way of information in the structure of register:

Left shift register
Right shift register
Left shift register with 4-bit and serial input/parallel output featured is seen on
figure 29.2.
Figure. 29.2
Operation principle of the circuit is to shift the information on the input to one left
at each clock pulse.
Make all FF outputs “0” by applying “0” to deletion input. Later on, make DATA
input “1”. At the first clock pulse, (at the rising or decreasing edge) the information of
“1” at the information input, by passing from the first FF, (QD output is LSB, QA output
is MSB) make the information at the second clock pulse "0", at the second clock pulse,
QC = 1, QD = 0. Make the information input “1” at the third clock pulse, When third
clock pulse is applied, QB = l, QC = 0, QD = 1. Make information input “1” at the fourth
clock pulse, when fourth clock pulse is applied, QA=1, QB=0, QC=1, QD=1. Thus, at
the end of four clock pulses, first information input reaches fourth FF output.
As shift registers can separately be formed with combined circuits, they can
also be available as combined circuits by themselves.
74HC194 is available on a single combined circuit as a Universal shift register (it is

4 bit).
S0 and S1 at the Universal register are mode selection inputs. There are 4 types of
mode selection inputs. These are seen on Table 29.1. SRSI input is serial right shift
register input, SLSI input is serial left shift register input. Inputs of D0, D1, D2, D3 are
parallel information inputs; outputs of QA, QB, QC, QD are parallel information outputs.
MR input is used to clean the outputs; that is to make all of them "0". QD output is also
used as a serial output point.
SHIFT REGISTER 101

INPUTS OUTPUTS
MOD SERIAL PARALLEL
MR CLK QA QB QC QD
S0 S1 LEFT(L) RIGHT(R) A B C D
0 X X X X X X X X X 0 0 0 0
1 X X 0 X X X X X X QA QB QC QD
1 1 1 1 X X A B C D A B C D
1 0 1 1 1 X X X X X QB QC QD 1
1 1 0 1 X 1 X X X X 1 QA QB QC
Table 29.1
On Table 29.1, foot explanations of Universal shift register are seen. When clear
input is active (at 0), whatever the other foot inputs and mode inputs are, outputs are
zeroed. When clear input is "1", shift register acts according to mode inputs. As long as
CLK sign does not come, outputs keep their prior positions.
When S0 and S1 inputs are 1-0, shift register works as right shift.
Input is made from SRSI point.
When S0 and S1 inputs are 0-1, shift register works as left shift.
Input is made from SLSI point (the information to be shifted).
When S0 and S1 inputs are 1-1, shift register makes parallel installation.
SHIFT REGISTER 102

TEST NO: 29
NAME OF THE TEST: RIGHT SHIFT REGISTER
Set to be used in the Test:

1- Y-0020-02 Test set,
Figure 29.3
SHIFT REGISTER 103

Steps of the test:
1. Install the circuit as shown in Figure 29.3. Apply the power.

2. Enable S0=1 (K switch), S1=0 (J switch) and prepare the circuit as right shift
register. The information has been prepared in a way to move from QA to QD.
3. Make all outputs as “0” by making MR "0" (G switch) (deletion:0). Then, make
deletion inactive by making MR "1".
4. Make the right shift input of SR register (F switch) "1".
5. Send pulse for 4 times via Puls beat (40194 positive edge will be triggered).
Has the information been taken on register? (Observe the result on the Leds)
Yes, the information is being displayed on LEDs.
6. Find in which way is the flow of information.

Information register is moving to right in it. After the information gets out of
information register, it does not return. Because there is no feedback.
INPUTS OUTPUTS
MODE SERIAL PARALLEL
MR CLK Q0 Q1 Q2 Q3
S0 S1 LEFT(SL) RIGHT(SR) A B C D
0 X X X X X X X X X 0 0 0 0
1 1 1 1 X X A B C D A B C D
1 0 1 1 1 X X X X X QB QC QD 1
1 1 0 1 X 1 X X X X 1 QA QB QC
Table 29.2
SHIFT REGISTER 104

TEST NO: 30
NAME OF THE TEST : LEFT SHIFT REGISTER
Set to be used in the Test:

1- Y-0020-02 Digital Test set.
Figure 30.1
SHIFT REGISTER 105

Steps of the test:

2. Make S0=0 (K switch), S1=1 (J switch) and prepare the circuit as right shift
register. The information has been prepared in a way to move from QD to QA.
3. Make all outputs as “0” by making MR "0" (G switch) (deletion: 0). Then, make
deletion inactive by making MR "1".
4. Make the right shift input of SL register (E switch) "1".
5. Send pulse for 4 times via Puls beat (74HC194 positive edge will be triggered).
Has the information been taken on register? (Observe the result on the Leds)
Yes, the information is being displayed on LEDs.
6. Find in which way is the flow of information.

Information register is moving to left in it. After the information gets out of
information register, it does not return. Because there is no feedback.
INPUTS OUTPUTS
MR CLK Q0 Q1 Q2 Q3
0 X X X X X X X X X 0 0 0 0
1 1 1 1 X X A B C D A B C D
1 0 1 1 1 X X X X X QB QC QD 1
1 1 0 1 X 1 X X X X 1 QA QB QC
Table 30.1
SHIFT REGISTER 106

TEST NO: 31
NAME OF THE TEST: SHIFT REGISTER WITH PARALLEL INPUT- PARALLEL
OUTPUT
Set to be used in the test:

1- Y-0020-2 Test set.
Figure 31.1
SHIFT REGISTER 107

Steps of the test:

2. Make S0=1 (K switch), S1=1 (J switch). (Prepare the circuit in the form of
parallel input/ parallel output)
3. Zero the outputs by making MR "0". Then, make MR "1"; that is make it
inactive.
4. Set the switches of A, B, C, D to enable D0 = 0, D1 = 1, D2 = 1, D3 = 0.
5. Press the Pulse button. Has the information you had set at the input been
transferred to the output?
Yes, the information at the input is exactly seen on Leds. The information was
transferred in parallel.
6. Retry the test by setting the input switches to various situations.
INPUTS OUTPUTS
MR CLK Q0 Q1 Q2 Q3
0 X X X X X X X X X 0 0 0 0
1 1 1 1 X X A B C D A B C D
1 0 1 1 1 X X X X X QB QC QD 1
1 1 0 1 X 1 X X X X 1 QA QB QC
Table 31.1
SHIFT REGISTER 108

NAME OF THE TEST:
RAM (RANDOM ACCESS MEMORY)
TEST PURPOSES:
A- To attain information on memories,
B- To observe the operation systems,
C- To know 6116 RAM integrate.
PRIOR KNOWLEDGE:
Memory is a saving system enabling to keep data or interim information being
formed during various processes and result information in a dual structure.
Memory types are divided into two as internal memory and external memory.
Internal memory is one of the main parts used inside the computer. For example;
Magnetic memories, semi conductor memories etc. External memories are the ones
assisting internal ones. For example; punched cards, disc, floppy etc.
Semi conductor memories are divided into two:
1- RAM (Random Access Memory)
2- ROM (Read Only Memory)
RAM is a type of memory which can be both read and written. When supply
voltage is stopped, the information inside it is lost. ROM is only a readable memory
type and when supply voltage is stopped, the information inside it is not lost.
ROM memories have the following types: programmable PROM (Programmable
Read Only Memory), programmable by being deleted with electricity EEPROM or
E2PROM (Electrically Erasable Programmable Read Only Memory) and
programmable being deleted with ultraviolet light EPROM (Erasable PROM). Besides,
there is also a type named MASK programmed ROM and this is created by the
manufacturer on order via programming the storage areas.
Internal structure of a RAM of 16 x 8 is seen in Figure 32.1.
Figure 32.1
RAM-6116 109
As it has 4 inputs, it means it has addressable register of 24 =16. 16 different
situations can be applied to the input in total. CS (Chip select) input is an integrated
selection input and when it is made '1', neither any information can be saved into RAM
or any information can be read from RAM. This integrate can not be used. When the
point of CS is made '0', both any information can be saved into RAM and the
information inside the RAM can be read. R/W’ (WE’) is used to save data into RAM and
to read the data inside RAM. If R/W' input point is at the situation of '1', RAM can only
be read. If it is '0', data can be saved in to RAM (it is in writing position). Each Register
in the RAM in the figure is 8-bit. Thus, input and output foot numbers are 8. Input and
output feet of the integrates used during the application are generally common (on the
same line).
Figure 32.2
Saving data in RAM:
RAM can be set to writing condition by taking CS’ point of RAM to "0" and R/W'
point to "0". Input buffers are opened. Output buffers are closed. According to the
condition of address inputs, 8-bit dual word entered from data input points is placed
into the selected Register. For example, when address inputs are "0 0 0 1" (A3 A2 A1
A0), number 1 Register is selected. When the word "1 0 0 0 0 0 0 1 1" (I7 I6 I5 I4 I3
I2 I1 I0) is entered from data input points, these data are saved to number 1 Register
(register). Later, when R/W' point is taken to the condition of '1', RAM passes to the
reading condition. Input buffers are closed, output buffers are opened. Data on the
register whose address is selected are transferred to output (data output points).
For example, let’s try to get the datum saved in number 1 Register in the
previous step from the output, first of all, position CS point to "0" and R/W' point to
'1'. Address information of the Register the information in which is wanted to be taken
is applied to the address inputs of RAM. According to the example, when the
information of “0 0 0 1” is applied to address inputs, the information on number 1
register is seen in outputs.
Main 6116 usage circuit is seen in the figure below.
RAM-6116 110
Figure 32.3
ADDRESS SELECTION INPUTS SELECTED

REGISTER
A3 A2 A1 A0
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Table 32.1
RAM-6116 111
TEST NO: 7.1
NAME OF THE TEST: EXAMINATION OF 6116 RAM INTEGRATE

1- Y-0020-01
2- Y-0020-02
Figure 32.4
RAM-6116 112
Steps of the test:
1. Install the circuit as shown in Figure 32.4. Join GND points of both sets.
NOTE: On our test circuit, 74HC244 integrate will be used as controlled buffer. As
this integrate is available in Y-0020-01 test set, both of the sets will be used in this
test.
W\R D0 Q0 D1 Q1 D2 Q2 D3 Q3
0 0 0 1 1 0 0 1 1
1 0 x 1 x 0 x 1 X
0 1 1 0 0 1 1 1 1
1 1 x 0 x 1 x 1 X
0 1 1 1 1 0 0 0 0
1 1 x 1 x 0 x 0 x
74HC244 integrate is a controlled buffer switch integrate. The information given to

the input is transferred to the output according to the situation of control point (W\R’).
This feature enables 6116 RAM integrate to save data from the output and read the
data saved from the same output.
When some data will be written in 6116, data are entered via switches to D0-D3
points which are the input points of 74HC244 integrate. In this situation, control point
(W\R’) should be made “0” in order to transfer the entered data to output. Buffers need
to be closed while reading the data. For this process, (W\R’) is made “1” and input and
output are isolated. In this case, data can actively be seen at 6116 output.
2. Position the switches as "0". Position READ-WRITE (W\R') point that is G switch
as "0" (WRITE'), Position (CE') point that is E switch as "0" (CHIPP-SELECT'=Chip
selection') and Position OE that is F switch as “0” (GND). Position A-B-C-D switches as
"0". Apply power to the set. (1 is the least important bit)
3. Position the switches between D0-D3 (Address Selection) as "0 0 1 0" (D0=0,
D1=0, D2=1, D3=0). What is the value seen on the display on address line?
“2” that is the hex. corresponding of 0010 entered via DATA switch is seen on
display.
4. Position the switches as "1 0 1 0". What is the value on the display?
A value that is the Hex. corresponding of 1010 is seen.
5. What is the meaning of the values read at 3 rd and 4th steps?

On step 3, number 2 address belonging to RAM; on step 4, number 10 address
belonging to RAM are seen.
6. What are the values on the display connected to data line on 3rd and 4th steps?
As data were not applied to these addresses previously, numbers showing
random data appear after the power is applied.
RAM-6116 113
7. Position the switches between D0-D3 as "0 0 0 1" and position the switches
between A0 and A3 as 0100. (CS'=0, R/W'=0). Then, make R/W'=1. What is the
operation made in this condition (condition of READ)?
In this condition, number 1 address by address line and datum of Hex.4 was
installed to this address. Besides, the datum on this address was read.
8. Position the switches between D0-D3 as "1 0 0 1", after that, again position it
as "0 0 0 1". Why the value read on data line is Hex. 4?
On the seventh step, number 4 was saved to this number 1 address (0001
address) and it was not changed.
9. Position CS' as "1" and the switches between D0-D3 as 0011. Did the value on
display change? Why?
It did not change. Because, positioning CS as "1" closed the situation that RAM
integrate is used. RAM can neither be read nor be written on.
10. Are the value seen on Display connected to data line same as the ones saved
to addresses related to 7th step by positioning CS' as "0" and R/W' as "1" after
repositioning the given address values on Table 32.1? Why?
Positioning R/W switch as "1" enabled that values entered to the previous
addresses made it easy to save data on those addresses and values on the specified
addresses are read. Therefore, the values entered on the Table and the ones read are
the same.
7. What should be done to change the value (4 datum) on the address of 1010 as
"0 1 1 0", (Hex. 6)?
CS'="0", R/W'="0", switches between D0-D3 are positioned as "1 0 1 0" and
switches between A0 and A3 are positioned as "0 1 1 0". When R/W'="1" is enabled,
the datum on the address of 1010 is saved as0110.
12. What should be made to use 32 RAM memory?

5 inputs of 6116 RAM integrate between A0 and A4 are used. (25 = 32 )
13. What should be made to use 127 RAM memory?

Inputs of 6116 RAM integrate between A0 and A6 are used.
(......+ 64 + 32 + 16 + 8 + 4 + 2 +1 = 127)
14. What is the total capacity of 6116 RAM integrate?

As there are 10 inputs (A0 - A10), it is 210 = 1024.
15. How many bits can be stored in RAM that has 1024 address input?
As datum input is 4 bits, it can be as 1024 x 4 = 4096 bits.
16. Save the data on the part of DATA paying attention to R/W' and CS' situations
on the addresses given in Table 32.2. After each new datum input, make CS' point as
“0” ultimately. Then, re-make the CS' point as "1". In this way, enter the addresses
given to 15 addresses. Make R/W' point as "1" and check that the data you previously
entered are kept by changing address data
.
RAM-6116 114
ADDRESS DATA
ROW WE’ CE’ HEX HEX
A B C D E F G H
0 0 0 0 0 0 0 0 1 0 1 1 B
1 0 0 0 0 0 1 1 0 0 1 1 3
2 0 0 0 0 1 0 2 1 1 0 0 C
3 0 0 0 0 1 1 3 1 1 1 1 1
4 0 0 0 1 0 0 4 0 0 0 1 2
5 0 0 0 1 0 1 5 0 0 1 0 8
6 0 0 0 1 1 0 6 1 0 0 0 F
7 0 0 0 1 1 1 7 1 1 1 1 D
8 0 0 1 0 0 0 8 1 1 0 1 7
9 0 0 1 0 0 1 9 1 0 1 0 A
10 0 0 1 0 1 0 A 0 1 0 0 4
11 0 0 1 0 1 1 B 0 1 0 1 5
12 0 0 1 1 0 0 C 1 0 0 1 9
13 0 0 1 1 0 1 D 1 1 1 0 E
14 0 0 1 1 1 0 E 0 0 0 0 0
15 0 0 1 1 1 1 F 0 0 0 0 0
Table 32.2
PROCESS OF DATA WRITING:

1- WR’=0 , OE’=1, CE’=0
2- Address is entered.
3- Data is entered.
4- Make OE’= 1.
5- Make WR’= 1.
6- Make OE’= 0.
RAM-6116 115
TEST NAME:
ANALOG TO DIGITAL CONVERTERS
TEST PURPOSES:
A- To learn how ADC’s work.
B- To recognize ADC 0804 integrated, to make truth table.
If values that one variable can take changes from “0” to “1” and intermediate
values such as “0, 1-0, 2……….0, 9” are calculated by voltmeter, ammeter or similar
devices; this variable is analog signal. If this variable only takes “0” and “1” values, in
other words if it doesn’t have any intermediate values, it is digital signal. If a device or
circuit turns analog signal to digital signal, this device or circuit is called ADC Analog
Digital Converter. Analog Digital Converters decrease noise effect. Digital signals are
coded and stored easily.
In figure 33.1, characteristic curve of 3 bit analog digital converter can be seen.
Figure 33.1
Analog input is between 0 and 1 volt. Input signal can be defined as in 23 = 2x2x2
=8 parts or intervals for 3 bits. All analog values in every interval are shown by using
the same binary code. During analog digital conversion, low value of the value in the
middle point of every interval is perceived as “0” and its high value is perceived as “1”.
If analog values are exactly in the middle point of the interval or part, it becomes the
point that is not known what it will be in binary coded system.
ADC 116
Figure 33.2
Uncertainty point can be seen in Figure 33.2. This situation is called quantization
uncertainty or error. Quantization error is to the ±0,5 LSB least significant bit. Least
significant bit means the bit that affects the result less when it changes. Quantization
error is reduced by increasing bit number of analog Digital converter. Quantization
value “Q” is the voltage value that can change LSB.
As a Formula, it is:
FS 1
Q n
 n
2 1 2
In the Formula;
n = Bit number
FS= Full Scale voltage.
During analog digital conversion, different methods are used. Some of these
methods are Digital Ramp type ADC, Flash ADC, Tracking ADC, Successive
approximation ADC.
Figure 33.3
In figure 33.3, block diagram of ADC (ADC 0804) that has 8 bit resolution is seen.
Sample and Hold circuit prevents the change of input signal during the conversion.
Control Logic arranges bits (D0-D1-D2-D3-D4-D5-D6) from the least significant bit
(LSB) to most significant bit (MSB) to “0” and arranges most significant bit (D7) to “1”.
This digital information is applied to DAC- Digital Analog Converter in ADC 0804
integrated. Besides, a reference voltage (VR) from outside is applied to the digital
analog converter.
As a Formula, output voltage (VD) of digital analog converter is;
VR 1
VD  2 n1.Q = 2 n 1.  VR
2n 2
ADC 117
As it is seen, VD voltage is as much as half of reference voltage. If input
voltage (VG) is bigger than (VD), most significant bit (D7) becomes “1” and least
significant bit becomes “0”. Then, by making (D6) bit “1”, a new VD is obtained in the
output of digital analog converter. Newly obtained VD and input voltage are compared
in Comparator. If input voltage (VG) is bigger than newly obtained VD, (D6) bit
becomes “1” and if it is smaller it becomes “0”. Same processing is repeated in
sequence. After the processing all digital outputs from (D7) bit to (D0) bit are obtained.
ADC 0804 is a 8 bit resolution single channeled 20 footed integrated. Supply voltage is
between 5V DC and analog input voltage interval 0-5V DC.
It has 15 mW expense, 100 µS (Micro Second) conversion time. Since this

integrated has 8 bit resolution, it has an interval of 28 =256 quantization.
If we take reference voltage 5V, quantization error is 5V/256=0.0195V. Hence,

error of ADC 0804 integrated is ±1 LSB= 0.0195V. This error also involves full interval
error, offset error and nonlinear error.
In Figure 33.4, foot connection of ADC 0804 integrated can be seen.
Figure 33.4
ADC 0804 integrated can produce required clock signal in its own. In order to do
this, it is required to connect a resistor between the feet of CLKIN and condenser from
CLKIN to “0”.
Figure 33.5
ADC 118
As a Formula, clock frequency is;
1
Fclk= ( Hz )
1.1.R : C
In the Formula, “R” is ohm and “C” is farad. Frequency of clock signal that ADC
0804 produces is 100 KHz-800 KHz. As it can be seen in Figure 10.5, there is also
Schmitt-Trigger in its structure.
WR is writing control signal. When CS’ and WR are “0”, process of clearing is
made. When WR is placed back to “1” (ADC 0804 accepts empty foot sign as “1”),
analog-digital conversion starts. During the conversion INTR’ is in “1” position. When
conversion finishes, INTR becomes “0”. ADC 0804 integrated has two GND feet. These
are analog ground (AGND) and digital ground (DGND). Foot number “9” must be half of
the reference voltage. In our test circuit, source voltage (+5V DC) is used as reference
voltage.
In this case, foot voltage numbered “9” must be positioned as 5/2=2,5V. Since,
when reference voltage is 5V DC every step will be 5V / 256 0.0195V;
00000000 (00H) shows 0.00V, and

11111111 (11F) shows 4.9805V.
ADC 119
TEST NO : 33
NAME OF THE TEST : ANALOG-DIGITAL CONVERTER (ADC ) TEST
Elemnts to be used in the Test:

1- Y-0020-2
Figure 33.6
ADC 120
Steps of the Test:
1. Install the circuit as in Figure 33,6 and power-up.
NOTE: LED diodes are used for digital outputs. Diodes light in “1” and go out in
“0”. In order to obtain a correct result, use Digital Voltmeter.
2. Set VR/2 = 2.5V DC with P2 potentiometer. In this situation, which analog

voltage values are converted to digital values by analog digital converter?
In this situation, analog voltage that is applied can convert analog values between
“0” and VR voltage (5V DC).
3. Connect a voltmeter to the analog input end. Set voltage to “0” V by P1

potentiometer. Press START button. Monitor digital outputs and interpret them.
Pushing the button erases the remaining information in outputs (D0…..D7). LED
diodes that were lighting went off when the button was pressed. When analog input
voltage was “0” all outputs went off, in other words all digital outputs were “0”.
4. Set analog input voltage to values in Table 33.1 by P1 potentiometer in

sequence. Record every value in each step. In the table, there are ideal values that
must be in the middle part. Compare the values you obtained with ideal values.
Obtained values are nearly the same with ideal values. In some values, there is a
difference of ± 1 LSB.
ANALOG IDEAL DIGITAL OUTPUTS READ-OUTS

INPUT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0.5 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0
1.0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1
1.5 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1
2.0 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1
2.5 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
3.0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0
3.5 1 0 1 1 1 0 0 0 1 0 1 1 0 1 0 0
4.0 1 1 0 0 1 1 0 1 1 1 0 0 1 1 0 1
4.5 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1
5.0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 33.1
ADC 121
TEST NAME:
EXAMINATION OF DIGITAL-ANALOG CONVERTER
TEST PURPOSES:
A- Examination of Digital-Analog Converter,
B- Monitoring working systems,
C- Recognizing AD 558 (DAC) integrated.
When you want to numerically transmit or store in memory an analog data or a

data output of a sensor such as temperature and pressure transmitter, datum must be
converted into digital form (1 and 0) from analog form. In order to make this
conversion, analog to digital (A/D) converter is used.
In DAC test, AD 558 integrated will be used. AD 558 (DAC) is an D/A converter
integrated with TTL inputs, low voltage, appropriate for CMOS, MSI (middle scale
integrated) type, 8-bit. It has an analog output with two zones and it is compatible
with microprocessor.
AD 558 has a R-2R resistance digital ramp, an output amplifier, low voltage
reference source and a control logic that can connect D/A to the 8-bit data link.
D/A converter in R-2R digital ramp takes a binary value applied to the inputs and
produces an analog value in proportion to this value. It makes this by controlling the
current flow and according to the condition of independent binary input bits. D/A
controls the flow of 8 different bit current. Each current value is directly proportional
with the weight of bit that controls the current. Weights are 1, 2, 4, 8, 16, 32, 64, and
128. The system that controls the current in this converter is a R-2R ramp.
Figure.34, 1
Working of the ramp D/A depends on the principle that current in each resistance
is divided equally (A, B, C point). In Figure 34, 1 junction, amount of current that is
divided into two arms (I1, I2) are equal to one another in both arms. I3 and I4 are
equal to half of current I2. In every junction, the process of dividing the current in the
previous one continues to the last junction point. Current in the 1st junction point is
half of the input current because the current is always divides into two. Current in the
2nd junction point is 1/3 of input current and current in the 3rd junction is 1/8 of the input
current. Resistances are connected to ground or summing amplifier input with proper
switching. OP-AMP is used here as summing amplifier. According the closure of the
key, currents are applied to the summing amplifier input.
DAC 122
Summing amplifier converts the current that comes to its input to a proportional
output voltage. Output of D/A converter depends on a 8 bit binary coded input, gain of
amplifier and voltage of power supply. AD 558 has a structure that can work with 4, 5
volts and 16, 5 volts supply voltage. Output zone can give outputs between 0......2, 56
V and 0.....10 V. If supply voltage is 5V, output value from 0......2, 56 V is obtained
from output cone (analog).
8 different input from “0 0 0” to “1 1 1” can be applied to the input of 3 bits DAC
in Figure 34.1. (23=8) If we accept full scale (*) as 4V, sensitivity of DAC becomes
4/8=0, 5 V. When input is “1 1 1” in full scale value, output is 3, 5 V. Because (1 1
1)2= (7)10 and 7x0, 5 =3, 5 V. In order to reach more accuracy (*) and full scale
value, DAC with more digital input must be used.
In the AD 558 integrated that we use in our test, there are 8 inputs. It means 256
different input values to the input. It has stability of 4/256 = 15 mV. When inputs are
"11111111" outputs will equal to 255 x 0,015 = 3,999 V and full scale value will be
approached further.
In our test, 0......2.56 V of output voltage will be used as output zone and in full
scale value it will have a stability of 2, 56/255=10,039 mV. If the first binary value is
"00000000", output of DAC will be 0 V. For input value of "1111 1111", full scale will
be 255 x 10 mV 2, 55 V.
AD 558 D/A converter has data input blockers that can be controlled by
microprocessor or control circuits. These blockers are controlled by CE’ (chip enable)
and CS’ (chip select) control inputs. When CS’ and CE’ is “0”, these blockers provide
that inputs coded according to binary system to be applied to D/A converter. If one of
the two inputs is “1”, it is prevented by binary input blockers and they can not be
applied to D/A. Therefore output can not be taken. That is to say, when CE’ and CS’
are “0”, digital input is converted into an analog output by D/A immediately.
Figure 34.2
(*)Full scale: The output analog value that needs to be obtained when all DAC digital
inputs are “1”.
(*) Accuracy: The proximity of analog value obtained in the output to the required value.
DAC 123
TEST NO: 34
NAME OF THE TEST: EXAMINATION OF AD 558 DIGITAL-ANALOG
CONVERTER INTEGRATED
Test Set and Measuring Device used in the Test:

2- Oscilloscope , Voltmeter
Figure 34.3
DAC 124
Steps of the Test :
1. Install the circuit as in Figure 34.3 and apply the power. (Places of key letter
orders are changed so that connection diagram won’t be drawn complicatedly. Pay
attention to this situation when installing the circuit.
2. Connect the oscilloscope between the output and ground and locate it to
measure 2V.
3. Set all keys to “1” position. (CE’ and CS’ =”0”) What is the D / A output
voltage? Why?
An output of D / A converter:
Analog value of least significant BIT (10 mV) x Base 10 equivalent of binary input
word
128 x 64 x 32 x 16 x 8 x 4 x 2 x 1 or = 255. Accordingly;
255 x 10 mV = 2.55 V
4. Set most significant BIT key (Key A) to “1” and others to “0” position. How
much volts can be seen in the oscilloscope? Why?
D/A output is the analog equivalent of any BIT binary weight whose logic is “1”.
Base 10 equivalent of most significant bit’s binary weight is (27 = 128).
Accordingly, output voltage will be: 128 x 0.01= 1.28 V.
5. Set all the keys between A and G to “1” and key H to “0”. The value measured
in the oscilloscope is 10 mV less than the value in 4th step. Why?
Base 10 equivalent of the binary weight of the first 7-bit is 127 (64 + 32 + 16 +
8 + 4 + 2 +1). Accordingly, 127 x 0.01 = 1.27 V.
6. Set all the keys to “0”. What is the output voltage?
Output voltage is “0”.
7. Record the outputs according to the positions of keys in Table 34.1.
8. Set positions of the keys to “0”. Set CS’ end to “1”. Set the keys between A
and G to “1” and key H to “0” position. What is the output?
Output is "0" V. Because CS' (CHIP-SELECT) is "1", integrated circuit doesn’t

process the data. Integrated is out of usage. DAC only processes when both CS’ and
CE’ (CHIP ENABLE) ends are “0”.
9. Set the end of CS’ to “0”. Tell what the difference is?
Output is 1.27 Volt. Because integrated is allowed to work.
DAC 125
AD558 DAC Integrated Output Table
INPUTS OUTPUTS
D7 D6 D5 D4 D3 D2 D1 D0 Vo
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 10mV
0 0 0 0 0 0 1 0 20
0 0 0 0 0 0 1 0 30
0 0 0 0 0 1 0 0 40
0 0 0 0 0 1 0 1 50
0 0 0 0 1 0 1 0 100
0 0 0 1 0 1 0 0 200
0 0 0 1 1 1 1 0 300
0 0 1 0 1 0 0 0 400
0 0 1 1 0 1 0 0 500
0 0 1 1 0 0 1 0 600
0 1 0 0 0 1 1 0 700
0 1 0 1 0 0 0 0 800
0 1 0 1 1 0 1 0 900
0 1 1 0 0 1 0 0 1V
1 0 0 1 0 1 1 0 1,5V
1 1 0 0 1 0 0 0 2V
1 1 1 1 1 0 1 0 2,5V
1 1 1 1 1 1 0 1 2,53V
1 1 1 1 1 1 1 0 2,54V
1 1 1 1 1 1 1 1 2,55
Table 34.1
DAC 126
TEST NAME:
EXAMINATION OF 555 INTEGRATED TIMER
TEST PURPOSES:
A- Examining 555 timer,
B- Observing working systems,
C- Recognizing 555 integrated.
555 Integrated circuit is an oscillator and timer integrated that is used commonly
in our day. It can be used in various application areas. Some of the features of 555
integrated are;
 Working as stable, astable or one stable multivibrator,

 Working as adjusted oscillator,
 Timing from microsecond to hours,
 Ability to give TTL compatible output,
 Ability to give 200mA output current,
 Working in voltages between 5V and 15 V.
Foot connection and internal structure is seen below.
Figure 35.1
555 TIMER 127

EXAMINATION OF WORKING OF 555 INTEGRATED AS ASTABLE
MULTIVIBRATOR
TEST PURPOSES:
A- Learning the ASTABLE working of 555 integrated.
In astable working, 555 integrated gives output between the frequency interval
that is determined by resistors and condenser. When output is observed from the LED,
it is seen that interval of lighting and fading is equal.
Circuit frequency;
Period of square wave;
T= 0,693(R1+2R2) C.
Frequency is found by the Formula below;

1 1,44
f= 
t ( R1  2 R 2 )C
Shape of the circuit and output wave shape is seen below.
Figure 35.2
Figure 35.3
555 TIMER 128

TEST NO: 35
TEST NAME: EXAMINATION OF WORKING OF 555 INTEGRATED AS
ASTABLE MULTIVIBRATOR
Elements to be used in the Test:

1- Y-0020-02
2- Oscilloscope
Figure 35.4
Steps of the Test:
1. Install the circuit as in Figure 35.4.

2. Draw the shape that you see in the screen of oscilloscope.
3. Is the circuit working as astable multivibrator?
4. Calculate the operating frequency of the circuit.
T= 0,693(R1+2R2)C.
Frequency;
1 1,44
f= 
t R1  2 R 2.C
Figure 35.5
555 TIMER 129

EXAMINATION OF WORKING OF 555 INTEGRATED AS MONOSTABLE
MULTIVIBRATOR
TEST PURPOSES:
B- Learning the MONOSTABLE working of 555 integrated.
555 Integrated can also be operated as MONOSTABLE. In the circuit in the figure,
there is an output when voltage is given and after a while LED goes off. When you
press the button again, LED lights; and according to the capacity of the condenser,
after a while it goes off again, thus monostable working continues as long as button is
pressed. Time period in the circuit is found with the Formula below.
T=1,1.(R1.C1)
T= Period second (s)

R1 = Resistor ohms ( )
C1 = Capacity farad (F)
Figure 36.1
Figure 36.2
555 TIMER 130

TEST NO: 36
TEST NAME: EXAMINATION OF WORKING OF 555 INTEGRATED AS
MONOSTABLE MULTIVIBRATOR
Elements to be used in the Test:

1- Y-0020-02
2- Oscilloscope
Figure 36.3
Steps of the Test:

2. Draw the shape you see in the screen of the oscilloscope.
3. Is the circuit working as monostable multivibrator?
4. Calculate the period of the circuit.
T= 1.1(R1.C1).
Frequency;
1 1,44
f= 
t ( R1  2 R 2 )C
Figure 36.4
555 TIMER 131

EXAMINATION OF WORKING OF 555 INTEGRATED AS BISTABLE
MULTIVIBRATOR
TEST PURPOSES:
C- Learning the BISTABLE working of 555 integrated.
555 Integrated can be operated as BISTABLE as well. This type of working can be
explained as flip-flop working. In the circuit in the figure there is an output when
voltage is given and it continues the output until second button is pressed. When
second button is pressed LED goes off and when the first button is pressed LED lights.
That is to say, one of the buttons operates the output and other cuts the output. This is
also a typical flip-flop working. Time period can be drawn as follows.
(It is not certain that which of the situation will occur at the beginning.)
Figure 37.1
Figure 37.2
555 TIMER 132

TEST NO: 37
TEST NAME: TEST OF WORKING OF 555 INTEGRATED AS BISTABLE
MULTIVIBRATOR
Elements to be Used in the Test:

1- Y-0020-02
2- Oscilloscope
Figure 37.3
Steps of the Test:

2. Draw the shape you see in the screen of oscilloscope.
3. Is the circuit working as bistable multivibrator?
Figure 37.4
555 TIMER 133

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ADVANCED LEVEL DIGITAL ELECTRONICS

1- POWER ON-OFF SWITCH:

2- DC +5V POWER SUPPLY:

3- 12 BIT LOGIC LED INDICATING SWITCH GROUP:

4- PULSE SWITCH CIRCUIT:

5- 2 PHASE 1Hz-1KHz SQUARE WAVE OSCILLATOR:

6- 12 BIT HIGH LEVEL LED INDICATOR CIRCUIT:

7- 12 BIT LOW LEVEL LED INDICATOR CIRCUIT:

8- ADVANCED LEVEL DIGITAL CIRCUITS:

9- 2x4 BIT HEXADECIMAL DECODER DISPLAY:

10- 5x7 DOT MATRIX DISPLAY:

11- BREADBOARD FOR EXTERNAL APPLICATIONS:

These are Logic integrateds and lineer integrateds:

Lineer integrateds: Are used generally in processes such as voltage rising,

Logic integrateds: Are composed of gate circuits. (digital integrateds)

Integrated Circuit Parameters

There are some important specifications to compare digital integrated circuit

1. Power supply voltage:

4. Output Capacitance (Fan out):

6. Pulse frequency (Clock frequency):

1. RTL - Resistance - Transistor Logic

Logic Family Types of the Integrated Circuits:

Transistor Transistor Logic (TTL):

There are 4 main ECL subgroups.

Complementary Metal -Oxide Semi Conductor Logic (CMOS):

Integrated Injection Logic (IIL):

SPECIFICATIONS TTL CMOS

Figure 1.1 Figure 1.2 Figure 1.3

4093 integrated counterfort connection, comprising four SCHMITT-TRIGGER gates

Elements To Be Used In The Test:

Steps of the Test:

3- Write down by measuring the output wave frequency with oscilloscope. In

4- Write down by measuring and calculating the output frequency when R is in

6- Bring R in 6K9 position, C in 680 nF position and P in minimum position.

7- Bring R in 6K9 position, C in 680 nF position and P in maximum position. Write

Q1(A)=0 , Q2(B)=0 , Q3(C)=0 , Q4(D)=0

A lot of counter circuit in asynchronous structure can be performed. If the

The Set To Be Used In the Test :

OUTPUTS HEX DECIMAL

7. Did the counter work as up counter according to this?

The counter worked as up counter.

The Test Set To Be Used In The Test :

5. Which number does the modulo of counter have?

OUTPUTS HEX DECIMAL

The Circuit Components Used In The Test :

2. Make the SET input (A switch) "0".

3. Press the PULSE button until the FF outputs are initialized.

5. What is the modulo of the counter? Why?

ÇIKIŞLAR HEX DECIMAL

A- The examination of the workings of synchronous counters

The working of synchronous 2 down counting circuit is in a similar way.

The Test Sets Used in the Test :

4. Fill the Figure 5.1 according to the pulses applied.

6. Is the principle of synchronous counter, given in the preliminary information,

OUTPUTS HEX DECIMAL

3. Fill the Table 6.1 in accordance with the pulses applied.

5. What is the modulo of the counter?

OUTPUTS HEX DECIMAL

The counter is designed according to the MODE-5. It counts from 0 to 4, resets in

4. Can the counting process be made to the desired number?

Yes, it can be made.

OUTPUTS HEX DECIMAL

A- The examination of 4024 Counter Integrated,