Vlsi Lab PDF

VLSI LAB IV B.
Tech I SEM
MENTOR GRAPHICS PROCEDURE
INTRODUCTION:
This document gives a overview of how to design & simulate with Mentor Graphics tools.
There are five basic steps:
1. Design the schematic in Pyxis.
2. Simulate the schematic and check for parameters.
3. Layout the schematic in Pyxis.
INVOKING MENTOR TOOLS:

Right click on the Linux desktop and click on open in terminal.
Type csh and press enter.
Type source /home/software/cshrc/cshrc130.cshrc
Type cd /home/software/FOUNDRY/GDK/Pyxis_SPT_HEP
Type ./pyxismgr and press enter then pyxis project manager window will be invoked
Dept of ECE, Aditya College of Engineering 1

VLSI LAB IV B.Tech I SEM
CREATING A PROJECT:
To create a new project click on File New project, this will invoke the new project window
as shown.
Select the project path in the project navigator window.

Select the root folder
Create a new directory and give the directory name as shown and click on OK

Next technology libraries have to be added to the project. In order to add the technology
files browse on the folder as shown
Browse the folder to

root/software/FOUNDRY/GDK/Pyxis_SPT_HEP/ic_reflibs/tech_libs/generic13 file and
click on OK.

Again click on OK then manage external/logic libraries window will pop up as shown.
Click on the Add Standard Libraries. The libraries will be added up as shown below and
click
on OK.
Then the pyxis project manager window will be shown where the technology libraries are
added
to the project and are placed below the project name.

CREATING A LIBRARY:
To create a library right click on the project name and select new library or click on the icon
on the icon bar.
Then a new library window will pop up asking for the library name.
Next name the library and click on OK.

CREATING A SCHEMATIC CELL VIEW:
To create a schematic cell view, a new cell has to be created in which new Schematic has to
be
defined. In order to create new cell right click on the manual library below the project name
and
select new cell or select the library and click on the icon C in the icon bar.
Then a new cell window will pop up asking for the cell name in which give the cell name and
click OK.
To create a schematic in the cell, right click on the cell name and select new schematic
or click on the new cell and select the icon in the icon bar.

A window will pop up asking for the schematic name.
Now name the schematic and click on OK which in turn leads to the pyxis schematic
editor window as shown.
CREATING A SCHEMATIC:
In this section you will become familiar with placing primitive analog devices for a inverter.
You‟ll learn how to:
• place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• route devices
• edit device parameter values
• name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using eldo
• view results

CREATING AN INVERTER:
Placing devices:
From the left icon bar press on add instance icon or press „I‟
Then a file browser which contains entire libraries will pop up as shown.
Next double click on generic13 in the library list.

And then follow the path to select pmos from $generic13/symbols/pmos as shown in the
figure.
Select the pmos and click on OK to place the pmos on the workspace as shown.

And then follow the path to select nmos from $generic13/symbols/nmos as shown.
Select the nmos and click on OK to place the nmos on the workspace as shown.
CHANGING DEVICE PROPERTIES:
In order to change the properties of the devices on the workspace click on the device then the
corresponding device properties will be shown in the object editor as shown.

CHANGING DEVICE PROPERTIES:

In order to change the properties of the devices on the workspace click on the device then the
corresponding device properties will be shown in the object editor as shown.
Change the Width & Length values of the Transistors to
For PMOS : L = 0.13u; W=0.3u
For NMOS : L = 0.13u; W =0.15u

Connect the circuit as shown below.
ADDING THE PORTS AND CONNECTING THE DEVICES:

Select generic library and place ground from the Instance window.
In the similar way place IN and OUT ports as above from the generic library.
Then the schematic would look as follows
For changing the port names click on the port and change the net name in the object editor to the
required name as shown below.
After editing the schematic check for errors by selecting check & save option in the icon
bar.

This will result to an window which shows the error report where the errors and warnings in
the schematic can be seen in the Transcript Area.
GENERATING THE SYMBOL:

Go to Add Generate Symbol
Select Replace existing & activate symbol options. Click Ok.
Symbol gets generated for you.
Change the shape of symbol if required from choose shape.
Then click on OK which leads to the pyxis symbol window.
Save the symbol.

After saving the symbol check for errors by selecting check and save option in the icon bar.
the schematic can be seen in the Transcript Area.
TEST BENCH CREATION:

To create a test bench close all schematics and symbol windows and go back to pyxis project
manager window. In the project manager window to create a new cell right click on the
manual
library below the project name and select new cell or select the library
and click on the icon in the icon bar.
Then a new cell window will pop up asking for the cell name in which give the cell
name and click OK.

Here the test bench cell name has been specified as inv_tb.
Right click on the test bench cell and select new schematic which in turn opens pyxis
Schematic
editor window.
Add symbol of the schematic made.
AddInstanceChoose Symbol.
Place the symbol on the work space as shown.
Add a Pulse Source at the input to inverter and a DC Voltage source VDD port.
And do the necessary connections as per the figure given below.
Right click on the Pulse Source and select Edit Properties.
Change the values of the below mentioned parameters and apply the changes.
Initial = 0V Pulse = 5V Delay = 1nS Rise = 1nS
Fall = 1nS Width = 25nS Period = 50ns.
Also change the magnitude of the Voltage Source from 1V to 5V by following the
below step.
Right Click on the Voltage source adjacent to VDD and then Edit properties

Next click on check & save icon in the icon bar.
the
symbol can be seen in the Trascript area.
SIMULATING THE SCHEMATIC:
SIMULATING TEST BENCH
When you have no errors select the simulation icon from the left icon palette to go into the
design context and simulate our design and select the run simulation.

Now in the design context we need to setup the analysis type, plots and load in the ELDO
models.
Select a New configuration (Give a new name for the simulation).
Select ac, dc, tran from setup simulation window
Select Analysis setup and enable “DC” and ”Transient” and click on Apply.
Drop down the Analysis setup and select DC setup give the parameters as
Select option Source
Select the voltage source as V1

Start: 0 Stop: 5 Step 0.1 and click on Apply.
Select Transient Setup and change the Stop time to 1000N click on Apply.
Select the input path A and then hold CTRL key and then output path Y.

Click on Edit Probes from the Setup Simulation. Select DC in Analysis tab, Plot from
Task tab. Select add.
Select TRAN from Analysis tab and select add and close the window.
Select the symbol, and from the setup simulation select TRAN in Analysis tab,
Plot from task tab, power from type tab then save and select add.

Select libraries from setup simulation, edit libraries window will pop up.
Select import library and browse for library path to /home/software/FOUNDRY/GDK/
Pyxis_SPT_HEP/ ic reflibs/tech libs/generic13/models/lib.eldo
Select Edit Corners/Families, from Library Corners tab check for TT

Click on Ok.

Select Edit Scenarios from Device Families tab check for TT

After adding the analysis, libraries and edit probes minimize the setup simulation
window
and run the simulator. To run the simulation select from the left icon palette or select
simulaterun simulation

View the simulation results by selecting the plo
t results from latest run icon from the

left icon palatte. This will open EZ Wave for you with the output waveforms.

CREATING A LAYOUT:

• To create a layout select inv cell. Right click on the cell and select New layout.
A new window named New layout will pop up, here the layout name is same as the cell
name as
shown and click Ok.
Pyxis layout window will be invoked with a New layout sub-window in it and keep the
settings as shown and click on OK.

Make the Schematic window active by selecting it with the Left Menu Bar. Select PMOS and
Press on the Pick & Place icon from the SDL tool bar on the Icon Bar. The tool will place
the device on the Workspace of IC layout window. Similarly select the NMOS and place it on
the workspace.
Note: To make SDL toolbar active, goto setup->toolbar->SDL tool bar

With the layout window active, select the Pick Place Ports icon from the SDL toolbar.

Place Schematic ports window will pop up. Select the VDD port and select a layer for this
port.
The Width and Height will be updated automatically according to the minimum metal1
dimensions. Press Apply to place the port.
Place the rest of the ports.

To add the substrate contacts to the mosfets. Select Add Device icon from the Left Hand
Palette,
then select Path-based Guard Band select psub

Do the same for but choose nwell instead of psub
To add the over flow lines for both psub & nwell , Select psub then Connectivity > Net >
Add
to Net to set psub to Ground and the same for nwell to set it to VDD
ROUTING THE LAYOUT:

Manual routing:
To start routing press on the IRoute icon in the SDL toolbar. Once you place the cursor on
where you want to start routing, it will start guided by the fly lines. You can toggle between
the
connectivity layers by pressing space-bar

Route all the ports in the layout except input port as shown
For routing poly and input port of M1, VIA has to be created
Routing Poly-M1
VIA CREATION:
Select Route in the ic palatte window as shown

Now select Options in ARoute Setup then following window will be invoked
Click on Advanced button in the ARoute Options window.
Then Advanced route options window pops up, Select the VIA OPTIONS check use via
generator and click OK and OK.

Select Iroute, place POLYG at the input and start routing as shown. Now press SPACE
BAR
automatically VIA will be created.

Then complete layout for the inverter will be generated as shown.

PHYSICAL VERIFICATION OF LAYOUT:
1. DRC
2. LVS
3. PEX
RUNNING CALIBRE INTERACTIVE DRC:
In the pyxis layout window, Select ToolsCalibreRun DRC

This will bring up the Calibre Interactive – DRC
RUNNING LVS (Layout versus Schematic):
Before going to LVS, text the ports on the layout .In the pyxis window menu bar select
Add Text on Ports.
Select Tools Calibre Run LVS entry from the pull down menu.
The Calibre Interactive – LVS window will popup.
RUNNING CALIBRE INTERACTIVE PEX:
Select Tools Calibre Run PEX from the menu.

The Calibre Interactive – PEX window will popup.

EXPERIMENTS

Circuit Diagram:
Test Bench:

Exp.No: Date:
INVERTER
AIM: Design and implement an Inverter using CMOS 130nm technology and draw the layout.
APPARATUS: Mentor Graphics Back End Tools
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS
source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain
terminals. the voltage at the input of the CMOS device varies between 0 and 5 volts, the state of the
NMOS and PMOS varies accordingly. When VIN is low, the NMOS is "off", while the PMOS stays
"on": instantly charging VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is
"on: draining the voltage at VOUT to logic low.
PROCEDURE:
1. Open Mentor Graphics tools by typing commands in terminal of LINUX.

2. Go to file click open and select the path to open your project.
3. Click on project name and create new cell with experiment name.
4. Click on cell and create new schematic, a Pyxis Schematic window will appear .
5. Connect the schematic as shown in the figure by using ADD and INSTANCE options.
6. After completing the schematic save and check save the schematic.
7. Generate a symbol for the schematic from ADD option Generate Symbol.
8. Click on project name and create new cell for Test Bench Creation.
9. Add symbol to the test bench, make connections and apply sources as shown in the figure.
10. Enter simulation mode and apply analysis setup as per the experiment.
11. Observe the corresponding outputs in EzWave.

Waveforms :
Transient Analysis
DC Analysis

12. Click on cell with experiment name and create a new layout.
13. Pick and place the components or select the layouts from Instance option.
14. Place the ports and route the connections using iRoute option to form complete layout.

Layout:

RESULT :

Circuit Diagram:
Test Bench:

Exp.No: Date:
2 INPUT NAND GATE
AIM: Design and implement an 2 input NAND gate using CMOS 130nm technology and draw the
layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
The NAND or “Not AND” function is a combination of the two separate logical functions,
the AND function and the NOT function connected together in series. The logic NAND function can
be expressed by the Boolean expression of A.B. The Logic NAND Function only produces an output
when “ANY” of its inputs are not present and in Boolean Algebra terms the output will
be TRUE only when any of its inputs are FALSE. A LOW (0) output results only if both the inputs to
the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results.
PROCEDURE:


Waveforms:
Layout:

RESULT:

Circuit diagram:
Test Bench:

Exp.No: Date:
2 INPUT NOR GATE
AIM: Design and implement an 2 input NOR gate using CMOS 130nm technology and draw the
layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital logic ORgate with
that of an inverter or NOT gate connected together in series. The NOR(Not – OR) gate has an output
that is normally at logic level “1” and only goes “LOW” to logic level “0” when ANY of its inputs are
at logic level “1”. The Logic NOR Gate is the reverse or “Complementary” form of the OR gate. The
logic or Boolean expression given for a logic NOR gate is that for Logical Multiplication which it
performs on the complements of the inputs. The Boolean expression for a logic NOR gate is denoted
by a plus sign, ( + ) with a line or Overline, ( ‾‾ ) over the expression to signify the NOT or logical
negation of the NOR gate giving us the Boolean expression of: A+B = Q.
PROCEDURE:


Waveforms:
Layout:

RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
FULL ADDER
AIM: Design and implement an full adder using CMOS 130nm technology and draw the layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit
binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade of
adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the
carry output from the circuit "above" itself in the cascade. The carry output from the full adder is fed
to another full adder "below" itself in the cascade. If you look closely, you'll see the full adder is
simply two half adders joined by an OR.
PROCEDURE:


Waveforms:
Layout:

RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
FULL SUBTRACTOR
AIM: Design and implement an full subtractor using CMOS 130nm technology and draw the layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
The main difference between the Full Subtractor and the previous Half Subtractor circuit is
that a full subtractor has three inputs. The two single bit data inputs X (minuend) and Y (subtrahend)
the same as before plus an additional Borrow-in (B-in) input to receive the borrow generated by the
subtraction process from a previous stage. Then the combinational circuit of a “full subtractor”
performs the operation of subtraction on three binary bits producing outputs for the difference D and
borrow B-out. Just like the binary adder circuit, the full subtractor can also be thought of as two half
subtractors connected together, with the first half subtractor passing its borrow to the second half
subtractor
PROCEDURE:


Waveforms:
Layout:

11. Observe the corresponding outputs in EzWave

RESULT:

Circuit Diagram:.
Test Bench:

Exp.No: Date:
STATIC RAM CELL
AIM: Design and implement an static RAM cell using CMOS 130nm technology and draw the
layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on
four transistors (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has two
stable states which are used to denote 0 and 1. Two additional access transistors serve to control the
access to a storage cell during read and write operations.
Access to the cell is enabled by the word line (WL in figure) which controls the
two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the
bit lines: BL and BL. They are used to transfer data for both read and write operations.
An SRAM cell has three different states: standby (the circuit is idle), reading (the data has been
requested) or writing (updating the contents). The three different states work as follows:
Standby
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the
bit lines. The two cross-coupled inverters formed by M1 – M4 will continue to reinforce each other as
long as they are connected to the supply.
Reading
In theory, reading only requires asserting the word line WL and reading the SRAM cell
state by a single access transistor and bit line, e.g. M6, BL. The read cycle is started by
precharging both bit lines BL and BL, i.e. driving the bit lines to a threshold voltage (midrange
voltage between logical 1 and 0) by an external module (not shown in the figures). Then asserting
the word line WL, enabling both the access transistors M5 and M6 which causes the bit line BL
voltage to either slightly

Waveforms:
Layout:

drop (bottom NMOS transistor M3 is ON and top PMOS transistor M4 is off) or rise (top
PMOS transistor M4 is on). It should be noted that if BL voltage rises, the voltage drops, and
vice versa. Then the BL and lines will have a small voltage difference between them. A sense
amplifier will sense which line has the higher voltage and thus determine whether there
was 1 or 0 stored..
Writing
The write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0,
we would apply a 0 to the bit lines, i.e. setting BL to 1 and to 0. A 1 is written by inverting the
values of the bit lines. WL is then asserted and the value that is to be stored is latched in.
PROCEDURE:

RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
RS LATCH
AIM: Design and implement an RS Latch using CMOS 130nm technology and draw the layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where
S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates.
The stored bit is present on the output marked Q.
While the R and S inputs are both low, feedback maintains the Q and Q outputs in a constant state,
with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output
is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low,
then the Q output is forced low, and stays low when R returns to low.
The R = S = 1 combination is called a restricted combination or a forbidden state because, as both

NOR gates then output zeros, it breaks the logical equation Q = not Q
PROCEDURE:


Waveforms:
Layout:

RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
D LATCH
AIM: Design and implement an D Latch using CMOS 130nm technology and draw the layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
This latch exploits the fact that, in the two active input combinations (01 and 10) of a gated SR
latch, R is the complement of S. The input NAND stage converts the two D input states (0 and 1) to
these two input combinations for the next SR latch by inverting the data input signal. The low state of
the enable signal produces the inactive "11" combination. Thus a gated D-latch may be considered as
a one-input synchronous SR latch. This configuration prevents application of the restricted input
combination. It is also known as transparent latch, data latch, or simply gated latch. It has a data input
and an enable signal (sometimes named clock, or control). The word transparent comes from the fact
that, when the enable input is on, the signal propagates directly through the circuit, from the input D
to the output Q.
PROCEDURE:


Waveforms:
Layout:

RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
DIFFERENTIAL AMPLIFIER
AIM: Design and implement an Differential Amplifier using CMOS 130nm technology and draw the
layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
The Differential amplifier is one of the versatile circuits in analog circuit design. A differential
amplifier is a circuit that can accept two input signals and amplify the difference between two input
signals. The circuit consists of NMOS and PMOS devices, where p-channel MOSFET is used to form
differential pair and n-channel current mirror load is used.
The figure shown above is an active load MOSFET differential amplifier. MOSFET M1 and
M2 formed differential amplifier pair. MOSFET M3 and M4 form a current mirror. Considering that
all transistors are in saturation region. The Bulk of all transistor connected to their sources. Transistor
M3, M4 connects to the VDD supply, whereas transistor M5 connected to VSS.
PROCEDURE:


Waveforms:
Layout:

RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
ASYNCHRONOUS COUNTER
AIM: Design and implement an Asynchronous counter using CMOS 130nm technology and draw the
layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
In digital logic and computing, a counter is a device which stores (and sometimes displays)
the number of times a particular event or process has occurred, often in relationship to a clock signal.
The most common type is a sequential digital logic circuit with an input line called the "clock" and
multiple output lines. The values on the output lines represent a number in the binary or BCD number
system. Each pulse applied to the clock input increments or decrements the number in the counter.
A counter circuit is usually constructed of a number of flip-flops connected in cascade.

Counters are a very widely-used component in digital circuits, and are manufactured as
separate integrated circuits and also incorporated as parts of larger integrated circuits.
An asynchronous counter (Ripple Counter) derives is its name from the fact that the output of
the counter is not directly dependant on the applied clock. Another way to explain this would be to
say that the clocking signal is provided only to one of the Flip Flops(FF) and the remaining (n-1) FF's
clock pins are driven by the output of the previous stage. So the output of the (n-1) flip flops changes
asynchronously with respect to the clocking signal of the system. It can count to 2n - 1 where n is the
number of bits (flip-flop stages) in the counter.
The circuit shown is a 3 bit Asynchronous Counter which will increment once for every clock
cycle and takes eight clock cycles to overflow, so every cycle it will alternate between a transition
from 0 to 1 and a transition from 1 to 0.

Waveforms:
Layout:

PROCEDURE:

RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
2 INPUT AND GATE
AIM: Design and implement an 2 input AND gate using CMOS 130nm technology and draw the
layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
A Logic AND Gate is a type of digital logic gate that has an output which is normally at logic
level “0” and only goes “HIGH” to a logic level “1” when ALL of its inputs are at logic level “1”. The
output state of a “Logic AND Gate” only returns “LOW” again when ANY of its inputs are at a logic
level “0”. In other words for a logic ANDgate, any LOW input will give a LOW output. The logic or
Boolean expression given for a digital logic AND gate is that for Logical Multiplication which is
denoted by a single dot or full stop symbol, ( . ) giving us the Boolean expression of: A.B = Q.
PROCEDURE:


Waveforms:
Layout:


RESULT:

Circuit Diagram:
Test Bench:

Exp.No: Date:
2 INPUT OR GATE
AIM: Design and implement an 2 input OR gate using CMOS 130nm technology and draw the
layout.
1. Pyxis Schematic
2. Pyxis Layout
3. EzWave
THEORY:
A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an output which
is normally at logic level “0” and only goes “HIGH” to a logic level “1” when one or more of its
inputs are at logic level “1”. The output, Q of a “Logic OR Gate” only returns “LOW” again
whenALL of its inputs are at a logic level “0”. In other words for a logic OR gate, any “HIGH” input
will give a “HIGH”, logic level “1” output. The logic or Boolean expression given for a digital logic
OR gate is that for Logical Addition which is denoted by a plus sign, ( + ) giving us the Boolean
expression of: A+B = Q.
PROCEDURE:


Waveforms:
Layout:


RESULT:

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VLSI LAB IV B.

MENTOR GRAPHICS PROCEDURE

INVOKING MENTOR TOOLS:

Dept of ECE, Aditya College of Engineering 1

Select the project path in the project navigator window.

Dept of ECE, Aditya College of Engineering 2

Browse the folder to

Dept of ECE, Aditya College of Engineering 3

Dept of ECE, Aditya College of Engineering 4

on the icon bar.

Next name the library and click on OK.

Dept of ECE, Aditya College of Engineering 5

A window will pop up asking for the schematic name.

Dept of ECE, Aditya College of Engineering 6

Next double click on generic13 in the library list.

Dept of ECE, Aditya College of Engineering 7

Dept of ECE, Aditya College of Engineering 8

CHANGING DEVICE PROPERTIES:

Dept of ECE, Aditya College of Engineering 9

CHANGING DEVICE PROPERTIES:

Dept of ECE, Aditya College of Engineering 10

Connect the circuit as shown below.

ADDING THE PORTS AND CONNECTING THE DEVICES:

Dept of ECE, Aditya College of Engineering 11

GENERATING THE SYMBOL:

Dept of ECE, Aditya College of Engineering 12

TEST BENCH CREATION:

Dept of ECE, Aditya College of Engineering 13

Dept of ECE, Aditya College of Engineering 14

Next click on check & save icon in the icon bar.

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Select ac, dc, tran from setup simulation window

Dept of ECE, Aditya College of Engineering 16

Start: 0 Stop: 5 Step 0.1 and click on Apply.

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Dept of ECE, Aditya College of Engineering 18

Select Edit Corners/Families, from Library Corners tab check for TT

Dept of ECE, Aditya College of Engineering 19

Select Edit Scenarios from Device Families tab check for TT

Dept of ECE, Aditya College of Engineering 20

Dept of ECE, Aditya College of Engineering 21

View the simulation results by selecting the plo

t results from latest run icon from the

Dept of ECE, Aditya College of Engineering 22

Dept of ECE, Aditya College of Engineering 23

Dept of ECE, Aditya College of Engineering 24

Note: To make SDL toolbar active, goto setup->toolbar->SDL tool bar

Dept of ECE, Aditya College of Engineering 25

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Place the rest of the ports.

Dept of ECE, Aditya College of Engineering 27

Dept of ECE, Aditya College of Engineering 28

Do the same for but choose nwell instead of psub

ROUTING THE LAYOUT:

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Dept of ECE, Aditya College of Engineering 30

Click on Advanced button in the ARoute Options window.

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Dept of ECE, Aditya College of Engineering 32

Then complete layout for the inverter will be generated as shown.

Dept of ECE, Aditya College of Engineering 33

PHYSICAL VERIFICATION OF LAYOUT:

RUNNING CALIBRE INTERACTIVE DRC: