Professional Documents
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STANDBY
0
POWER
STANDBY/ON
RRV1887
DVD PLAYER
DV-505
THIS MANUAL IS APPLICABLE TO THE FOLLOWING MODEL(S) AND TYPE(S).
Model Regional
The voltage can be converted by the
Type Power Requirement restriction codes
DV-505 following method.
(region number)
WY O AC 220 – 240V 2
WY/RD O AC 220 – 240V 4
WYW/SP O AC 220 – 240V 2
RD/RC O AC 110 – 127/220 – 240V Automatic select 3
RAM O AC 110 – 127/220 – 240V Automatic select 6
RL O AC 110 – 127/220 – 240V Automatic select 3
CONTENTS
1. SAFETY INFORMATION ...................................... 2 7. GENERAL INFORMATION ................................ 46
2. EXPLODED VIEWS AND PARTS LIST ................ 3 7.1 DISASSEMBLY ........................................... 46
3. SCHEMATIC DIAGRAM ..................................... 10 7.2 BLOCK DIAGRAM ........................................ 47
4. PCB CONNECTION DIAGRAM .......................... 24 8. PANEL FACILITIES AND SPECIFICATIONS .... 48
5. PCB PARTS LIST ............................................... 33
6. ADJUSTMENT .................................................... 38
PIONEER ELECTRONIC CORPORATION 4-1, Meguro 1-Chome, Meguro-ku, Tokyo 153, Japan
PIONEER ELECTRONICS SERVICE, INC. P.O. Box 1760, Long Beach, CA 90801-1760, U.S.A.
PIONEER ELECTRONIC (EUROPE) N.V. Haven 1087, Keetberglaan 1, 9120 Melsele, Belgium
PIONEER ELECTRONICS ASIACENTRE PTE. LTD. 501 Orchard Road, #10-00 Lane Crawford Place, Singapore 0923
c PIONEER ELECTRONIC CORPORATION 1997
T - IZM DEC. 1997 Printed in Japan
DV-505
1. SAFETY INFORMATION
This service manual is intended for qualified service technicians ; it is not meant for the casual do-it-
yourselfer. Qualified technicians have the necessary test equipment and tools, and have been trained
to properly and safely repair complex products such as those covered by this manual.
Improperly performed repairs can adversely affect the safety and reliability of the product and may
void the warranty. If you are not qualified to perform the repair of this product properly and safely, you
should not risk trying to do so and refer the repair to a qualified service technician.
IMPORTANT
THIS PIONNER APPARATUS CONTAINS
LASER OF CLASS 1.
SERVICING OPERATION OF THE APPARATUS
SHOULD BE DONE BY A SPECIALLY
INSTRUCTED PERSON.
LABEL CHECK
2. When the cover is open, close viewing through the objective lens
with the naked eye will cause exposure to the laser beam.
2
DV-505
8 Card Not used Notused Not used VRY1110 VRY1109 Not used
10 Label (Region) VRW1701 VRW1705 VRW1701 VRW1702 Not used VRW1702
15 Packing Case VHG1718 VHG1718 VHG1736 VHG1717 VHG1743 VHG1717
17 Operating Instructions (English) Not used Not used Not used VRB1192 VRB1192 VRB1192
18 Operating Instructions (Spanish) Not used Not used VRC1065 Not used Not used Not used
18 Operating Instructions (Trad-chinese) Not used Not used Not used VRC1063 Not used VRC1063
18 Operating Instructions (Simp-chinese) Not used Not used Not used Not used VRC1061 Not used
NSP 19 Caution (EW) Not used Not used VRM1027 Not used Not used Not used
NSP 20 Card (Information Center Tel. No.) Not used Not used VRR1023 Not used Not used Not used
NSP 21 Card (Service Tel. List) Not used Not used VRR1034 Not used Not used Not used
NSP 22 Card (Connection) Not used Not used VRR1033 Not used Not used Not used
23 Label (Model Type) Not used VRW1713 Not used VRW1710 Not used Not used
3
DV-505
RD/RC and RAM
types only
1
2.2 EXTERIOR SECTION 19
18
16
17
9
14 Except for
RAM,RL type
20
10 16
Refer to
"2.3 FRONT PANEL
SECTION" 21
15 22
5
Refer to
12 "2.4 BOTTOM VIEW SECTION"
13 11
2 4
3 15
20 Label (Region) VRW1700 VRW1704 VRW1700 VRW1703 Not used Not used
22 Power Button VNK4184 VNK4184 VNK4184 VNK4159 VNK4159 VNK4159
4
DV-505
16
2 3
8(1/3)
7
4 10
8(2/3) 14
15
6
13
16
11
12 1
RD/RC,RAM,
RL only
17 8(3/3)
5
DV-505
25 4 Refer to
"2.5 LOADING MECHANISM ASSY"
23
5 23
6
7
8
31 23
8 22
28
21
23
23
11
12
23 2 23
14 23
10 23 23
10
23 19
13
1
12 20
23
23
30
3
29
WY, WY/RD,
17 WYW/SP only
15 18
23 16 24
6
DV-505
7
DV-505
Refer to
20
"2.6 SERVO MECHANISM
ASSY" 1
17 7
18
9 8
3
4
16
10
13 15
6
11 14
12
8
DV-505
3
2 1
4
5
6 10 20
29
7
11
14 9 21
30
22
12
28
13 23
25
32
27
8 17
15 18
16 18
31
26 24
18
18
19
9
1 2 3 4
DV-505
3. SCHEMATIC DIAGRAM
3.1 OVERALL CONNECTION DIAGRAM, LOMB, LOSB, INSB
AND FGSB ASSEMBLIES
A WY,WY/RD,WYW/SP
ONLY
L
SCCB ASSY
(VWV1577)
H ( H 1/3 H 3/3 )
DVDM ASSY
(VWS1326)
I
AVJB ASSY
VWV1575:WY,WY/RD,WYW/SP
VWV1574:RD/RC,RAM,RL
SR IN
C
G
DILB ASSY
(VWG1881) E
FLKB ASSY
VWG1876:WY,WY/RD,
D
F :WYW/SP
VWG1940:RD/RC
PWSB ASSY VWG1934:RAM
VWG1937 VWG1875:RL
:WY,WY/RD,WYW/SP
VWG1880
RD/RC,RAM,RL
10
1 2 3 4
5 6 7 8
DV-505
Note : When ordering service parts, be sure to refer to "EXPLODED VIEWS and PARTS LIST" or "PCB PARTS LIST".
A D FGSB ASSY
(VWG1884)
A
LOMB ASSY
(VWG1886) PC101
GP2S27(B)
CN401
B2B-PH-K-S
CN303
B2B-PH-K-S
B CN101
B3B-PH-K-S
LOSB ASSY CN201
B3B-PH-K-S
(VWG1885)
CN301
VKN1272
S301
CN302
VKN1268
CN202
VKN1239 C
S201 INSB ASSY
(S) (VWG1883)
(S)
(S) (S)
(S) (S) B
SPINDLE MOTOR
ASSY : VXX2563 VXM1062
(T) (T)
(F) (F)
(T) (T)
(F) (F)
(T)
(F)
(F)
(T) C
(F)
(F)
PICKUP ASSY
(VWY1046)
: RF SIGNAL ROUTE
(F)
: FOCUS SERVO LOOP LINE
(T)
(S)
: SLIDER SERVO LOOP LINE
MSWB
ASSY
(VWR1285)
(VWG1882)
AC 220-240V
50/60Hz
: WY,WY/RD,WYW/SP
AC 110-127V/220-240V D
50/60Hz
: RD/RC,RAM,RL
J
AC POWER CORD
ADG1154 : WY,RL
ADG1127 : WY/RD,WYW/SP
ADG7003 : RD/RC
ADG7017 : RAM
5 6 7
A B C D 8
11
1 2 3 4
DV-505
A
E FLKB ASSY
VWG1876 :WY,WY/RD,WYW/SP
VWG1940 :RD/RC
VWG1934 :RAM
VWG1875 :RL
R128 R138
WY,WY/RD 27k 20k
WYW/SP
RD/RC 16k 2.7k
0
RAM 27k 68k
RL 47k 62k
C114
0.1
B
C113
0.1R197 R198
0 0
C C111
0.1
FL TUBE
12 E
1 2 3 4
5 6 7 8
DV-505
F
PWSB ASSY
SLP4118C51H
VWG1937
D202
:WY,WY/RD,WYW/SP
VWG1880
:RD/RC,RAM,RL
R201
SLP9118C51H
R201
WY,WY/RD, 180
WYW/SP
B
D201
RD/RC, 750
RAM,RL
AC1
AC2 FLKB ASSY
S102 : (OPEN/CLOSE)
S103 : (REV)
H 2/3 S104 : (FWD)
S105 : (STOP)
CN105 S106 : (PLAY/PAUSE)
PWSB ASSY
S202 : FL OFF
REMOTE
RECEIVER
UNIT
G DILB ASSY
C112
(VWG1881)
0.1
R118-R120 D
WY,WY/RD,
WYW/SP 62
RD/RC,
RAM,RL 36
5 6 7
E F G 8
13
1 2 3 4
DV-505
A (VWS1326)
VTL1074 (6/6)
L340
VKF1001
H 2/3 (2/6) (1/6) TP300
1/2
(3/6)
VCO Offset ADJ.
(4/6)
2/2
VKF1001
TP400
! !
VKF1001
TP100
(ROM)
H 2/3
(ROM)
B
S14B-PH-SM3
CN101 (F) H 2/3
(F)
(F)
(F)
(T)
(T)
CN201
J
(F)
CN201
VKN1324
(F)
(F)
(T)
(F)
(T)
(F)
(F)
PICKUP ASSY
(T)
C H 3/3
(S)
(T)
(T)
(T)
(S)
(S)
(F)
R177
(T) 33k
(F) R178
33k 2/2
(T)
CN102 IC171
VKN1445 BA10393F
(S)
1/2
(S) IC171
BA10393F
VKN1416
CN107
CN301
(F)
(S)
D
B
(S)
(F)
(F)
(F)
14 H 1/3 1 2 3 4
5 6 7 8
DV-505
(F)
: RF SIGNAL ROUTE : FOCUS SERVO LOOP LINE
(ROM) (T)
IC506 : ROM DATA SIGNAL ROUTE : TRACKING SERVO LOOP LINE
TC74VHCT245AFT (S)
: SLIDER SERVO LOOP LINE
A
SRM2B256SLMX70
IC504
TC74VHC20FT
AGCOFF
IC501
PD4889A
IC505(1/2)
TC74VHC139FT
IC505(2/2)
H 3/3 TC74VHC139FT
H 2/3 B
VKF1001
TP200
H 2/3
XRESET,DOUT,SBSY,
PW,SFSY,SBCK,LRSY,
ROMCK,ROMXA,MON,
C2F,FG
(ROM)
(T) (T)
(T)
(F)
(F)
(F)
IC201
LC78650NE
(S) (S) C
(F)
(F)
(T) (T)
LD-ON
2/2
R276 R275
150k 33k
H 2/3
1/2
LEVEL SHIFT
D
H 2/3
5 6 7
H 1/3 8
15
1 2 3 4
DV-505
A
H 2/3 DVDM ASSY(2/3)
(VWS1326)
H 1/3
C2F,XRESET
H 3/3
XCSDOLV,DOLV-CD,XWRL,XWRH,
XRD,XLT3,XAMUTE,XDREQ1,
HCPUCK,IR,SEL-IR,XDVRST1,
XAVIRQ0,48/X44,HIBSEL,XCS6,
XDACK1,NAP SW
CN106
VKN1411
H 3/3
ADDRESS
A2-A10
H 3/3
DATA
C
IC605(1/2)
TC74VHC139FT
H 1/3
D X602
VSS1114
20MHz Q771,Q772:
PDTC114TK
IC605(2/2)
TC74VHC139FT
16 H 2/3
1 2 3 4
5 6 7 8
DV-505
H 3/3
H 1/3
H 3/3
H 1/3
(ROM)
(ROM)
B
(ROM) (ROM)
MONITOR OUTPUT
H 1/3
SERVO
H 3/3
H 1/3
H 3/3
VKN1418
CN105
(ROM)
H 3/3
H 3/3
(ROM)
E H 3/3
H 3/3
CN101
H 1/3
D
H 1/3
5 6 7
H 2/3
8
17
1 2 3 4
DV-505
(2/4)
H 3/3 DVDM ASSY(3/3)
(VWS1326)
A H 2/3 (3/4)
(4/4)
H 2/3
H 2/3
H 2/3
H 2/3
(ROM)
(ROM) H 2/3
H 2/3
H 2/3
H 2/3
(COM)
(Y)
(C)
R845
(2/3)
0
(1/4)
(3/4)
S4B-PH-SM3
CN801
CN301
(1/3)
IC813
CY2081SL-611
Video
D Output
H 2/3
I
(4/4)
Level (COM)
ADJ.
(3/4)
(1/4)
(Y)
(2/4)
(C)
H 1/3 (2/4)
(4/4)
H 2/3
(3/3)
H 1/3
18 H 3/3 1 2 3 4
5 6 7 8
DV-505
IC901
H 2/3
HIBSEL,48/X44,XRESET,
XLT3,XAMUTE
H 2/3
1/2
VKN1421
CN802
CN901
(C)
2/2
(COM)
(COM) (Y)
(COM)
I
(COM) C
H 2/3
(C)
1/2
(Y)
(Y)
(Y) VKN1418
CN803
CN191
2/2
I
(C)
(C)
(C)
: AUDIO SIGNAL ROUTE
(ROM)
: ROM DATA SIGNAL ROUTE
(COM)
: COMPOSITE VIDEO SIGNAL ROUTE
D
(Y)
: Y SIGNAL ROUTE
(C)
: C SIGNAL ROUTE
5 6 7
H 3/3
8
19
1 2 3 4
DV-505
A
CN802
(C)
R3080 R5020
(COM)
0
SR IN
0
(C)
(COM)
(C) (C)
B (COM) (COM)
TC7WU04F TC7WU04F
H 3/3 CN801
RD/RC,RAM,RL
ONLY
C
18MHz
Master
Clock ADJ.
H 3/3
CN803
IC101
PD2029A(L)
WY,WY/RD,WYW/SP
ONLY
20 I
1 2 3 4
5 6 7 8
DV-505
I A
AVJB ASSY
VWV1575 : WY,WY/RD,WYW/SP
VWV1574 : RD/RC,RAM,RL
(Y) (Y)
(Y)
(Y)
(C) (C)
D501
(C)
(COM)
MA111 B
(C)
(COM)
(C)
(COM)
(COM)
D601
MA111
R60
R17
0
0
CN100
R20 C
0
82P
L
82P
R16
0
R19
R21
0
WY,WY/RD,
WYW/SP ONLY
(COM)
: COMPOSITE VIDEO SIGNAL ROUTE
(Y)
: Y SIGNAL ROUTE
(C)
: C SIGNAL ROUTE
: AUDIO SIGNAL ROUTE D
5 6 7 8
I 21
1 2 3 4
DV-505
A
NOTE OF SPARE PARTS IN POWER SUPPLY ASSY
• In case of repairing, use the described parts only to prevent an accident.
• Please write the red mark on the board when the primary section of POWER SUPPLY Assy is repaired.
• Please take care to keep the space, not touching other parts when replacing the parts.
AC IN C101
NEUTRAL 2
C104 C103 !
D211
L211 ! P211 VEK1048
C105 T101 13 VZF1058
FG101 ! 10UH
C211 + 1.5A/60V +
B CN102 330/35V D212 C212
5 VZF1061 100/35V
LIVE 1 C112 ! L311 P311 VEK1041
14 D311 ! ! 1.0A/60A
D108 + C114
VZF1045 10UH VZF1060 +
6 S3L20U C313
! Q103 + + IC711
15 C312 ! 56/35V
VZF1062 C311 100/35V I O
NEUTRAL 2 ! D411 330/35V
G CT
!
IC411 VZF1048 CN201
R104 R115 C118 L104 I O
1 GND
56/35V
G CT
C411 + +
C412
VZF1059 R313
CN101
7 R411 2 +12V
16 330/35V 68 2W 3 GND
JMP
8 4 +5V
C111 + R105 5 GND
R109 R108 Q511 R312 C314 6 GND
! R201 10K +3.3V
L103 C116 R116 R512 33/35V 7
! 3 47
22K 8 +3.3V
! R514
+
9 GND
H 1/3
VZF1045
+
VZF1062
D110
!
C117
(2/2) 11 P ON/OFF
+
1SS270A
(1/2)
10
! R205 R204
47/35V
10 +
C711
! C115 IC201 1SS270A
200 1.6K C612
2 AN1431T ! D512 0.01/50V
11 R611 0.01/50V
D106: R206
C107 C108 PS2561L1-1VM 1.5K 3.9 C611
Q511 : 2SC1740S
C
CAUTION : FOR CONTINUED PROTECTION AGAINST RISK OF FIRE,
REPLACE ONLY WITH SAME TYPE NO. 49101.5, MFD BY LITTELFUSE
INC. FOR P211 AND 491001 MFD. BY LITTELFUSE INC. FOR P311.
RKP1751
CN10
!
K
!
MSWB ASSY
C10 0.01/250
(VWG1882)
ACG7010
22 J K 1 2 3 4
1 2 3 4
DV-505
L SCCB ASSY
(VWV1577)
I
CN19
1 2 3
L
4
23
1 2 3 4
DV-505
B C E B C E SIDE A
Transistor
B C E with resistor
D G S D G S
Field effect
D G S transistor
P.C.Board Chip Part SIDE B
B Resistor array
3-terminal
regulator
A LOMB ASSY
C
(VNP1628-A)
(VNP1627-B)
SIDE A
D SPINDLE MOTOR
ASSY
24 A B C D
1 2 3 4
1 2 3 4
DV-505
F PWSB ASSY
E CN102
(VNP1625-B)
SIDE A
G DILB ASSY (VNP1625-B)
B
E CN103
F PWSB ASSY C
(VNP1625-B)
SIDE B
G DILB ASSY (VNP1625-B)
D
1 2 3
F G 4
25
1 2 3 4
DV-505
SIDE A
E FLKB ASSY
F CN201
SIDE B
C
E FLKB ASSY
Q105
26 E
1 2 3 4
5 6 7 8
DV-505
G CN301
A
H CN105
(VNP1625-B)
IC102 Q103
D
(VNP1625-B)
5 6 7
E
8
27
1 2 3 4
DV-505
4.4 DVDM ASSY • This PCB is a four-layered board. Middle layer is mainly connected to Vcc and GND.
IC501
IC601
Q401
|
Q403
IC506
IC401 VC301
IC302
B IC303
Q301
IC701
B
CN301
IC203
IC202
IC807 IC806
Q291
IC204
IC801 IC151
IC161
C IC271
IC171
IC824
Q802 IC206 VR801
Q801
IC902 Q105
IC815 IC816 VR891
Q891 Q455
IC813 Q102
IC814
IC818 Q873
| PICKUP
IC820 ASSY
IC810
IC811
D
(VNP1624-C)
H DVDM ASSY
A
IC505 Q601
IC605 |
Q603
Q771
IC504 Q772
IC502 IC603
IC503
IC602
IC301 IC604
IC703 IC817
IC702
IC201 IC808
IC809
IC205
IC805
IC821
IC802
Q261 C
Q871
Q851
Q831
Q106
Q107 IC901
Q872
Q852
Q832
IC101
Q103 IC804
Q108
|
Q110
Q104
D
(VNP1624-C)
SIDE B
1 2 3
H
4
29
1 2 3 4
DV-505
IC102
IC101
IC201
H CN803
IC191
Q502
Q501
C L
CN100
Q602
Q601
IC701
D H SIDE A
CN802
IC901
30 I
1 2 3
(VNP1626-B)
4
1 2 3 4
DV-505
I AVJB ASSY
A
IC301
|
IC306
Q121
|
Q124
IC102
IC201
Q221 B
|
Q224
Q511
|
Q514
Q521
| C
Q524
IC701
SIDE B D
IC901
(VNP1626-B)
1 2 3
I
4
31
1 2 3 4
DV-505
B
Q101
|
Q103
(VNP1626-B)
Q511
IC411
C
IC711
CN100
I
CN19
Q108
Q107
(VNP1629-A)
H CN101
D
SIDE B
SIDE A
WY, WY/RD, WYW/SP ONLY
32 J K L
1 2 3 4
DV-505
Mark No. Description Part No. Mark No. Description Part No.
FLKB ASSY
VWG1876, VWG1940, VWG1934 and VWG1875 are constructed the same except for the following :
Part No.
Mark Symbol and Description Remarks
VWG1876 VWG1940 VWG1934 VWG1875
R118 – R120 RS1/10S620J RS1/10S360J RS1/10S360J RS1/10S360J
R128 RS1/10S273J RS1/10S163J RS1/10S273J RS1/10S473J
R138 RS1/10S203J RS1/10S272J RS1/10S683J RS1/10S623J
PWSB ASSY
VWG1937 and VWG1880 are constructed the same except for the following :
Part No.
Mark Symbol and Description Remarks
VWG1937 VWG1880
R201 RS1/10S181J RS1/10S751J
33
DV-505
Mark No. Description Part No. Mark No. Description Part No.
AVJB ASSY
VWV1575 and VWV1574 are constructed the same except for the following :
Part No.
Mark Symbol and Description Remarks
VWV1575 VWV1574
IC191 PD0236AM Not used
L191 LAU220J Not used
C191 CEAT101M10 Not used
C192 CKSQYF104Z25 Not used
LOAB ASSY
OTHERS
D FGSB ASSY
SEMICONDUCTOR
PC BOARD LOAB VNP1628
PC101 GP2S27(B)
RESISTORS
A LOMB ASSY All Resistors RS1/10S J
OTHERS OTHERS
CN401 KR CONNECTOR B2B-PH-K-S CN101 KR CONNECTOR 3P B3B-PH-K-S
CAPACITORS
SMEB ASSY C101,C102 CEJA470M6R3
C117,C125-C128 CKSQYB102K50
OTHERS C111-C114 CKSQYF104Z25
PC BOARD SMEB VNP1627
RESISTORS
All Resistors RS1/10S J
34
DV-505
Mark No. Description Part No. Mark No. Description Part No.
35
DV-505
Mark No. Description Part No. Mark No. Description Part No.
C887 CEV470M6R3 R920,R921,R935,R936,R961 RS1/10S0R0J
C211 CKSQYB104K25 R205 RS1/10S101J
C109,C124,C216,C220,C229 CKSQYB105K10 R835,R839,R855,R859,R875 RS1/16S1001F
C234,C261,C275,C308,C326 CKSQYB105K10 R881 RS1/16S1001F
C332,C333,C730,C731 CKSQYB105K10 R834,R854,R874 RS1/16S1201F
C818,C823,C828 CKSQYF105Z16 R823-R825 RS1/16S1500F
C213,C292,C309,C321 CKSRYB102K50 R117,R118 RS1/16S1501F
C105,C106,C108,C146,C147 CKSRYB103K50 R126 RS1/16S1502F
C151,C154-C157,C161,C207 CKSRYB103K50 R241,R247 RS1/16S2202F
C217,C221,C247,C263,C265 CKSRYB103K50 R110,R153,R155,R173,R174 RS1/16S2702F
C276,C318,C320,C620,C705 CKSRYB103K50 R213,R228,R229,R248 RS1/16S2702F
C722,C772,C859 CKSRYB103K50 R152,R156,R158-R164 RS1/16S4702F
C143,C162-C165,C223,C224 CKSRYB104K16 R167-R170,R172,R175,R194 RS1/16S4702F
C242,C273,C274,C311,C312 CKSRYB104K16 R227 RS1/16S4702F
C315 CKSRYB104K16 VR801 (1kΩ) VCP1125
Other Resistors RS1/16S J
C141 CKSRYB222K50
C328 CKSRYB223K25
C262,C271 CKSRYB472K50 OTHERS
C122 CKSRYB473K16 CN101 PH CONNECTOR S14B-PH-SM3
C102,C103,C113,C129 CKSRYF104Z16 CN801 PH CONNECTOR S4B-PH-SM3
TP100,TP200,TP300,TP400 VKF1001
C132-C134,C136,C137,C159 CKSRYF104Z16 CHECKER CHIP
C166,C191,C202-C204,C209 CKSRYF104Z16 CN201 B TO B CONNECTOR VKN1324
C214,C218,C219,C222 CKSRYF104Z16 14P
C226-C228,C235,C237,C241 CKSRYF104Z16
C246,C302,C304,C305,C317 CKSRYF104Z16 CN106 7P FFC CONNECTOR VKN1411
CN107 12P FFC CONNECTOR VKN1416
C322,C402,C403,C405,C407 CKSRYF104Z16 CN105,CN803 VKN1418
C409,C411,C413,C415 CKSRYF104Z16 14P FFC CONNECTOR
C502,C503,C505-C509 CKSRYF104Z16 CN802 17P FFC CONNECTOR VKN1421
C602-C605,C608-C611 CKSRYF104Z16 CN102 20P FFC CONNECTOR VKN1445
C614,C615,C617,C621,C622 CKSRYF104Z16
KN1-KN3 EARTH METAL VNF1109
C702,C703,C707-C721 CKSRYF104Z16 LABEL VRW1634
C732-C734,C736,C738 CKSRYF104Z16 X602 CHIP CERAMIC VSS1114
C740-C742,C771,C791,C800 CKSRYF104Z16 RESONATOR (20MHz)
C802,C805-C812,C816,C817 CKSRYF104Z16 X501 CHIP CERAMIC VSS1115
C819-C822,C824,C825,C827 CKSRYF104Z16 RESONATOR (10MHz)
36
DV-505
Mark No. Description Part No. Mark No. Description Part No.
COILS
L101,L191,L201,L301,L801 LAU220J
J POWER SUPPLY ASSY
L901 LAU220J SEMICONDUCTORS
L903 PULSE TRANS. PTL1003 IC201 AN1431T
L902 NOISE FILTER RTF1167 IC411 VZF1048
L302,L303 CHIP BEAD VTL1098 IC711 VZF1060
Q101,Q103 VZF1062
Q102 2SC3377
SWITCH
S30 VSH1020 Q511 2SC1740S
D511 10ELS2
CAPACITORS D512,D514 1SS270A
D105 1SS270A
C103,C203 CCSQCH820J50
D104 MTZJ2.4B
C310,C322 CCSQCH120J50
C320 CCSQCH270J50
D513 MTZJ8.2B
C311 CCSQCH330J50
D106 PS2561L1-1VM
C106,C111,C206,C211 CCSQCH470J50
D103 RD18FB2
D311 S3L20U
C307,C308 CCSQCH470J50
D101 VZF1044
C114,C191,C193,C801,C901 CEAT101M10
C903 CEAT101M10
D108,D110 VZF1045
C503,C603 CEAT102M6R3
D211 VZF1058
C300 CEAT470M16
D411 VZF1059
D212 VZF1061
C101,C201 CEAT471M16
C107,C207 CEGA470M25
C104,C113,C204 CEZA470M25 OTHERS
C112,C212,C224,C904 CKSQYF103Z50 P311 FUSE (1A) VEK1041
C102,C105,C115,C192,C202 CKSQYF104Z25 P211 FUSE (1.5A) VEK1048
F101 FUSE (2A) VEK1049
C205,C228,C301-C306,C309 CKSQYF104Z25
C321,C333,C401,C502,C511 CKSQYF104Z25
C516,C602,C802,C902,C906 CKSQYF104Z25
C911-C913 CKSQYF104Z25
C108,C208
VC301 (20pF)
CQMBA332J50
VCM-008
K MSWB ASSY
SWITCH
S10 ASG1006
RESISTORS
R508,R518,R607 RN1/10SC75R0D
R106,R111,R206,R211 RN1/10SE4702D CAPACITOR
Other Resistors RS1/10S J C10 (0.01µ/AC250V) ACG7010
OTHERS OTHERS
CN501 4P MINI DIN SOCKET AKP7008 CN10 AC CORD SOCKET RKP1751
CN301 KR CONNECTOR B4B-PH-K-S
JA101 4P PIN JACK DKB1038
JA801 OPTICAL MODULE GP1F32T
JA401 REMOTE CONTROL
JACK
RKN1004
L SCCB ASSY
SEMICONDUCTORS
PCB BINDER VEF1040
Q100 2SA933S
JA601 1P PIN JACK VKB1063
Q107,Q108 PDTC124EK
JA901 1P PIN JACK (NI,BLK) VKB1077
D114 MA111
CN19 8P FFC CONNECTOR VKN1239
D101,D103 UDZS5.1B
CN191 14P FFC CONNECTOR VKN1245
OTHERS
PCB BINDER VEF1040
JA100 RGB CONNECTOR VKB1037
CN100 8P FFC CONNECTOR VKN1239
PC BOARD (SCCB) VNP1629
37
DV-505
6. ADJUSTMENT
6.1 ADJUSTMENT ITEMS AND LOCATION
Adjustment Points (PCB Part)
DVDM ASSY AVJB ASSY
SIDE A 1
1 VC301
3
13 1 VR801
CN201 IC813
14 2
CN201 IC801
1,2 : FE
3,4 : GNDS Adjustment Items
5,6 : RFO
7,8 : GNDS
9,10 : TE [Mechanical Part]
11,12 : VREF
13 : TDO 1 Tangential Skew and Radial Skew Coarse Adjustment
14 : FDO
IC701 2 DVD Jitter Adjustment
IC302
1 [Electrical Part]
VC301 1 18MHz Master Clock Adjustment
2 1
2 VCO Offset Adjustment
CN101
1 2
Tangential adjustment screw Note 1:
Remove the tray when adjusting
1 2
the tangential and radial
Radial adjustment screw
adjustment screws.
Note 2:
After the adjustment, stabilize
the screw with an adhesive.
38
DV-505
CD test disc (ABEX-784) DVD test disc (DVD-MJK1) Screwdriver (medium) Screwdriver (small)
CH1 CH2
(X) (Y)
Dual-trace oscilloscope
(with delay)
Precise screwdriver Screwdriver (large) Screwdriver (medium) Frequency band 40MHz
Frequency counter
Test mode remote control
Display digit 8-digit unit (GGF1067) Hexagonal screwdriver
TV monitor
LEVEL JITTER
X1
27M
39
DV-505
ESC TEST
POWER
GGF1067
Test mode
ON remote control
unit
TEST 2
+ TILT-OFF
TRKG-OFF e TILT-OFF(N)
TRKG-ON
TEST 5
<TRACKING ON PLAY>
TILT-OFF
TRKG-ON
ESC
POWER
OR
GGF1067
OFF Test mode
remote control
unit
40
DV-505
Electric
point
Electric
point
EXCHANGE PCB ASSY
Key input the number with the test mode remote control unit (GGF1067).
41
DV-505
Mechanism
assy RF(11T)
Tangential
• Test mode Max.
Adjustment
TRKG → OFF Screw
• Play the DVD test disc
∗ See “Adjustment
at outer track. points”.
Mechanism RF(11T)
assy
Player Radial
Adjustment Max.
Screw
∗ See “Adjustment
points”.
START
DVDM ASSY
CH1 CH2
(X) (Y) Oscilloscope
CN201
V: 50mV/div.
H: 0.5µsec/div.
Probe (10:1) AC mode
RFO 5
Mechanism
assy
Tangential
Adjustment
• Test mode Screw JT:Min.
TRKG → ON ∗ See “Adjustment
• Play the DVD test disc points”.
at outer track
(around #1F0000).
JT[0000] 0280
VIDEO OUT VIDEO IN
Mechanism
assy TV monitor
Player JT:Min.
Radial
Adjustment
Screw CHECK
START ∗ See “Adjustment
points”. Jitter < 6.0 nS
DVDM ASSY
Probe (10:1)
RFO 5 EQ X1
27M
UNIT
Jitter Meter
42
DV-505
AVJB ASSY
• Normal mode
• Power ON
27MHz ± 20Hz
VC301
Player
START
DVDM ASSY
IC813 6
Frequency counter
1.9V ± 0.1V
DVDM ASSY
• Normal mode
• Play the DVD test disc
GND
VC301
Player
CH1 CH2
START (X) (Y)
Oscilloscope
DVDM ASSY V: 50mV/div.
Probe (10:1) H: 10msec/div.
DC mode
IC302 1 TV trigger
43
DV-505
• Normal mode
• Still the DVD test disc 1Vp-p
100% White Screen. DVDM ASSY
VR801
VIDEO
OUT
VIDEO
IN
44
DV-505
Player status
REPEAT B
Play Stop
LASER DIG/ANA DISP TEST 3
DISC SR
Clamp + Focus sweep
(Up and Down)
TEST ESC TEST CX
MODE
Tray ×3 ×3
STILL
STEP
1 2 3 CLEAR
Tray Move REPEAT A
Tray Open 4 5 6 +10
Tray Disc clamp
open
7 8 9 0
TEST 2 TEST 5
+10 FRM/TIM CHAP CHP/TIM SEARCH Clamp +
Play
Search to SPDL ON,
3
input frame # PIONEER SERVICE GGF1067 TRK servo OFF
1
TRK
servo TRK servo
8 # 3183 OFF ON
TRK TRK servo
3 servo
ON OFF
CHP/TM
TV Monitor Display
Character in bold : Item name
: Information display Remote control code
45
DV-505
7. GENERAL INFORMATION
7.1 DISASSEMBLY
BONNET DVDM ASSY
1
1 1
1
4 1
4 1
1
2
2 3
DISC TRAY 5
2 1
POWER
2
OPEN/CLOSE
DVDM ASSY
DVDM ASSY
1 6
3
6
2
46
IC802
MB811171622A-100FN
IC601 16M bit SDRAM
PD3381A CODE Buffer
(Video, Audio, Sub-picture,GUI)
IC702 System CPU
HM514800CJ-7 (32 bit RISC)
4M bit DRAM
7.2 BLOCK DIAGRAM
Mechanism
Control
CPU IC101
PD4890A
Loading
Motor Display
CPU
Mechanism Key-SW
sense SW & Display
47
DV-505
DV-505
FRONT PANEL
Disc illumination Open/Close 0 button
Turned off when a disc other
STANDBY indicator than a DVD is played back.
STANDBY
0
POWER
STANDBY/ON
'
DIGITAL VIDEO
with
REAR PANEL
Digital Output Jack (Coaxial)
This is used for output of the digital audio signal
recorded on CDs and Video CDs. Depending on the Coaxial Connect to the coaxial jack, and select PCM from the menu.
Regular AV amp
components you connect this digital output to, noise
Your Optical Connect to the optical jack, and select PCM from the menu.
may be generated.
amp
When connecting to an AC-3 compatible component, AC-3 compatible Coaxial Connect to the PCM/ jack, and select PCM/DOLBY DIGITAL from the menu.
use the PCM/ jack. (Refer to the chart on the amp
Optical Connect to the optical jack, and select PCM/DOLBY DIGITAL from the menu.
right.)
AC IN
DIGITAL OUT AUDIO OUT
R L
PCM/Ÿ
PCM/Ÿ(OPT) VIDEO OUT S-VIDEO OUT CONTROL
1 TV SYSTEM
1 2
IN
NTSC PAL AUTO
2
48
DV-505
DISPLAY WINDOW
49
DV-505
REMOTE CONTROL
PREV NEXT
Enter button (ENTER)
4 ∞
¢
Previous button (PREV 4)
REV PAUSE PLAY FWD
1 8 3 ¡
Next button (NEXT¢)
STOP STEP
50
DV-505
8.2 SPECIFICATIONS
• For DV-505/RD/RC, RAM and RL types
General Digital audio characteristics
System ....................................... DVD system,Video CD system and
Compact Disc digital audio system Frequency response 4 Hz to 22 kHz (DVD fs: 48 kHz)
Laser ................................ Semiconductor laser: wavelength 635 nm 4 Hz to 20 kHz (CD)
Power requirements: .................. AC 110-120 V/220-240 V, 50/60 Hz S/N ratio 115 dB (EIAJ)
Power consumption ................................................................... 21 W Dynamic range 97 dB (EIAJ)
Weight ..................................................................... 2.9 kg (6 lb 6 oz)
Dimensions .................................... 420 (W) x 284 (D) x 104 (H) mm Total harmonic distortion 0.003 %
(16 9/16 x 11 5/16 x 4 in.) Wow and flutter Limit of measurement
(Not including protruding cables, etc.) (±0.001% W. PEAK) or lower (EIAJ)
Operating temperature ................... +5°C to +35°C (+36°F to +96°F)
Operating humidity ............................. 5% to 85% (no condensation)
Other Terminals
S-Video Output Optical digital output (PCM/ ) ........................... Optical digital jack
Y (luminance) - Output level .......................................... 1 Vp-p (75Ω) Coaxial digital output (PCM/ ) ........................................ RCA jack
C (color) - Output level ........................................... 286 mVp-p (75Ω) CONTROL IN ............................................................. Minijack (3.5ø)
Jacks ........................................................................... S-VIDEO jack
Accessories
Video Output Remote control unit ......................................................................... 1
Output level ......... 1 Vp-p (75Ω when loaded, synchronous negative) AA (LR6) dry cell batteries .............................................................. 2
Jacks .......................................................................................... RCA Audio cord ....................................................................................... 1
Video cord ....................................................................................... 1
Power cord ...................................................................................... 1
Audio Output (2 pairs) Operating Instructions ..................................................................... 1
Output level
During audio output ............................... 200 mVrms (1 kHz, –20 dB)
Number of channels ........................................................................ 2
NOTE:
Jacks .......................................................................................... RCA The specifications and design of this product are subject to change
without notice, due to improvement.
Accessories
Audio cord (VDE1033) Remote control unit (VXX2540)
(L=1.5m) White (CU-DV008)
PO
W
ER
AU
D
IO
SU
BT
IT
LE
TIT
O LO
AN
PE S
LE
N E
G
/
LE
0
M
EN
D
IS
U
PL
PR
AY
2
EV
5
4
R
EN
EV
R
1
ER
ET
U
R
PA
3
SE
8
Red
ST
PL
O
N
1
AY
P
7
EX
3
(L=1.5m)
4
FW
ST
D
¡
EP
PR
7
OG
3
RA
C
M
LE
8
R
AR
C
6
EP
C
H
P/T
EA
• Warranty card
T
IM
E
+1
9
R
EP
0
O
EA
A-B
D
T
E
LA
0
R
ST
• Operating Instructions
AN
M
EM
D
O
O
M
CO
ND
ITIO
N
Batteries ..... 2
ADG1154 (WY, RL Type)
ADG1127 (WY/RD, WYW/SP Type)
ADG7003 (RD/RC Type)
ADG7017 (RAM Type)
51
SERVICE GUIDE
ORDER NO.
RRV1896
DVD PLAYER
DV-505
DV-S9
DVD LD PLAYER
DVL-909
CONTENTS
1. CIRCUIT DESCRIPTION ...................................... 2
2. CIRCUIT DESCRIPTIONS
FOR DV-S9 AND DV-09 ............................... 10
3. TEST MODE ....................................................... 13
4. IC INFORMATION .............................................. 22
5. FL INFORMATION .............................................. 47
PIONEER ELECTRONIC CORPORATION 4-1, Meguro 1-Chome, Meguro-ku, Tokyo 153-8654, Japan
PIONEER ELECTRONICS SERVICE, INC. P.O. Box 1760, Long Beach, CA 90801-1760, U.S.A.
PIONEER ELECTRONIC (EUROPE) N.V. Haven 1087, Keetberglaan 1, 9120 Melsele, Belgium
PIONEER ELECTRONICS ASIACENTRE PTE. LTD. 501 Orchard Road, #10-00 Lane Crawford Place, Singapore 0923
c PIONEER ELECTRONIC CORPORATION 1998
T - IZM APR. 1998 Printed in Japan
2
IC802
DV-505
MB811171622A-100FN
IC601 16M bit SDRAM
PD3381A CODE Buffer
(Video, Audio, Sub-picture,GUI)
IC702 System CPU
HM514800CJ-7 (32 bit RISC)
4M bit DRAM
IC701 VBR Buffer
PD4833A IC603 IC604
VYW1536 TC551001BFL-85 Memory Controller
LSI-11 FLASH
IC301 RAM
DRAM I/F ROM
TLC5540INS CPU
HA Sync (bus arbitor)
A/D I/F
Spindle TA Demod
DV-505, DVL-909, DV-S9
FA OEIC
Motor
CPU
Slider I/F MPEG2 Sub- GUI
ECC & Video picture
ID Reg. Program Stream SYSTEM
Decoder Decoder Decoder
Spindle DMA (DMUX)
control
SREO SREO
TE
1.1 OVERALL BLOCK DIAGRAM
Mechanism
Control
CPU IC101
PD4890A
Loading
Motor Display
CPU
Mechanism Key-SW
sense SW & Display
IC601 16M bit SDRAM
Key-SW Display System CPU PD3381A
& Display CPU (32 bit RISC) CODE Buffer
IC702 (Video, Audio, Sub-picture,GUI)
IC101 HM514800CJ-7 IC802
PD4890A MB811171622A-100FN
4M bit DRAM
IC701 VBR Buffer IC602
PD4833A IC603 PDK026A IC604
VYW1536 TC551001BFL-85
LSI-11 GUI Memory Controller
IC301 ROM RAM
ROM
TLC5540INS DRAM I/F
(bus arbitor) CPU
HA Sync I/F
TA A/D Demod
Spindle OEIC
Motor FA
CPU
DV-S9 and DV-09
S/PDIF
DVD/V-CD Digital
IC201 Out
LC78650NE IC801 AV Decoder
CD DSP MB86371 (MPEG2 Decoder)
CD PCM
EFM
Decoder CD Digital Out
Mechanism IC501
Servo Control PD4889A
DSP CPU
Mechanism 8
10
sense SW VIDEO DAC FILTER AMP. DRIVER Cb
DRAM ENCODER,
10
COPY GUARD DAC FILTER AMP. DRIVER Cr
IC951
DV-S9 Only M65677FP DRIVER Y
Component
DIRB Video Out
IC861 AUDIO
Digital In CD0015AF 96/24 DAC L ch (Analog)
(OPTICAL) DATA
DIGITAL HIBIT LEGATO S L ch (Analog)
SELECTOR
INTERFACE 96/24 DAC R ch (Analog)
(COAXIAL) RECEIVER IC811 R ch (Analog)
AUDIO
TRANSFORMER Audio Out
AUDIO
AC IN
POWER SUPPLY
3
DV-505, DVL-909, DV-S9
DV-505, DVL-909, DV-S9
DVL-909
IC601
4Mbit DRAM IC702 PD3381A
VBR Buffer HM514800CJ-7 System CPU
IC701 (32bit RISC)
PD4833A
IC603 IC602 IC604
LSI-11
DRAM I/F FLASH GUI
(Bus Arbiter) RAM
ROM ROM
Sync
HA Demod CPU
A/D
TA TA OEIC I/F
SPDL FA FA ECC & ID Reg.
Motor Program Stream
Slider Slider TE DMA
Spindle CD-ROM
GEN
Control Sync gene
For CLD For DVD Sub-code Buffer
Sub-CPU 27M
I/F CD PCM
CD Digital out
16M
16M
CD PCM
CD DSP CD Digital Out
27M
IC 201
LC78650E-P IC 501 IC 813
PD4889A CY2081SL 36M
EFM Decoder -611
Mechanism
Servo DSP Control
CPU
XRESET 4
SHAKE
16M
18M
Mecha. DVD TILT ERR
SW
IC352 Analog L
25 15
4 CA0002AM 14
Analog R
Analog Audio
Phillips Code
ACOM
IC500 IC101
27 10 37 A/D PD6159B PD3212A
IC400 Dual DVP Memory
LA7134M SPDL Cont.
Cont 14-21 65-72 (with DNR) 44-51
VDEM
VCXO ERR
4
DV-505, DVL-909, DV-S9
MIX
Front Section
FL TUBE
FL A.B.
Copy Gurd
DAC Cont.
NTSC
/PAL DAC
REMOTE
Encode SENSOR
DAC Key
27M AV Sync
Controller
AC3/MPEG1
36M Audio Decoder
DVD/V-CD S/PDIF
AV Decoder
AC-3/PCM Digital
PCM Digital
DVD C.
DVD Y.
SEL IR
DATA
Hi-Bit
Key
PD
IR
X311 2
384 × 44.1k
(16M) 3 SR IN
VCXO Sel IC203
TC74HC157AF
4 CLK SR OUT
8
9 L
Hi-Bit 25 Sel L OUT
14 10
IC202
PD0236AM D/A 5 R
Sel R OUT
6
Y (DVD)
3
4
IC301 33
Y (LD) Y OUT
D/A
CXD2046Q 5
1 IC620
Y/C SEP.
1-8 36
C (LD) C OUT
D/A 15
2
IC620
TC74HC4053AF Comp. OUT
MYCB ASSY
CLDM ASSY
5
DV-505, DVL-909, DV-S9
DVD SETUP
MIRR Modulation
Measurement
RF AGC ON
T Servo ON
SLDR Servo ON
LD ON
Sweep UP → Down
F Gain Adj.
T Gain Adj.
Focus Lock
AFB Adj.
(Auto Focus Bias)
Yes
SPDL ACCEL
Layer Det.
ATB ON
Lead-in Search
PLAY
LDON
UP
UP
FDO
FE
DRF
(FOK)
6
DV-505, DVL-909, DV-S9
179
RF IC101 RFO
OEIC 3 50 3 200
RFIC IC301
CLK | 8 bit |
A/D
32 (27M) 10 207
12 IC701
RF LSI II
176
APC
178
AFC
180
IC302 ASC
(1/2) 177
159
41 VCO 161 163 166 167 95
IC201 FPWM
DIGITAL VPWM
FG SERVO
57 31 PPWM
IC271 RPWM
48 (2/2)
SPDO DUTY50
SPDL +
12 V165
SPDL IC161 IC271
SPDO
M DRV 25 (Compatible) (1/2)
13
SPDL -
(Base) FG
7
DV-505, DVL-909, DV-S9
OEIC gain = H
FCS AMP gain up More than 0.5V
Lens sweep
OEIC gain = H
Checking Yes
the sine wave
NO DISC
Disc determination
END
8
DV-505, DVL-909, DV-S9
102,107,108,111
IC601
SI1,SO1 PD3381A
16
IC101 SCK1,XRDY
PD4890A IC604 IC603 IC602
13
System
Work FLASH GUI
Mode Control Cont.
22 RAM ROM 4M ROM
(FL Cont.)
21
DATA,ADDRESS
MAIN BUS IC801
MB86371
POWER ON
AV-Dec.
Remote XRESET MAD0–MAD7
KEY
Sensor
142 151
26
72
PD4833A PD4889A LC78650E-P
LSI-11 Mech. Cont. Digital
19
65
(DVD) Servo
39
77 8 10
POWER SUPPLY
ASSY
SO1,SI1
DVDP PK
SCK1
19 21
Slider SLDPOS LD/DVD
Position 9 IC101 XLPO Carriage
SW 56 Out position SW
PD0260A2
33
SW 54
24 25
IC803 IC171
Tilt /
Loading M Tilt / Loading Turn
M
Motor Drive Drive
CLD MAIN
XRDY LT1
13 102
IC101 IC601 SCK
LT1
PD4890A 46 65 PD3381A
SCK1 SI
Mode Control 14 111 System
(FL Cont.) SO1 Cont.
15 107
DATA
SI1
16 108 SO
Timing Chart
If there is no communication for 2 sec.,
Mode Cont. turn off the power and reset.
9
DV-505, DVL-909, DV-S9
Non-linear
BPF
circuit
Horizontal edge generation
Delay
10
DV-505, DVL-909, DV-S9
CLAMP Y
ANR1
ANR2
Amp.
BF
IC952 Y Analog
LPF CLAMP Y
M65677FP NR
NTSC Amp.
ENCODER C
LPF C
CLAMP CVBS
11
DV-505, DVL-909, DV-S9
2.2 DIRB BLOCK (DIRB ASSY) 2.3 96K, 24-Bit, HIBIT LEGATO S
(DV-S9 ONLY) SYSTEM (AUDIO ASSY)
The two major purposes of the DIRB block are the following: All 16-bit and 20-bit sources are converted to 24-bit data by IC101,
(1) Switching between data reproduced from a disc and a data signal which lets a 24-bit data pass through.
in DAC mode As PCM1702P is a 20-bit D/A converter, processing of the upper
(2) Data decoding in external input mode (DAC mode) 20 bits is assigned to it by the shift register.
The lower 4 bits are converted from serial to parallel, then the
(1) Switching Between Data Reproduced from a significance of each bit is converted digital to analog, functioning
Disc and a Data Signal in DAC Mode as a 4-bit D/A converter for the lower 4 bits.
By adding the lower 4 bits to the upper 20 bits in the low-pass &
The signal switching is performed at IC811, sending 3-line data
ADD block, D/A conversion is achieved for 24 bits.
(LRCK, BCK and DATA) to the AUDIO Assy. The switching
control line (DAC MODE) is supplied from the DVD MAIN Assy. Hi Bit
The master clock (MCK) is generated by a crystal on the AUDIO IC101
Assy when reproducing a disc, and by IC861 in DAC mode. MCK
is sent to the AUDIO Assy via RXP.
Legato S
(2) Data Decoding in External Input Mode (DAC IC111
Mode)
Serial to Parallel
When the user selects DAC mode, the DAC MODE port is set to H Shift Register and Significance
and VCO in IC861 starts oscillating. (VCO does not oscillate in TC74HC164AF Conversion
any other modes than DAC mode.) When there is a toss link of an TC74HC163AF
external input or a coaxial digital input, the digital input signal is
sent to IC861 from RXP of CN801, generating 3-line data D/A Converter
corresponding to the input sampling frequency. At the same time, PCM1702P
the master clock (MCK) to be used in DAC mode is also generated.
For a 96kHz input, the MCK frequency is divided by 2 by IC831.
Low-pass
& ADD
When the user selects the internal clock as the system clock, the
clock generated by the crystal on the AUDIO Assy is sent to the
DVD MAIN Assy. When the user selects an external sync as the
system clock, the following parameters are used. Analog Output
16M clock in 18M clock in 16M clock sent to 18M clock sent to
FS(kHz)
the AUDIO Assy the AUDIO Assy the DVD MAIN Assy the DVD MAIN Assy
32 Oscillates Oscillates Crystal 16M clock Crystal 18M clock
44.1 Stops oscillating Oscillates DIR 16M clock Crystal 18M clock
48 Oscillates Stops oscillating Crystal 16M clock DIR 18M clock
96 Oscillates Stops oscillating Crystal 16M clock DIR 18M clock
IC831
Clock Selector
IC861
IC835
DIR
1/2 Divider
CN801 CN811
12
DV-505, DVL-909, DV-S9
3. TEST MODE
3.1 HOW TO ENTER THE TEST MODE (5) Pause
There is the three following methods in an enters of the test mode. 1. It becomes pause condition by pressing [CX] (0E) key of the
1. Short-circuit the terminals (TP6006 and TP6007) for test mode remote control unit in the play.
entry at the side of the system control IC (IC601) of DVDM ASSY, 2. Pause ON/OFF changes alternately by pressing [PAUSE] (18)
and turn the power on. key in the play.
2. Input [ESC] key and [TEST/RANDOM] key of the test mode
remote control unit in order under the power on condition. (6) Search Address Input Entry
3. Connect a personal computer with the RS232C terminal (CN106), It becomes the address input mode when [+10] key (1F) is pressed.
and input entry command (TE) of test mode from the personal (indication for the most significant digit : > )
computer. Indicate the last address as the initial condition in this time.
Note: FL indication and LED come all to light until key operation Only in case of DVD, addition search (indication for the most
is done when entering the test mode. significant digit : + ) and subtraction search (indication for the most
significant digit : – ) are able to select in order by pressing [+10]
3.2 RELEASE THE TEST MODE key continuously.
The address where input value was added to the present address is
There is the three following methods in a release of the test mode.
make to search with addition search.
1. Turn the power off.
The address where input value was subtracted to the present address
2. Press [ESC] key of the remote control unit. At this time, reset it
is make to search with subtraction search.
for a while except for during the LD and CDV set.
In case of CD is only absolute time search.
3. Connect a personal computer with the RS232C terminal (CN106),
Also address clear and release from the address input mode are able
and input normal mode entry command (NE) from the personal
to perform by 2 steps by pressing [CLEAR] (45) key.
computer.
13
DV-505, DVL-909, DV-S9
14
DV-505, DVL-909, DV-S9
15
DV-505, DVL-909, DV-S9
16
DV-505, DVL-909, DV-S9
(3) There are three methods for entering a search address: (5) If disc-type designation is forcibly executed during a mode other
Absolute address designation than Checker mode, the system controller will abandon disc-
→ Searching for the address entered (indication for the most type designation after setting the mechanism controller.
significant digit :>) Therefore, after startup of the player, disc sensing will be
Additional input performed again for safety.
→ Searching for the address with the current ID number plus If disc-type designation is forcibly executed during Checker
an entered number mode, as disc-type designation is not abandoned, playback will
(indication for the most significant digit :+) be immediately started.
Subtractive input
→ Searching for the address with the current ID number minus (6) A background color change in order of blue → green → light
an entered number(indication for the most significant digit :–) blue → red → purple → yellow → gray → black → with the [2/
The above modes can be changed by pressing [10] key. R] key.
Note : A number for addition or subtraction must be entered in It changes in order of gray → yellow → purple → red → light
hexadecimal. blue → green → blue → black → in the case of the [1/L] key.
(7) In case of PD0260A∗, tilt servo on function may not move with
DVD.
• Screen Composition
Character in bold : Item name
: Information display Remote control code
Caution :
The first screen and second screen switch by
pressing [DISPLAY] key of the remote control FL controller version
unit. GUI-ROM number
It is only a version display part on the lower
right of the screen those contents of display Part No. of flash ROM and system controller
change. Part No. of DVD mechanism controller
ATB : ON/OFF information display and AGC Part No. of CLD mechanism controller
manual establishment display deleted with the
second generation.
Second screen display (at lower right portion of the screen)
17
DV-505, DVL-909, DV-S9
(2) Code indication of the remote control unit [R-∗∗∗∗] (12) Error rate indication
The code for the key pressed on the remote control unit, which is C1 error value of CD [ER-C1 ∗∗∗∗ ]
received by the FL controller, is displayed while the key is pressed. C1 error value of DVD [ER-∗∗∗∗ ∗∗∗∗]
In the case of the double code, the second code will be displayed.
(13) Internal operation mode of mechanism controller
(3) Key code indication for the main unit [K-∗∗]
[MM-∗∗:∗∗]
The code for the key pressed on the main unit, which is received by
Internal mechanism mode (2 digits) and internal mechanism step (2
the system controller, is displayed while the key is pressed.
digits) of the mechanism controller
Note : For details, see the specifications of the mechanism controller.
(4) Tilt error value, Tilt servo status [TILT-∗:∗∗∗]
Tilt error value : [0] to [F]
(14) Disk sensing [DSC-∗∗∗]
Tilt servo status :
The type of discs loaded is displayed.
Tilt neutral [N]
[DVD], [CD ], [CDV], [LD ], [VCD], [ ]
Tilt servo on [ON]
Tilt servo off [OFF]
(15) Pickup [PU-∗∗∗]
(5) Tracking status [TRKG-∗∗∗] The pickup being operating is displayed.
DVD [DVD]
Tracking on [ON]
CLD [CLD]
Tracking off [OFF]
(9) AGC setting [AGC-∗∗] (19) Revision of the system controller [S:∗.∗∗∗/∗.∗∗]
AGC on [ON] Revision number of the external ROM part (flash ROM) of the
AGC off [OFF] system controller <Front>
Revision of the internal ROM part of the system controller
<Rear>
(10) Output video system [V-∗∗∗∗]
NTSC system [NTSC]
PAL system [PAL ]
Auto-setting [AUTO]
18
DV-505, DVL-909, DV-S9
(26) Part number of the DVD mechanism controller Using the Function in Test Mode (The Remote
(Example) PD4889A0 → 4889A0
Control Keys to be Used are Indicated in Brackets)
(1) Set the DVD or CD to trace (playback) state with AGC OFF.
(27) Part number of the CLD mechanism controller (2) Press [TEST] and [DIGITAL/ANALOG].
(Example) PD0260A2 → 0260A2 The current jitter value appears to the right of “JT: ” on
the display. The jitter value keeps changing unless any additional
(28) AV1 classification [AV1 : ∗∗∗] key operation is made.
RAM, E/A, S/C
Note : Although a value may be displayed on the screen even with
(29) Flash ROM size [FLSH : ∗∗] AGC ON, this is NOT a jitter value.
The jitter value with AFB ON cannot be displayed (see the
8M : 8M bit, 4M : 4M bit
next section). The jitter value with AFB ON can be obtained
only by directly measuring the voltage at the JV connector
3.8 DESCRIPTIONS OF NEW FUNC- (pin 94) of the servo DSP (LC78650).
TIONS IN TEST MODE
3.8.1 Error Rate
Overview
The error rate of CDs can be measured on basic models, such as the
DV-505, and that of CDs as well as LDs with sub-Q codes can be
measured on DVD/LD-compatible models, such as the DVL-909.
The value is displayed in decimal and indicates the number of C1
errors (including the corrected ones) counted during the specified
measurement time.
An indeterminate measurement result may be caused by a dirty disc,
decentering, surface deflection, birefringence (double reflection),
or a pickup problem (dirty lens, etc.), misadjustments of the pickup,
improper automatic adjustment, or incomplete adjustments. On the
manufacturing line, the value is used for yes/no decision of pickups.
Normally, for a measurement for 5 seconds, the value may be less
than 10 with a clean disc and less than 100 with a disc with some
damage.
19
DV-505, DVL-909, DV-S9
20
DV-505, DVL-909, DV-S9
21
DV-505, DVL-909, DV-S9
4. IC INFORMATION
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
• List of IC
PD4890A, PD0260A2, PD0261A2, LA9700M, BA6195FP, LC78650E-P, PD4889A, SRM2B256SLMX70, VYW1536, PD3381A,
MB86371, MB811171622A-100FN, CY2081SL-611, PD2058A
• Block Diagram
47 P00
TO0/P30 43 16-bit TIMER/ 44
PORT0 P01-P03
TI0/INTP0/P00 47 EVENT COUNTER 46
31 P04
TO1/P31 42 8-bit TIMER/ 21
PORT1 P10-P17
TI1/P33 40 EVENT COUNTER 1 28
TO2/P32 9
41 8-bit TIMER/ PORT2 P20-P27
TI2/P34 39 EVENT COUNTER 2 16
36
WATCHDOG TIMER PORT3 P30-P37
43
6-bit UP/DOWN
CI0/INTP3/P03 44
COUNTER 7 P80
PORT8
6 P81
SI0/SB0/P25 11
SERIAL 78K/0 ROM
SO0/SB1/P26 10 1-5
INTERFACE 0 CPU CORE PORT9 78-80
P90-P97
SCK0/P27 9
SI1/P20 16 69,70
PORT10 72-77 P100-P107
SO1/P21 15
SERIAL
SCK1/P22 14
INTERFACE 1
STB/P23 13 61
PORT11 P110-P117
BUSY/P24 12 68
ANI0/P10- 21 53
PORT12 P120-P127
ANI7/P17 28 RAM 60
17 RESET
BUZ/P36 37 BUZZER OUTPUT 34 X1
SYSTEM
35 X2
CONTROL
CLOCK OUTPUT 31 XT1/P04
PCL/P35 38
CONTROL 32 XT2
8,52 33 48
VDD VSS IC
22
DV-505, DVL-909, DV-S9
• Pin Function
No. Mark Pin Name I/O Function
1 P94 G7
2 P93 G6
3 P92 G5
4 P91 G4 O FL timing output H : ON
5 P90 G3
6 P81 G2
7 P80 G1
8 VDD VCC − Power supply pin
9 P27 (NC)
10 P26 (NC) O Not used
11 P25 (NC)
12 P24 LAMP O DVD lamp ON/OFF H : ON
Communication handshake line with the system controller
13 P23 XREADY O
L :Permit the communication
14 P22 SCK I/O Communication clock output with the system controller
15 P21 SO I/O Communication data output with the system controller
16 P20 SI I Communication data input with the system controller
17 RESET RESET IN I Reset input L : reset
(NC) (DV-505) O Not used
18 P74
SIDE A LED (DVL-909) O SIDE A LED ON/OFF L : ON
(NC) (DV-505) O Not used
19 P73
SIDE B LED (DVL-909) O SIDE B LED ON/OFF L : ON
20 AVss Vss − GND pin
21 P17 POWER ON O SW 5V ON/OFF H : ON
22 P16 RESET OUT O System reset output L : reset
23 P15 (NC)
O Not used
24 P14 (NC)
25 P13 KIN1
I Key input
26 P12 KIN0
27 P11 MS1
I Destination judgement input
28 P10 MS0
29 AVDD AVDD − Power supply pin
30 AVREF AVREF − Reference voltage
31 P04 P04 I Not used
32 XT2 (NC) − Not used
33 VSS VSS − GND pin
34 X1 X1 I
Connect a microprocessor clock
35 X2 X2 −
36 P37 (NC)
37 P36 (NC) O Not used
38 P35 (NC)
39 P34 P34
I Not used
40 P33 P33
23
DV-505, DVL-909, DV-S9
24
DV-505, DVL-909, DV-S9
• Pin Function
No. Pin Name I/O Function
1 VCC I Power supply pin Apply 5V ± 10%
2 RWC O DSP read/write command signal output "L"= Read "H"= Write
3 XPLAY O Signal output during spindle servo "L"= During servo "H"= During acceleration, brake and stop
4 CLK:SCK3/CQCK O DVP/DSP clock switch "H"= DVP "L"= DSP
5 XCD O LD/CD switch signal output "L= CD "H"= LD
A/D • This signal is A/D converted as the tilt servo control input. Control the tilt motor so that this signal
6 TILT ERR I
becomes 2.5V.
7 TRK BAL ERR I A/D • Tracking balance error signal input This signal is A/D converted as the tracking offset control input.
A/D • This signal is A/D converted as the slider servo control input.
8 SLD ERR I
Control the slider motor so that this signal becomes 2.5V.
A/D • Pickup position detection switch input
9 SLD POS I
Detect the position by reading A/D input value which each switches are resistance divided.
10 FSEQ I Subcode sync. confirmity detection signal input "L"= Not confirmity "H"= Confirmity
11 C DETECT I Spindle over-current detection signal input "L" = Over current "H"= Normal
PWM • Output the tracking offset signal to PWM output, then use for auto tracking offset.
12 TRK BAL DRV O
910 µsec period, tri-state control H, L, Z
Handshake signal for data communication with the DVD mechanism control IC
13 SHAKE I/O
This pin is the bilateral data line and each microprocessor control the Input/Output.
RF correction switch signal output "H"= Gain UP CD, CDV-A:Low, CAV inner circuit gain up, others are
14 RF CORRECTION O
High.
15 SQOUT I Command data input from DSP Read out SUBQ
16 SO3/COIN O Command data output to DVP/DSP
17 SCK3/CQCK O DVP/DSP read/write command clock output Read-in at rising edge
18 SLD OUT O PWM • Slider control signal output 5V= FWD, 0V= REV, 2.5V= STOP 910 µsec period, tri-state control
19 SI1 I Data input from the DVD mechanism control IC
20 SO1 O Serial data output to the DVD mechanism control IC
Clock for serial communication with the DVD mechanism control IC
21 SCK I/O
Becomes input mode without communicate with the DVD mechanism control IC
INT • Tracking error zero cross signal input
22 TRK 0 CRS I
Monitor this signal when searching track count in the miss clamp detection
23 SBSY I Subcode block sync. input
LOAD/TILT control output
24 TILT OUT I/O
PWM output 0V : Tray IN / Tilt DOWN, 5V : Tray OUT / Tilt UP, 2.5V : STOP
25 TURN OUT O Turn drive signal output
26 XPBV I Playback vertical sync. signal input of LD/CDV "L"= During vertical sync.
27 CNVSS I Ground for A/D conversion
28 XRESET I Reset signal input "L"= Reset "H"= Release reset Control with the DVD mechanism control IC.
29 XIN I 9MHz clock oscillation input
30 XOUT O 9MHz clock oscillation output
25
DV-505, DVL-909, DV-S9
26
DV-505, DVL-909, DV-S9
• Block Diagram
RFOUT
DEPC
DLPC
DEFI
GND
PHC
BHC
RFO
REF
DEF
EQI
PHI
BHI
PH
BH
TC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
50k
REF Scratch Detection
PDRF– 1 48 BPI1
VCC REF VCC
PH BH PH BH
50k
–
REFI 2 47 VCC
+
–
+
50k
1k
3k
REF
PD1 5 LIM PD 44 BPO2
–
+
3k
26p
PD2 6 LIM PD 43 N/C
CP
40k 60k
40k
–
+
–
PD3 7 LIM PD + 42 BPI2
40k
40k 60k
PD4 8 LIM PD 41 N/C
26p
1k
+ 10p REF
PD5 9 –
80k
15k 60k 40 DLAY1
3k
+
–
–
3k
+ +
PD6 10 –
80k 60k
39 DLAY2
REF 15k 10p
LDD 11 REF 38 MIXO1
APC
VCC
LDS 12 37 VCC
+
–
LDON 13 36 MIXI1
AGOF 14 35 MIXI2
20k
10k
+
–
PH/RR 15 34 GND
–
+
REF
QAGC 16 REF
+ 33 MIXO2
10k
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
QPH/BH
DVD/CD
DPD/TE
CPOF
TEBAL
SGC
TES
TESI
RREC
TE
TLP
CP
TEO
TE–
FE
EFMO
27
DV-505, DVL-909, DV-S9
• Block Diagram
OPIN+
OPIN–
MUTE
GND
GND
VCC
NC
NC
NC
NC
NC
NC
25 24 23 22 21 20 19 18 17 16 15 14
NC NC NC NC NC NC
GND TSD GND
Driver mute VCC
IN Level shift
10K 10K
10K
10K
10K 10K
NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13
OPOUT
NC
NC
BIAS
DRIN'
DRIN
NC
NC
NC
NC
NC
DROUT–
DROUT+
• Pin Function
No. Pin Name Function No. Pin Name Function
1 OPOUT OP amp. output pin 14 N.C.
2 N.C. 15 N.C. Non Connection
Non Connection
3 N.C. 16 N.C.
4 BIAS Bias pin 17 VCC Power supply pin
5 DRIN' Driver gain adjustment pin 18 N.C. Non Connection
6 DRIN Driver gain input pin 19 GND
Sub-strait GND pin
7 N.C. 20 GND
8 N.C. 21 N.C. Non Connection
9 N.C. Non Connection 22 MUTE Mute pin
10 N.C. 23 N.C. Non Connection
11 N.C. 24 OPIN + OP amp. non-inverting input pin
12 DROUT – Driver negative output pin (for input)
25 OPIN – OP amp. inverting input pin
13 DROUT + Driver positive output pin (for input)
28
DV-505, DVL-909, DV-S9
• Block Diagram
FE 35 49 FDO
TE 34 50 TDO
47 SLDO
TILTE 31 8bit Servo 8bit
MPX Processor 48 SPDO
A/D D/A
RF_PH 32 (16×16+32→32) 46 TBAL
RF_BH 33 45 TILTDO
JITT 30 44 AUXO
61 VREF
HFL 63 CMP
26 DRF
Track Counter 55 DVD_CDB
TES 28
1 PP5/SYNC
PP7/EVNT 58 Event Counter
LCD Driver 56 LCDCNTL
PP6/FG 57 FG Counter
SLCIST1,2 36,37
EFMIN 41 25 V_PB
SLC
SLCO1,2 38,39 CLV 24 FAST
EFMOUT 3
79 WRQ
PCKIST1,2 89,90
76 SQOUT
CDFR 93 Frame Synchronous Sub Code
CD-PLL 77 CQCKB
Detection, Protection, Decode
78 RWC
DVDFR 92 Insertion EFM CRC
DVD-PLL Demodulation 19 EMPH
PD01-3 85-87
14 PW
JV 94
12 SBCK
LEFM 2
20 SBSY
PCK 95
13 SFSY
VRPFR 81 For De-Interleave
VCOC 82 Error Detect 16k SRAM
Clock Correction
VPDO 83 11 FSX
Generator C1-Twofold,
XIN 16
C2-Fourfold 4 C2F
XOUT 17 22 EFLG
XTALOUT 10
CSB 60
DOUT 21 DOUT
WRB 62 Supplement/Mute
Command D Attenuate
RDB 61
Interface Deemphasis Filter 7 LRSY
P0-7 65-72
Serial Out 6 ROMCK
BUSYB 75
5 ROMXA
LASER 54
29
DV-505, DVL-909, DV-S9
• Pin Function
No. Pin Name I/O Function
1 PP5/SYNC I/O General-purpose port input/output / DVD sync. signal input
2 LEFM O Output the state that cut and out a signal which was binary-stated value EFM/EFM + with PCK.
3 EFMOUT O Output the state that was binary-stated value EFM/EFM + .
4 C2F O C2 flag output
5 ROMXA O ROMXA data output
6 ROMCK O Shift clock output for ROMXA data output
7 LRSY O L/R clock output for ROMXA data output
8 DVDD2 − 5V power supply
9 VSS − GND
10 XTALOUT O External system clock output
11 FSX O CD 1 frame sync. signal output
12 SBCK I Subcode reading out clock input
13 SFSY O Frame sync. signal output of subcode
14 PW O Subcode P, Q, R, S, T, U, V and W output
15 VSS − GND for oscillation circuit
16 XIN I Connect a crystal resonator (16.9344MHz)
17 XOUT O Connect a crystal resonator
18 DVDD1 − 3.3V power supply of the oscillation circuit
19 EMPH O Monitor the deemphasis
20 SBSY O Sync. signal output of the subcode block
21 DOUT O Output for the digital audio I/F
22 EFLG O Error correction state monitor of the error correction C1 and C2
23 FSEQ O Detection monitor of the CD/DVD frame sync. signal
24 FAST O Playback speed monitor
25 V_PB O Monitor output of the rough servo/CLV control
26 DRF O In focus monitor
27 TEST3 I Test input 3
28 TES I Tracking error signal input
29 TEST2 I Test input 2
30 JITT I Jitter quantity detecting signal input of EFM/EFM + PLL
31 TILTE I Tilt error signal input
32 RF_PH I RF peak hold signal input
33 RF_BH I RF bottom hold signal input
34 TE I Tracking error signal input
35 FE I Focus error signal input
36 SLCIST1 − Current setting pin 1 of the constant current charge pump for SLC
37 SLCIST2 − Current setting pin 2 of the constant current charge pump for SLC
38 SLCO1 − Control output 1 for SLC
39 SLCO2 − Control output 2 for SLC
40 TEST1 I Test input 1
41 EFMIN I EFM/EFM + input
42 AVDD − 5V power supply of A/D and D/A for servo
43 AVSS − GND of A/D and D/A for servo
44 AUXO O DA auxiliary output
45 TILTDO O Tilt control signal output
46 TBAL O Tracking balance control signal output
47 SLDO O Sled control signal output
48 SPDO O Spindle control signal output
49 FDO O Focus control signal output
50 TDO O Tracking control signal output
30
DV-505, DVL-909, DV-S9
31
DV-505, DVL-909, DV-S9
• Pin Function
No. Pin Name I/O Function No. Pin Name I/O Function
1 LODDRV I/O Loading motor drive output 33 XDSPRST − Reset pulse for servo DSP "L"
Address strobe of multiplexed address/data
2 DVD/XCD O Clock switch H : DVD , L : CD 34 ASTB O
bus "H"
3 AGOFF O Turn AGC of RF IC to OFF for "H" 35 XRST I CPU reset input "L"
Count data input of error rate Subcode frame sync. input
4 EFLG I 36 SBSY INT
Measureable by using timer 1 and 2. (H : S0+S1 period)
Error rate count area input (EFM frame sync.) Communication handshake of CLD
5 FS X I 37 SHAKE INT
H : C1 , L : C2 mechanism controller "L" (DVL-909 only)
6 P35/PCL − Not used (pull down) 38 XABUSY INT DSP auto sequence busy input "L"
High impedance (input) at DEFECT ON
7 XTOFF I/O 39 XIRQ2 INT LSI-11 interrupt input "L"
"L" output at DEFECT OFF
8 XCBUSY I DVD command reception is possible "L" 40 VDD − Power supply pin
9 VSS − GND 41 X2 −
Connect a ceramic resonator
10 MAD0 42 X1 −
11 MAD1 43 IC (Vpp) − GND
12 MAD2 44 XT2 − Not used
Park position detection of compatible DVD
13 MAD3 45 DVDPPK I
I/O External address / data bus pickup "L" (DVL-909 only)
14 MAD4 46 AVss − GND
15 MAD5 47 LODPOS I Loading and clamp position SW input
16 MAD6 48 SLDPOS I Slider position SW input
17 MAD7 49 DORPOS I Panel position SW input (DV-S9 only)
Acutuator over-current detection input (former
18 MA8 50 XCURDET I
TRDLMT) "L" Servo OFF for 300 ms.
Panel and loading switch of PWM output
19 MA9 51 DR/XLD O
Panel : H , loading : L (DV-S9 only)
20 MA10 O External address bus 52 MON O Spindle motor ON output "H"
21 MA11 53 XCD2X O Not used
22 MA12 54 OEICG O "H" : OEIC gain up to 6dB
23 MA13 55 AVDD − Power supply pin
24 VSS − GND 56 AVREF − Reference power supply pin
25 MA14 57 P_ERR O Not used
O External address bus
26 MA15 58 P21/SO1 − Not used (pull down)
27 DRF I (FOK) Focus OK input 59 P22/XSK1 − Not used (pull down)
(LOCK) EFM servo lock signal
28 V_PB I 60 XCSB O DSP parallel command setting output "L"
"H"/"L"= rough servo / phase servo
29 P62 − Not used (pull down) 61 CLD O CLD circuit block switch (DVL-909 only)
Inputs serial communication output of CLD
30 WRQ I Readable flag of subcode Q 62 LDSO I
mechanism controller (DVL-909 only)
Outputs serial communication input of CLD
31 XRD O CPU read pulse "L" 63 LDSI O
mechanism controller (DVL-909 only)
Inputs serial communication clock output of
32 XWR O CPU write pulse "L" 64 LDSCK I
CLD mechanism controller (DVL-909 only)
32
DV-505, DVL-909, DV-S9
• Block Diagram
A0 10
A1 9
A2 8
A3 7 Memory-Cell
9 Line 512 Array
A4 6 Decoder
Address Buffer
A5 5 512×64×8
A6 4
A7 3
A8 25
A9 24
64×8
A10 21
A11 23
A12 2 6 64
Row Row Gate
A13 26 Decoder
A14 1
CS
CS 20 Control 8
Logic
OE 22 OE, WE
Control I/O Buffer
WE 27 Logic
14 18 11 12 13 15 16 17 18 19
Vss
VDD
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
• Pin Function
No. Pin Name Function No. Pin Name Function
1 A14 15 I/O4
2 A12 16 I/O5
3 A7 17 I/O6 Data input/output
4 A6 18 I/O7
5 A5 19 I/O8
Address input
6 A4 20 CS Chip select
7 A3 21 A10 Address input
8 A2 22 OE Output enable
9 A1 23 A11
10 A0 24 A9
Address input
11 I/O1 25 A8
12 I/O2 Data input/output 26 A13
13 I/O3 27 WE Write enable
14 VSS GND (0V) 28 VDD Power supply (2.7 to 5.5V)
33
DV-505, DVL-909, DV-S9
• Block Diagram
RY/BY DQ0-DQ15
15-22,
1
24-31
RY/BY RY/BY
BUFFER
ERASE INPUT/OUTPUT
CIRCUIT BUFFER
WE 43
BYTE 33
CONTROL
RESET 44 CIRCUIT
WRITE
CIRCUIT
CE 12 CHIP ENABLE STB
OUTPUT ENABLE DATA LATCH
OE 14 CIRCUIT
Y DECODER Y GATE
STB ADDRESS LATCH
LOW VCC WRITE/ERASE
DET. CIRCUIT PULSE TIMER 8,388,608
CELL
2-11, X DECODER
A0-A18 34-42 MATRIX
A-1 31
• Pin Function
No. Pin Name Function No. Pin Name Function
1 RY/BY Ready / Busy output 23 VCC Power supply (+5.0V ± 10% or ± 5%)
2 A18 24 DQ4
3 A17 25 DQ12
4 A7 26 DQ5
5 A6 27 DQ13 Data input / output
6 A5 28 DQ6
Address input
7 A4 29 DQ14
8 A3 30 DQ7
9 A2 31 DQ15/A-1 Data input/output / address input
10 A1 32 VSS Ground
11 A0 33 BYTE Switch the 8 bit and 16 bit modes
12 CE Chip enable 34 A16
13 VSS Ground 35 A15
14 OE Output enable 36 A14
15 DQ0 37 A13
16 DQ8 38 A12 Address input
17 DQ1 39 A11
18 DQ9 40 A10
Data input/output
19 DQ2 41 A9
20 DQ10 42 A8
21 DQ3 43 WE Write enable
22 DQ11 44 RESET Hardware reset
34
DV-505, DVL-909, DV-S9
• Block Diagram
PA13/IRQ1/DREQ0/TCLKB
PA12/IRQ0/DACK0/TCLKA
PA9/AH/IRQOUT/ADTRG
PA15/IRQ3/DREQ1
PA11/DPH/TIOCB1
PA14/IRQ2/DACK1
PA1/CS5/RA5/RAS
PA10/DPL/TIOCA1
PA2/CS6/TIOCB0
PA0/CS4/TIOCA0
PA5/WRH(LBS)
PA3/CS7/WAIT
PA4/WRL(WR)
PA8/BREQ
CS1/CASH
PA7/BACK
CS3/CASL
PA6/RD
CS2
CS0
A21
A20
A19
A18
A17
A16
69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 51 50 49 48 47 46 45 44 42 41
PORT A ADDRESS
RES 79 39 A15
WDTOVF 78 38 A14
MD2 82 37 A13
MD1 81 36 A12
MD0 80 35 A11
64k PROM / MASK ROM 4kB RAM1
NMI 76 34 A10
33 A9
OSCILLATOR
CK 71 32 A8
ADDRESS
EXTAL 73 30 A7
XTAL 74 29 A6
28 A5
Vpp 77 DIRECT 27 A4
Vcc 15 CPU MEMORY
ACCESS 26 A3
Vcc 43 CONTROLLER 25 A2
Vcc 70 24 A1
Vcc 75 23 A0(HBS)
INTERRUPT USER BREAK BUS STATE
Vcc 83 CONTROLLER CONTROLLER CONTROLLER
Vcc 84 21 AD15
Vcc 99 20 AD14
Vss 3 19 AD13
Vss 12 SERIAL 18 AD12
16BIT
COMMUNICATION
Vss 22 INTERFACE
INTEGRATED 17 AD11
TIMER PULSE UNIT
Vss 31 (×2CHANNEL)
16 AD10
DATA/ADDRESS
Vss 40 14 AD9
Vss 52 PROGRAMABLE
TIMING A/D WATCHDOG 13 AD8
Vss 61 PATTERN CONVERTER TIMER
11 AD7
CONTROLLER
Vss 72 10 AD6
Vss 96 9 AD5
Vss 106 8 AD4
7 AD3
AVref 86 6 AD2
AVcc 85 5 AD1
PORT C PORT B
AVss 91 4 AD0
95 94 93 92 90 89 88 87 2 1 112 111 110 109 108 107 105 104 103 102 101 100 98 97
PC7/AN7
PC6/AN6
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
PB15/TP15/IRQ7
PB14/TP14/IREQ6
PB13/TP13/IREQ5/SCK1
PB12/TP12/IREQ4/SCK0
PB11/TP11/TxD1
PB10/TP10/RxD1
PB9/TP9/TxD0
PB8/TP8/RxD0
PB7/TP7/TOCXB4/TCLKC
PB6/TP6/TOCXA4/TCLKC
PB5/TP5/TIOCB4
PB4/TP4/TIOCA4
PB3/TP3/TIOCB3
PB2/TP2/TIOCA3
PB1/TP1/TIOCB2
PB0/TP0/TIOCA2
35
DV-505, DVL-909, DV-S9
• Pin Function
No. Pin Name I/O Function
1 PB14/TP14/IRQ6
I/O 16 bit input/output (port B) / Timing pattern output / Interruption request
2 PB15/TP15/IRQ7
3 VSS I Ground
4 AD0
5 AD1
6 AD2
7 AD3
I/O 16 bit bilateral data bus
8 AD4
9 AD5
10 AD6
11 AD7
12 VSS I Ground
13 AD8
I/O 16 bit bilateral data bus
14 AD9
15 VCC I Power supply
16 AD10
17 AD11
18 AD12
I/O 16 bit bilateral data bus
19 AD13
20 AD14
21 AD15
22 VSS I Ground
23 A0 (HBS) O Address bus output (upper byte strobe signal)
24 A1
25 A2
26 A3
27 A4 O Address bus output
28 A5
29 A6
30 A7
31 VSS I Ground
32 A8
33 A9
34 A10
35 A11
O Address bus output
36 A12
37 A13
38 A14
39 A15
40 VSS I Ground
41 A16
O Address bus output
42 A17
43 VCC I Power supply
36
DV-505, DVL-909, DV-S9
37
DV-505, DVL-909, DV-S9
102 PB4/TP4/TIOCA4 16 bit input/output (port B) / Timing pattern output / ITU input capture input/ITU output compare
I/O
103 PB5/TP5/TIOCB4 output (channel 4)
104 PB6/TP6/TOCXA4/TCLKC 16 bit input/output (port B) / Timing pattern output / ITU output compare output (channel 4) /
I/O
105 PB7/TP7/TOCXB4/TCLKD ITU timer clock input
38
DV-505, DVL-909, DV-S9
• Block Diagram
Exclusive
Parallel port 16Mbit
CPU
Input Signal SDRAM
Internal
Bus
MIX
Starting
Reset Control Signal
Picture
Signal Block Block
Reset Signal
Clock
Generation
Block
39
DV-505, DVL-909, DV-S9
• Pin Function
No. Pin Name I/O Function No. Pin Name I/O Function
1 CLKSEL I ON/OFF signal of PLL ("H" : ON, "L" : OFF) 27 VDD − 3.3V power supply
Digital component signal output (MSB)
2 DIGCPN7 O 28 DIGCOMP4
Digital Y signal output (9-bit) (MSB)
3 VSS − GND 29 DIGCOMP3 Digital composite signal output
Digital C signal output
4 DIGCPN6 30 DIGCOMP2 O
5 DIGCPN5 31 DIGCOMP1
Digital composite signal output (LSB)
6 DIGCPN4 Digital component signal output 32 DIGCOMP0
O Digital C signal output (LSB)
Digital Y signal output (9-bit)
7 DIGCPN3 33 DACK O 27 MHz clock output
8 DIGCPN2 34 N.C. − Non connection
9 DIGCPN1 35 VSSA3 − GND (D/A converter)
10 VDD − 3.3V power supply 36 ANAC O Analog color (C) output signal
Digital component signal output (LSB) 3.3V power supply (for built-in D/A converter
11 DIGCPN0 O 37 VDDA3 −
Digital Y signal output (9-bit) (LSB) only)
Cb and Cr discrimination signal at the digital
12 RBSEL O component signal output. 38 VSSA2 − GND (D/A converter)
LSB at the digital Y signal output.
13 XHS O Horizontal sync. output signal 39 ANAY O Analog luminance (Y) output signal
3.3V power supply (for built-in D/A converter
14 XVS O Vertical sync. output signal 40 VDDA2 −
only)
15 VSS − GND 41 VREF I Reference voltage for D/A converter
16 XRESET I LSI reset signal 42 VRO O Internal current setting pin of D/A converter
17 XLDCSYNC I External sync. signal input (LD mode) 43 N.C. − Non connection
KEY signal for LD and OSD overlay
18 KEY O 44 VSSA1 − GND (D/A converter)
(LD mode)
Phase comparison result output signal of
19 PD O 45 ANACOMP O Analog composite output signal
horizontal sync. (LD mode)
Field discrimination signal at the digital signal 3.3V power supply (for built-in D/A converter
20 VFLD O 46 VDDA1 −
output H : even field L : odd field only)
Digital composite signal output (MSB)
21 DIGCOMP9 47 BF O Burst flag signal
Digital C signal output (MSB)
22 DIGCOMP8 48 XBLK O H/V composite blanking signal
O
23 DIGCOMP7 Digital composite signal output 49 N.C. − Non connection
24 DIGCOMP6 Digital C signal output 50 VSS − GND
25 DIGCOMP5 51 TEST0 − Normally, set to "open".
26 VSS − GND 52 TEST1 − "L" status normally
40
DV-505, DVL-909, DV-S9
No. Pin Name I/O Function No. Pin Name I/O Function
53 DAIIN I Digital data input of external input (SPDIF) 92 HADRS10 I CPU address bus signal (MSB)
Audio data input of external input
54 CDDATA I 93 HADRS9
(correspond to CD)
Data channel clock input of external input
55 CDLR I 94 HADRS8 I CPU address bus signal
(correspond to CD)
Data clock input of external input
56 CDBCK I 95 HADRS7
(correspond to CD)
57 AODATA3 96 VSS − GND
58 AODATA2 O Audio decode data 97 VDD − 3.3V power supply
59 AODATA1 98 HADRS6
60 VSS − GND 99 HADRS5
CPU address bus signal
61 VDD − 3.3V power supply 100 HADRS4 I
62 AODATA0 O Audio decode data 101 HADRS3
Digital audio interface output
63 AOPCM O 102 HADRS2 CPU address bus signal (LSB)
(compression data)
64 AODAI O Digital audio interface output (decode data) 103 HDATA15 CPU data bus signal (MSB)
65 LRCK O Data channel clock for D/A and digital filter 104 HDATA14
I/O
66 AOMCK O Master clock for D/A and digital filter 105 HDATA13 CPU data bus signal
67 BCK O Bit clock for D/A and digital filter 106 HDATA12
68 ICED1 107 VSS − GND
69 ICED0 Pin for emulator 108 HDATA11
−
70 ICEBRK Normally, set to "open". 109 HDATA10
71 XDSPRST 110 HDATA9
I/O CPU data bus signal
72 VSS − GND 111 HDATA8
73 N.C. − Non connection 112 HDATA7
74 TEST2 113 HDATA6
75 TEST3 114 VDD − 3.3V power supply
− Normally, set to "open".
76 TEST4 115 HDATA5
77 TEST5 116 HDATA4
I/O CPU data bus signal
78 SD7 I Parallel data input 117 HDATA3
79 VDD − 3.3V power supply 118 HDATA2
80 SD6 119 VSS − GND
81 SD5 120 HDATA1 CPU data bus signal
I/O
82 SD4 I Parallel data input 121 HDATA0 CPU data bus signal (LSB)
Bus width selection signal
83 SD3 122 BUSSEL I
(0 : 8-bit bus, 1 : 16-bit bus)
84 SD2 123 XOSDACK I OSD data acknowledge signal
85 VSS − GND 124 XOSDREQ O OSD data request signal
86 SD1 125 HCPUSEL1 CPU selection signal (00 :SPARC,
I Parallel data input I
87 SD0 126 HCPUSEL0 01 :86 system, 10 :68 system, 11 :Reserve)
41
DV-505, DVL-909, DV-S9
No. Pin Name I/O Function No. Pin Name I/O Function
131 VDD − 3.3V power supply 170 XMDRCAS O CAS signal for SDRAM
Input mask / output enable signal for
132 XINT0 O Interrupt request signal to CPU 171 XMDRDQM1 O
SDRAM
SPARC, 68 system : Ready signal to CPU
133 XEXTRDY O 86 system : Acknowledge (ACK) signal to 172 VSS − GND
CPU
134 HRW I CPU read / write signal 173 XMDRWE O Write enable signal for SDRAM
Input mask / output enable signal for
135 HCLKIN I Host clock input 174 XMDRDQM0 O
SDRAM
136 XHCS I LSI chip select signal 175 MDRDAT8 I/O Data bus signal for SDRAM
SPARC, 68 system : CPU address strobe
137 XHAS I 176 VSS − GND
86 system : CPU address status
138 XHBE3 177 MDRDAT7
139 XHBE2 178 MDRDAT9
I CPU byte enable signal
140 XHBE1 179 MDRDAT6 I/O Data bus signal for SDRAM
141 XHBE0 180 MDRDAT10
142 VSS − GND 181 MDRDAT5
143 MDRADR4 182 VSS − GND
144 MDRADR3 183 VDD − 3.3V power supply
O Address signal for SDRAM
145 MDRADR5 184 MDRDAT11
146 MDRADR2 185 MDRDAT4
147 VDD − 3.3V power supply 186 MDRDAT12 I/O Data bus signal for SDRAM
148 VSS − GND 187 MDRDAT3
149 MDRADR6 188 MDRDAT13
150 MDRADR1 Address signal for SDRAM 189 VSS − GND
151 MDRADR7 O 190 MDRDAT2
152 MDRADR0 Address signal for SDRAM (LSB) 191 MDRDAT14 Data bus signal for SDRAM
I/O
153 MDRADR8 Address signal for SDRAM 192 MDRDAT1
154 VSS − GND 193 MDRDAT15 Data bus signal for SDRAM (MSB)
155 TEST6 194 MDRDAT0 I/O Data bus signal for SDRAM (LSB)
156 TEST7 195 VSS − GND
− "L" status normally
157 TEST8 196 N.C. − Non connection
158 TEST9 197 ICK27M I System clock input
159 MDRADR10 198 VSS − GND
Address signal for SDRAM
160 MDRADR9 O 199 OCK27M O System clock output
161 MDRADR11 Address signal for SDRAM (MSB) 200 VSSA(VCO) − GND (for VCO only)
162 XMDRCS O Chip select signal for SDRAM 201 VDDA(VCO) − 3.3V power supply (for VCO only)
163 MDRCKE O Clock enable signal for SDRAM 202 ILPF O PLL block inverter output for audio
164 VSS − GND 203 MLPF I PLL block inverter input for audio
165 VDD − 3.3V power supply 204 OLPF O Phase detector output for audio
166 XMDRRAS O RAS signal for SDRAM 205 OVCO I VCO input for audio clock
167 MDRCLK O Clock output signal for SDRAM 206 VSS − GND
168 VSS − GND 207 XPLLRST I PLL section reset signal
169 MDRCLKIN I Clock input signal for SDRAM 208 XSYNCRST I SYNC reset signal
42
DV-505, DVL-909, DV-S9
• Block Diagram
CLK 35 Clock To
Bank 1
Buffer Blocks
CKE 34
RAS
Bank 0
CS 18
Control
RAS 17 Command Signal CAS
CAS 16 Decoder Latch
WE
WE 15
DRAM Core
Mode
21-24, 27-32, 20, 19 Address (2,048×256×16)
Register
Buffer/
A0-A11, Register
AP &
Bank Row Address
Select
DQML 14 Column
Address Column Address
DQMU 36
Counter I/O
40,42,43,45,46,48,49
2,3,5,6,8,9,11,12,39,
I/O Data
Buffer/
DQ0-DQ15 Register
1,7,13,25,38,44 4,10,26,41,47,50
VCC/VCCQ VSS/VSSQ
• Pin Function
No. Pin Name Function No. Pin Name Function
1 VCC Power supply (+ 3.3V) 26 VSS Ground
2 DQ0 27 A4
Data input/output
3 DQ1 28 A5
4 VSSQ Ground 29 A6 Address input
5 DQ2 30 A7 Row : A0 to A10 , Column : A0 to A7
Data input/output
6 DQ3 31 A8
7 VCCQ Power supply (+ 3.3V) 32 A9
8 DQ4 33 DU Don't use (use for open)
Data input/output
9 DQ5 34 CKE Clock enable
10 VSSQ Ground 35 CLK Clock input
11 DQ6 36 DQMU Input mask / Output enable
Data input/output
12 DQ7 37 DU Don't use (use for open)
13 VCCQ Power supply (+ 3.3V) 38 VCCQ Power supply (+ 3.3V)
14 DQML Input mask / Output enable 39 DQ8
Data input/output
15 WE Write enable 40 DQ9
16 CAS Column address strobe 41 VSSQ Ground
17 RAS Row address strobe 42 DQ10
Data input/output
18 CS Chip select 43 DQ11
19 A11 (BA) Bank select 44 VCCQ Power supply (+ 3.3V)
Address input
20 A10/AP Row : A0 to A10 , Column : A0 to A7 45 DQ12
/ Auto pre-charge enable Data input/output
21 A0 46 DQ13
22 A1 Address input 47 VSSQ Ground
23 A2 Row : A0 to A10 , Column : A0 to A7 48 DQ14
Data input/output
24 A3 49 DQ15
25 VCC Power supply (+ 3.3V) 50 VSS Ground
43
DV-505, DVL-909, DV-S9
• Block Diagram
XTALIN 3 Refference
Oscillator PLL1 EPROM- 1 CLKA
XTALOUT 4
Configurable
PLL2 Multiplexer 5 CLKB
GND 2 and
PLL3 Drive Logic 6 CLKC
VDD 7
OE/PD/FS/SUSPEND 8
• Pin Function
No. Pin Name Function
1 CLKA Configurable clock output
2 GND Ground
3 XTALIN Reference crystal input or external reference clock input
4 XTALOUT Reference crystal feedback
5 CLKB Configurable clock output
6 CLKC Configurable clock output
7 VDD Voltage supply
Output control pin
8 OE/PD/FS/SUSPEND Either active-High output enable, active-Low power down, CLKA frequency select, or active-Low suspend
input
44
DV-505, DVL-909, DV-S9
• Block Diagram
TPS16
TPS0
VDDR
VSSR
TES0
TES2
VDD
RST
VSS
1–3,6–11,
45 42–44 13 12 4,31 5,14,34,52
53–60
Interface bus
Data bus
Work register 35 CKSL
bus
36 PLOFF
24b 16b 32 XI
Temporary 33 XO
Register
Multiply 30 SYNC
Program and add Timing
Serial Data 28,29 ELRI1,ELRI0
Counter Culculator Generation 25,26 EBCI1,EBCI0
Logical Input/Output
24b×16b+43b Circuit
Program Arithmetic Circuit 27 ELRO
ROM Unit(LU) Work Interface Input (2 port) 24 EBCO
1024w×32b Register Circuit Output (3 port)
20 LR
21 WCK
VCO Oscillation 22 FS32
Circuit
23 FS64
46 47 50 48 49 51 18,19 17–15 41 37 40 39 38
CS
IFCD
IFCK
IFDI
IFDO
ACK
SDI1
SDI0
SDO0
SDO2
VDDA
PD
AMPI
AMPO
VSSA
• Pin Function
No. Pin Name I/O Function
1 TP8
Test data output pin
2 TP7 O
Normally, use with open.
3 TP6
4 VDD − Power supply pin
5 VSS − Ground pin
6 TP5
7 TP4
8 TP3 Test data output pin
O
9 TP2 Normally, use with open.
10 TP1
11 TP0
45
DV-505, DVL-909, DV-S9
46
DV-505, DVL-909, DV-S9
5. FL INFORMATION
VAW1046 (FLKB ASSY : V101)(DV-505 and DVL-909 only)
• FL DISPLAY
1 34
P4
G1
96kHz GUI ANGLE LAST MEMO CONDITION DOLBY P9
P1 TITLE PB CHP / TRK P6 REMAIN TOTAL DIGITAL P7 P8
P6 P5
P3 P10
P14
• PIN ASSIGNMENT
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Assignment F1 F1 NP P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2
Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Assignment P1 G11 G10 G9 G8 NL NL G7 G6 G5 G4 G3 G2 G1 NP F2 F2
47