Drive for better vision

Source/Gate driver introduce

November, 2008

Himax Technologies, Inc.

奇景光電股份有限公司
 Outline

l Function of gate driver in TFT LCD

l Gate driver
l Source driver

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 LCD Display Principle

l Normally white 形式
l 利用电压的改变,控制透光率

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 Architecture

l 6 bit data driver

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 TFT Module Block Diagram

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 TFT LCD Equivalent Circuit

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 Timing Chart of TFT-LCD

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 Source Input Data and Display colors

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 Gate driver

l Block diagram
l Power supply
l Power on/off sequence
l OE and XAO function
l Waveform of operation
l Case study

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 Block diagram

CPV => Vertical Clock Pulse

L/R => Shift direction control
STV => Vertical start pulse
OE => Output Enable control
XAO => Output All-On control
MODE=>Channel number
select

VGH => Gate High voltage

VDD => Logic power
VSS => Logic ground
VGL(VEE) => Gate Low
voltage

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 Block diagram

l Simply considered as HV logic

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 Bi-directional Shifter Register

l 4-bit bi-direction shift register

v Data can be shifted register left or right
v RIGHT/LEFT’ control line : gating logic
v RIGHT/LEFT’ = 1 : G5,G6,G7,G8 disable

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 Level shifter

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 Level shift

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 Output buffer

l 由于LS的驱动能力可能不够,因此需要一个output buffer来增加它的驱
动能力.

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 Power supply for gate driver

l VGH: Power supply for G/D output high, up to 30V

l VGL: power supply for G/D output low, low to -20V
l VDD: Digital power supply, can be low to 1.8V
l VSS: Digital ground 0V
l VEE: LCD driver negative power supply
eg. HX8636-A VGL-VEE=0~6V

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 Power ON/OFF sequence

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 OE and XAO function

l OE function

l XAO function
v 當關機(power down)時，XAO訊號(low active)將TFT上所有Gate打開，
使液晶上儲存的電壓快速中和至Vcom位準，如此可避免殘影現象(image
sticking)發生。
v 一般電路上以Reset IC來供給Gate driver IC所需要的XAO訊號。
v 若不使用XAO function，需將該Gate driver的XAO pin pull high至VDD。

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 L/R control indication

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 Waveform of operation

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 Waveform of operation

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 Gate Driver Timing

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 Shift register

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 LS

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 Output buffer

l HX8668-C00LPD300 week line issue

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 mode

l Abnormal display issue

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 Source driver

l Source driver introduction

l Case study

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 Source IC block diagram
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EIOn (STH) à Start pulse
input/output
DIR(L/R) à Shift direction control
POL2n(INV) àdata inversion control
POLà Output polarity control
TP1(STB)à Latch input
Vr1~10àgamma voltage
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 RSDS Interface

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 TTL input

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 RSDS input

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 POL 1/2 line control
STV
Line 1
Line 2
POL
Line 3
Line 4 TP1
+ - + - + - + - + - +
POL 1 line inversion

STV
Line 1
Line 2
POL
Line 3
Line 4 TP1
+ - - + + - - + + - -
POL 1+2 line inversion

STV
Line 1
Line 2
Line 3
POL
Line 4 TP1
POL 2 line inversion + + - - + + - - + + -

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 Polarity method

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 Level shifter

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 DAC

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 3-bit DAC

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 Source Driver Output Timing

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 Direction Control

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 Two Channel Block Diagram

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 Shift register

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 latch-1

l Bit line:CH172

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 Latch 2

l Bit line:CH413,CH414

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 LS

l Bit line:CH55,CH56

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 DAC

l Bit line:CH235,CH236

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 OP

l S line:CH191,CH192

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 Output MUX

l S line:CH407,CH408

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 Gamma

l Band defect:CH1~CH90

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Drive for better vision