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Mercury XU8-R2 IO NetLength
Mercury XU8-R2 IO NetLength
Revision: R2
PCB Revision: B
Date: 6/5/2019
*1) Signals are routed via level shifter to FPGA. Signal length includes trace from module connector
to level shifter, and from level shifter to FPGA.
*2) Signal is routed via series resitor to FPGA. Signal length includes trace from module connector
to resistor, resistor length and resistor to FPGA.
Disclaimers
All pinout and pin information is provided as-is without assurance of correctness or
completeness.
All information
Please verify all is subject
data with to change atuser
Enclustra's anymanuals
time without
FPGAnotice.
and other components vendor's
documentation.
Enclustra recommends checking the module's and the FPGA and other components errata
sheets.
Comment
*1)
*1)
*1)
*1)
*2)
Module: ME-XU8
Revision: R1
PCB Revision: A
Date: 11/9/2018
*1) Signals are routed via level shifter to FPGA. Signal length includes trace from module connector
to level shifter, and from level shifter to FPGA.
*2) Signal is routed via series resitor to FPGA. Signal length includes trace from module connector
to resistor, resistor length and resistor to FPGA.
Disclaimers
All pinout and pin information is provided as-is without assurance of correctness or
completeness.
All information
Please verify all is subject
data with to change atuser
Enclustra's anymanuals
time without
FPGAnotice.
and other components vendor's
documentation.
Enclustra recommends checking the module's and the FPGA and other components errata
sheets.
Comment
*1)
*1)
*1)
*1)
*2)