Interrupt Vectors

interrupt vectors :
The interrupt vectors and vector table are crucial to the understanding of hardware and software
interrupts. Interrupt vectors are addresses that inform the interrupt handler as to where to find the ISR (interrupt
service routine, also called interrupt service procedure). All interrupts are assigned a number from 0 to 255, with
each of these interrupts being associated with a specific interrupt vector.
The interrupt vector table is normally located in the first 1024 bytes of memory at addresses 000000H–0003FFH. It
contains 256 different interrupt vectors. Each vector is 4 bytes long and contains the starting address of the ISR. This
starting address consists of the segment and offset of the ISR.  Remember that in order to install an interrupt vector
(sometimes called a hook), the assembler must address absolute memory.

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interrupt vector table:
An "interrupt vector table" (IVT) is a data structure that associates a list of interrupt handlers
with a list of interrupt requests in a table of interrupt vectors. Each entry of the interrupt vector table, called an
interrupt vector, is the address of an interrupt handler. While the concept is common across processor architectures,
IVTs may be implemented in architecture-specific fashions. For example, a dispatch table is one method of
implementing an interrupt vector table.

Handling methods:

An interrupt vector table is used in the three most popular methods of finding the starting
address of the interrupt service routine:

Predefined:

The "predefined" method loads the program counter (PC) directly with the address of some entry inside the interrupt
vector table. The jump table itself contains executable code. While in principle an extremely short interrupt handler
could be stored entirely inside the interrupt vector table, in practice the code at each entry is a single jump
instruction that jumps to the full interrupt service routine (ISR) for that interrupt. The Intel 8080[3], Atmel AVR[4]
[5] and all 8051 and Microchip microcontrollers[6] use the predefined approach.

Fetch:

The "fetch" method loads the PC indirectly, using the address of some entry inside the interrupt vector table to pull
an address out of that table, and then loading the PC with that address.[6] Each and every entry of the IVT is the
address of an interrupt service routine. All Motorola/Freescale microcontrollers use the fetch method.

Interrupt acknowledge

For the "interrupt acknowledge" method, the external device gives the CPU an interrupt handler number. The
interrupt acknowledge method is used by the Intel Pentium and many older microprocessors.

When the CPU is affected by an interrupt, it looks up the interrupt handler in the interrupt vector table, and transfers
control to it.

Difference Between x86 and ARM Architecture in Interrupt Vector

 There are some processors, which use ISR_VECTADDR directly as ISR address and processor fetches
from there the ISR instruction, for example, ARM or 8051 2.
 There are some processors, which use ISR_VECTADDR indirectly as ISR address and processor fetches
the ISR address from the bytes saved at the ISR_VECTADDR, for example, 80x86
 The ARM architecture started out as a RISC architecture. The intended usage was in embedded systems -
unlike x86s which were designed for full fledged PCs / servers. Thus, ARM exception handling
mechanisms are designed keeping in mind their use in embedded devices.
  The Speed is of essence in embedded devices, as your cycles / sec are more limited when you run an ARM
at sub-GHz frequencies than in a x86 processor running at a few GHz. This means that an ARM processor
does not want to go through the hassle of saving and restoring the entire register file each time we take an
exception and do a return from the handler
 . To avoid doing this, the ARM architecture (or atleast the current generation ones) thought it prudent to
provide a lot of exceptions with their own modes. Each mode gets its own register file (either partially or
fully). This saves the overload of saving registers, which number somewhere between 16 and 32 on to the
stack each time you take an exception, and then restoring them each time you return from one.

x86 Processor Mechanism:

 80x86 Processor Mechanism: A software interrupt instruction, for example, Int n explicitly also defines
type of interrupt and the type defines the ISR_VECTADDR
 Type value multiplied by 0x00004 gives the vectoring address from where the processor fetches the four
bytes to compute the ISR address for executing the ISR
 x86 interrupt system is tripartite in the sense of it involves 3 parts to work conjointly:

 Programmable Interrupt Controller (PIC) must be configured to receive interrupt requests (IRQs) from
devices and send them to CPU.
 CPU must be configured to receive IRQs from PIC and invoke correct interrupt handler, via gate described
in an Interrupt Descriptor Table (IDT).
 Operating system kernel must provide Interrupt Service Routines (ISRs) to handle interrupts and be ready
to be preempted by an interrupt. It also must configure both PIC and CPU to enable interrupts.

ARM processor Mechanism :.

 In a certain processor architecture, for example, ARM, the software instruction SWI does not explicitly
defines the type of interrupt for generating different vector address and instead there is a common
ISR_VECTADDR for each exception or signal or trap generated using SWI instruction
 ISR that executes after vectoring has to find out which exception caused the processor to interrupt and
program diversion. Such a mechanism in processor architecture results in provisioning for the unlimited
umber of exception handling routines in the system with common an interrupt vector address. ARM
processor provisions for such a mechanism