www.advenergymat.

de
www.MaterialsViews.com

Large-Area Rolled-Up Nanomembrane Capacitor Arrays for

FULL PAPER
Electrostatic Energy Storage
Ravikant Sharma, Carlos César Bof Bufon,* Daniel Grimm,* Robert Sommer,
Arndt Wollatz, Jörg Schadewald, Dominic J. Thurmer, Pablo F. Siles, Martin Bauer,
and Oliver G. Schmidt

selected passive elements such as induc-

The fabrication, characterization, and optimization of large area rolled-up tors or capacitors.[1,2] In the case of minia-
ultracompact nanomembrane-based capacitor arrays is demonstrated by turized energy autonomous systems, such
combining bottom-up and top-down fabrication methods. The scalability as wireless sensor networks and medical
of the process is tested on a 4-inch wafer platform where 1600 devices are device implants,[3–5] the reduction of the
whole system must be addressed.[6] Min-
manufactured in parallel. By using a hybrid dielectric layer consisting of HfO2 iaturized energy autonomous systems
and TiO2 incorporated into an Al2O3 matrix, rolled-up ultracompact capacitors (MEAS) are ultracompact elements that
can have their capacitance per footprint area increased by over two orders of are able to operate with a minimum of
magnitude. Their electrical properties can be precisely controlled by adjusting human interference after their installa-
the oxide composition. Furthermore, the rolling of large-area nanomembrane- tion.[7,8] In order to accomplish this, MEAS
need not only to autonomously collect
based structures naturally results in a substantial decrease of the occupied
energy but also store it for future use.[9,10]
footprint area. Such electrostatic rolled-up ultracompact energy-storage ele- Both the miniaturization of the electronic
ments have a large potential in powering various autonomous microsystems. devices (sensing and processing units)
and the reduction of the footprint area of
the energy harvesters and energy-storage
1. Introduction elements (ESE) are essential ingredients to develop future
MEAS.[11,12]
Our increasingly mobile society urgently calls for novel In the past years, substantial efforts have been dedicated to
approaches to create ultracompact integrative devices for port- produce more compact and efficient energy harvesters.[13] In the
able use. To date, the miniaturization in microelectronics field of compact ESE, model systems have already been success-
has been mainly focused on the shrinkage of transistors and fully realized.[14–16] In order to make ESE suitable for MEAS, a
set of selected features are required: long life (10 years or more)
and short charging times (seconds to minutes) associated with
R. Sharma, Dr. D. Grimm, R. Sommer,
a large number of charge-discharge cycles (up to 10 000 cycles),
A. Wollatz, J. Schadewald, Dr. P. F. Siles,
Prof. O. G. Schmidt small geometrical dimensions (<1 mm2), high temperature
Technische Universität Chemnitz stability, and parallel manufacturing capability.[17] Even though
Material Systems for Nanoelectronics the use of solid-state electrolytes and the surface engineering
Reichenhainer Str. 70, 09107 Chemnitz, Germany of conventional semiconductors present alternatives to increase
E-mail: daniel.grimm@etit.tu-chemnitz.de
the energy density and consequently to reduce the dimen-
R. Sharma, Dr. C. C. B. Bufon, Dr. D. Grimm,
Dr. D. J. Thurmer, M. Bauer, Prof. O. G. Schmidt sions of ESE, the features mentioned above still represent a
Institute for Integrative Nanosciences, IFW Dresden challenge.[18,19] Alternatively, electrostatic capacitors can fulfill
Helmholtzstr. 20, 01069 Dresden, Germany very well criteria including life and charging time, number of
E-mail: cesar.bof@lnnano.cnpem.br charging–discharging cycles, miniaturization and large scale
Dr. C. C. B. Bufon production. Yet, these systems become less appealing when
Brazilian Nanotechnology National Laboratory, CNPEM
energy storage capabilities above 1–2 Wh kg–1 are required.
PO Box 619, 13083–970 Campinas, Brazil
However, with the continuous decreasing power dissipation in
Dr. D. Grimm, Dr. P. F. Siles, Prof. O. G. Schmidt
Technische Universität Chemnitz embedded digital signal processors, which has been observed to
Cluster of Excellence MERGE follow a scaling trend of ≈1.6× per year (also known as Gene’s
Faculty of Mechanical Engineering law[20]) the opportunity of employing electrostatic energy storage
Reichenhainer Straße 70, 09107 Chemnitz, Germany units in MEAS becomes attractive. An additional contribution
Prof. O. G. Schmidt to this tendency is the continuous improvement of thin film
TU Dresden, Center for Advancing Electronics Dresden (cfAED)
Barkhausen Building II/7b, 01062 Dresden, Germany dielectrics based on high-k oxide and ceramic films that can also
contribute to the development of ultracompact energy storage
DOI: 10.1002/aenm.201301631 elements that are suitable for MEAS.[21,22] At the microscale,

Adv. Energy Mater. 2014, 1301631 © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim wileyonlinelibrary.com (1 of 8) 1301631
 www.advenergymat.de
FULL PAPER
rolled-up nanotechnology has emerged as an alternative tech-
nique to create 3D ultracompact electronic devices with sub-
stantially reduced processing complexity, such as tubes, scrolls,
helices, rings, etc.[23–30] In this approach, the corresponding
planar devices are fabricated on pre-strained hybrid nanomem-
branes by conventional 2D processing techniques.[31–34] The
optimization of the intrinsic mechanical strain in the device’s
layers allows the autonomously rolling of the planar structure
once it is released from the host substrate. Therefore, with the
combination of these bottom-up and top-down methods, 3D
ESE[35] with a footprint area of at least two orders of magnitude
smaller than their planar counterparts can be fabricated.[23]
Such shrinkage represents a substantial gain in energy density
without making use of the conventional top-down nanofabrica-
tion methods, such as electron beam lithography and/or nano-
structuring, for instance.[19] Multilayer ceramic capacitors are
fabricated by contacting several vertically stacked layers in par-
allel. A large number of alternating deposition[36] or membrane
transfer[37] steps is required to build the stacked devices.[37] To
increase further the capacitances, ever thinner dielectric films
need to be transferred, with thicknesses already in the techno-
logical limit.[38] This challenge can be avoided by employing the
single step rolled-up nanotechnology.
2. Fabrication Methods
Towards the development of ultracompact electrostatic energy
storage elements, in this work we have successfully employed
the rolled-up nanotechnology to decrease the footprint area of
capacitors and to increase their capacitance by using Al2O3,
TiO2 and HfO2 as dielectric multilayers. The self-assembling
rolled-up process is responsible for the decrease of the device’s
footprint area and consequently for the increase of the capaci-
tance per footprint area. The electrical properties of these
rolled-up ultra-compact capacitors (UCCaps) are tailored by
combining different high-k dielectrics. Furthermore, we dem-
onstrate strategies to increase the capacitance per footprint area
(Cpa) of a single element by modifying the UCCap geometry.
In order to highlight the flexibility and scalability of the self-
assembly process described here, an amount of 1600 UCCaps
were manufactured in parallel on a 4-inch wafer platform.
The fabrication steps for processing rolled-up UCCaps are
schematically illustrated in Figure 1a–e. The process starts by
microstructuring planar double-plate capacitors by sequentially
depositing metal and oxide layers on top of a sacrificial layer,
which is selectively removed during the release of the device
from its host substrate.[23,31] All the patterning of the nanomem-
brane is performed by standard photolithography. First the Ge
sacrificial layer is physical vapor deposited on top of a Si/SiO2
substrate (Figure 1a). Next the sacrificial layer undergoes an oxi-
dation procedure to form GeOx, which is soluble in water.[25,26]
Afterwards, the strained first plate of the UCCap is prepared
by sequentially depositing 5 nm Au and 15 nm Ti (Figure 1b).
Using gold as the first deposited layer results in a low adher-
ence of the entire capacitor device processed on top. This anti-
sticking property assists the delamination of the capacitors for
long rolling distances. The complete sample is then covered
by a combination of oxides via atomic layer deposition (ALD).
1301631 (2 of 8) wileyonlinelibrary.com © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
www.MaterialsViews.com
Figure 1. Fabrication process for rolled-up UCCaps. a) Deposition and
patterning of sacrificial layer (Ge), which is further oxidized to form GeOx.
b) Deposition of the 1st plate (Au/Ti) and oxide multilayer stack. c) Depo-
sition of 2nd plate (Cr) and oxide multilayer stack. d) Deposition of bond
pads (Cr/Au) and opening of the trench. e) Rolling of the UCCap, starting
from the dashed line. f) Layer sequence of the planar structure. g) Com-
position of the 7 nm thick dielectric multi-layer, where x is the thickness
of TiO2 or HfO2. h) Surface roughness measured by AFM at the edge
Cr/oxide: rms ≈ 0.5 nm (Cr) and rms ≈ 0.9 nm (Cr/Al2O3/TiO2). Optical
microscopy images of a processed capacitor i) before and j) after rolling.
The dashed lines indicate the area consumed by the planar capacitors
before rolling. k) Typical image of an array of UCCaps highlighting the
high reproducibility of the process.
Here, we use a multi-layer stack consisting of Al2O3, HfO2 and
TiO2 (Figure 1g). Next, the second capacitor plate is formed by
depositing 20 nm strained Cr (Figure 1c). Finally, the second
oxide multi-layer is deposited by ALD, which is necessary to
prevent the first plate from short-circuiting the second plate
after rolling up the planar capacitor. The thicknesses and mate-
rial configuration of the second oxide layer are identical to the
first oxide multilayer. Figure 1f shows the sketch of the oxide
layer sequence used to form the planar device. The next fabrica-
tion step consists in preparing the bond pads by first selectively
removing the oxide layers by HF etching and then depositing
20 nm Cr and 30 nm Au (Figure 1d). All thicknesses and the
top surface roughness are confirmed via atomic force micros-
copy (AFM) as shown in Figure 1h. The surface roughness after
deposition of the bottom Cr layer (rms ≈ 0.5 nm) is slightly
increased compared to the substrate (rms ≈ 0.3 nm). The depo-
sition of the oxide multilayer (Al2O3/TiO2) increases the rough-
ness slightly more to values around rms ≈0.9 nm.
After the microfabrication of the planar capacitor structure,
the substrate is immersed in the wet etchant solution (2%
H2O2) to start selectively removing the Ge/GeOx sacrificial
layer.[23] The rolling speed was kept around 50 μm h–1. Upon
the release of the hybrid nanomembrane, the strain relaxation
leads to the curling of the structure (Figure 1e). This procedure
Adv. Energy Mater. 2014, 1301631
 www.advenergymat.de
www.MaterialsViews.com

FULL PAPER
decreases the area occupied by the capacitor, leading to a higher
Cpa. The value of Cpa is directly dependent on the rolling length
as well as on the tube diameter which can be precisely con-
trolled by several processing parameters, including the rolling
speed, thicknesses of employed thin films and their respec-
tive deposition rates.[23,32] Figure 1i,j shows optical micros-
copy images of the device before (i) and after (j) rolling. The
rolled-up capacitor forms into a tube-like structure with ≈15 μm
diameter and ≈6 windings. The rolling of the hybrid nanomem-
brane results in a reduction of the footprint area from ≈0.060
mm2 to ≈0.003 mm2, which signifies a reduction of ≈20 times.
Figure 1k shows the optical image of a typical array of rolled-up
capacitors, confirming the high reproducibility of the fabrica-
tion process with a yield of ≈90%.

3. Results and Discussions

For electrostatic capacitors the change of the dielectric material
affects the heart of the device, and as such represents a major
challenge to the device fabrication, performance and func-
tionality, which needs to be fundamentally explored and opti-
mized. To optimize the electrical properties of the capacitors,
we incorporate HfO2 (k ≈ 20–25) or TiO2 (k ≈ 40–86) into the
Al2O3 matrix.[41] If for one side an increase of the capacitance
is expected by such multilayered combination, the leakage cur-
rent between the capacitor plates also tends to increase. This
effect is expected as both HfO2 and TiO2 have smaller band gap
energies (≈5.6 eV and ≈3.5 eV, respectively) when compared to
Al2O3 (≈8.8 eV).[42,43] Here, we investigate the electrical proper-
ties of the oxide multilayers grown via ALD before and after the
self-rolling. Figure 2a displays the dependence of the current as
a function of the applied electric field for different Al2O3 layer
thicknesses (7, 10, 13, 16 and 19 nm) before rolling. Regard-
less of the Al2O3 thickness, the critical (onset of leakage cur-
rent) and breakdown fields are found between Ecrit ≈ 3.5 MV Figure 2. Incorporation of high-k oxides in nanomembrane capacitors. a)
Leakage currents across the oxide layer as a function of the applied elec-
cm–1 and Ebreak ≈ 7.3 MV cm–1, respectively. These values agree
tric field (E) and Al2O3 thicknesses. The arrow indicates the increase of
with the ones typically reported for ALD grown Al2O3 layers.[44] the thickness: 7, 10, 13, 16, and 19 nm. Breakdown and critical field Ec are
This demonstrates that the properties of the Al2O3 oxide layers indicated. b,c) Leakage current as a function of HfO2 and TiO2 thickness
prepared here are independent of the layer thickness down to (x) incorporated into the Al2O3 matrix. The arrow indicates the increase
7 nm. Since the capacitance increases by decreasing the dielec- of the applied voltage: 0.5, 1, and 1.5 V, equivalent to 0.7, 1.4, and 2.1
tric layer thickness, for the rolled-up devices we employed an MV cm–1. d–f) Capacitance as a function of the frequency (f) for planar
and rolled-up devices: d) x = 0 (100% Al2O3), e) x = 4 nm (56% HfO2 +
overall oxide thickness of 7 nm as it exhibits low leakage cur-
44% Al2O3), and f) x = 1.5 nm (21% TiO2 + 79%. Al2O3). The capacitor
rents in the range of a few pA. area is 200 × 300 μm2.
Figure 2b,c shows the dependence of the leakage current
with the applied bias and the systematic incorporation of HfO2
and TiO2 (see the multilayer stack in Figure 1g) into the Al2O3 TiO2 thickness of 20 nm was required to fabricate capacitors
matrix. The systematic incorporation of these oxides into the with a pure TiO2 dielectric layer showing acceptable low leakage
Al2O3 dielectric matrix leads to increased leakage currents. currents. Nevertheless, in the presence of the Al2O3 layer at
Regardless of the amount of HfO2 and TiO2 incorporated, the the metal-plate/TiO2 interfaces (as shown in Figure 1g), the
total thickness of all multilayered dielectrics are kept constant electrical properties are improved by suppressing the leakage
at 7 nm following the sketch presented in Figure 1g. While it current.
was possible to prepare up to 4 nm of HfO2 sandwiched by Figure 2d shows the capacitance–frequency (C–F) measure-
3 nm of Al2O3, (Figure 2b), only 1.5 nm of TiO2 was possible to ments for planar and rolled-up capacitors consisting of a 100%
be incorporated (Figure 2c) without compromising the desired Al2O3 layer as dielectric material. The capacitance remains almost
low-level leakage current (≈100 nA). For TiO2, the leakage cur- constant up to ≈100 kHz for measurements performed with
rent is, apart of the lower energy band gap, further associated an AC amplitude of 50 mV. An on-set of capacitance decrease
with a higher density of Ti-O bond related defects, which makes is observed around 1 MHz, which is expected for thin dielectric
the material actually semiconducting.[45] Thus, a minimum and electrode films[23,46,47] As the oxides with higher dielectric

Adv. Energy Mater. 2014, 1301631 © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim wileyonlinelibrary.com (3 of 8) 1301631
 www.advenergymat.de
www.MaterialsViews.com
FULL PAPER

constants are incorporated into the Al2O3 matrix (Figure 2e,f), the
capacitance of both planar and rolled-up devices increases.[48] The
incorporation of material with higher dielectric constants leads to
an increase of the dielectric losses.[47,49] The ALD grown oxides
are mainly amorphous and the capacitor’s performance might be
further improved by modifying the hybrid oxide layers during or
after the device preparation through thermal treatment.[50] Yet,
the increase of the dielectric constant by heat treatment causes
also an increase in leakage current. Thus, no thermal treatment
was applied to the oxide layers presented here.
By evaluating the capacitance of the hybrid oxide layer, the
dielectric constants of both HfO2 and TiO2 embedded thin films
can be obtained.[23] In this case, the equivalent capacitance can
be modeled as a series circuit consisting of three capacitors rep-
resenting each individual dielectric material with a well-known
thickness. From the circuit analysis, we estimate the relative die-
lectric constants as ≈7.2, ≈16, and ≈45 for Al2O3, HfO2 and TiO2
respectively, which is comparable to previous reported results.[51,52]
Since the bottom metal plate forms an additional interface
with the top oxide layer during the rolled-up of the nanomem-
brane, the total absolute capacitance of the devices enhances
upon rolling. This capacitance increase depends on the tight-
ness of the windings during rolling as well as the numbers
of windings in the rolled-up capacitor.[23] The tightness of the
windings can be evaluated by taking the ratio of the capaci-
tance for the rolled device (Croll) and its planar value (Cpl) and
1
equals C roll /C pl = 2 − . Theoretically, this value approaches
N
2 as the number of windings tends to infinity.[23] As shown in
Figure 3. Incorporation of high-k dielectrics in rolled-up UCCaps. The
Figure 3a,b, the increase of the total capacitance after rolling up ratio of the rolled-up to planar capacitance (Croll/Cpl) with a) HfO2 and
the nanomembrane is evident for all dielectric compositions. b) TiO2 incorporation. Insets show the cross-sectional SEM views of the
By evaluating Croll/Cpl, the capacitances of rolled-up capacitors UCCaps. The windings are indicated by blue arrows. c) Capacitance per
based on 100% Al2O3 dielectric layers (x = 0 in Figure 3a) as footprint area, Cpa, and increase of Cpa for UCCaps as a function of the
well as Al2O3-TiO2 multilayers (Figure 3b) increase by a factor HfO2 and TiO2 incorporation. The measurements are performed at 1 kHz
of ≈1.3. Upon HfO2 incorporation, an increase of typically 1.7 is and with an AC amplitude of 50 mV. The total oxide multilayer thickness
is kept constant (7 nm).
observed upon rolling. Considering the number of windings
performed (≈6), the capacitance increasing factor is expected
to be ≈1.8 for all devices.[23] Since the rolling speed was kept require the capability of scaling up the amount of devices fabri-
constant, the main reason to explain the deviation from the cated in parallel. Therefore, apart from tailoring the capacitance
calculated value is the presence of voids caused by loose wind- of UCCaps by incorporating HfO2 and TiO2, the devices can
ings. This possibility is further supported by cross-sectional be properly engineered in a variety of configurations to allow
scanning electron microscopy (SEM) images shown in the inset better integration, parallel production, higher compactness
of Figure 3a,b. As expected, the SEM image of the HfO2 based factor and increased capacitance per element. As in Figure 4,
devices shows very tight windings and no visible voids. The UCCaps with different geometries can be prepared on a 4-inch
tightness of subsequent windings can be further improved by wafer, demonstrating the high flexibility of the fabrication pro-
optimizing the process parameters, such as the rolling speed, cess. As a first attempt to increase the nominal capacitance of
thicknesses of employed thin films and their respective depo- the UCCap, the planar structure was designed and strain engi-
sition rates as well as rolling length. As later discussed, for a neered to allow for rolled-up of longer tubes, and consequently
large number of windings (e.g., 22) a capacitance increase larger active areas. Limitations in further increasing the planar
close to the theoretical value is retained. Figure 3c shows the device’s area are mainly given by the density of defects pre-
increase of Cpa for rolled-up devices as a function of the amount sent on the metal/oxide layers and/or on the substrate and its
of incorporated HfO2 and TiO2. The incorporation of high-k aspect ratio (length × width).[53,54] Here the density of defects
oxides allows achieving an increase of up to 100% of Cpa when were reduced by adopting conventional cleaning procedures of
compared to UCCaps using only Al2O3 as dielectric. the substrate based on oxygen plasma, using moderate metal
deposition rates to avoid excessive stress in the deposited layers
(and the consequent presence of cracks on the plates) and
3.1. Optimization of Rolled-up Device Geometry performing the ALD deposition at 200 °C. The aspect ratios
were investigated to maximize the device’s active area, consid-
Besides the miniaturization of the device footprint and the ering the particular multi-layer combination adopted here (see
increase of its capacitance, applications such as MEAS also Figure 1f). The optimum values to allow an effective rolling

1301631 (4 of 8) wileyonlinelibrary.com © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim Adv. Energy Mater. 2014, 1301631

www.MaterialsViews.com
Figure 4. UCCaps in different geometries on a 4-inch wafer platform.
a–c) Optical microscopy images of rolled-up capacitors with different
shape and size employing Al2O3 (7 nm) as the dielectric layer. The planar
capacitors rolled-up into tubes with 13 μm ± 1 μm diameter, independent
of shape and size of the planar device adopted. The arrows indicate the
direction of rolling. a) Single UCCap rolled-up from a 0.5 mm2 planar
area. The inset shows the capacitance as a function of frequency for the
UCCap before and after rolling. b) Double tube UCCap rolled-up from a
0.5 mm2 planar area. c) Double UCCap rolled-up from a 1 mm2 planar
area. d) Array of double tube UCCaps prepared on a 4-inch wafer plat-
form. e) Array of two parallel rolled UCCaps during rolling. f) Top: two
parallel UCCaps during rolling, bottom: two parallel UCCaps after suc-
cessful rolling. g) 4-inch Si/SiO2 wafer containing nearly 1600 UCCaps
processed in parallel.
Adv. Energy Mater. 2014, 1301631 © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
www.advenergymat.de
with a minimum of device loss and defects are 0.5 × 1 mm2,
FULL PAPER
0.5 × 0.5 mm2 and 1 × 0.5 mm2. Figure 4a shows a capacitor
rolled-up from a 0.5 × 1 mm2 planar structure at a rolling speed
of ≈50 μm h–1. While the rolling distance is the same as for
previously reported capacitors (1 mm), the final tube is twice
as long.[23]
For each added winding, the tube diameter increases by two
times its total layer thickness (≈54 nm, see Figure 1f). It adds
a total of ≈2.3 μm to the external diameter of the tube after
22 windings.[24] Since the measurement of the tube diameter
was performed by optical microscopy, its increase due to the
addition of 22 windings is nearly close to the measurement pre-
cision (≈1 μm). Therefore, regardless of the number of wind-
ings performed here, we consider that the tube diameter is kept
at 13 μm ± 1 μm. For the device in Figure 4a, it represents a
reduction of the footprint area by a factor 70–90 (from a planar
structure with 0.5 mm2 into a 3D tube-like structure with no
more than 0.008 ± 0.001 mm2). The inset of Figure 4a shows
the capacitance of an Al2O3-based UCCap measured before and
after rolling. After forming an UCCap with ≈22 windings, the
capacitance increases by a factor of ≈1.8 (from ≈5 nF to ≈9 nF),
which is close to the maximum theoretical value[23] of ≈1.95. In
this case, loose windings are responsible for ≈8% of the losses
in the additional interface area. Considering the decrease of the
footprint area obtained, Cpa evolves from 1.8 μF cm–2 to 130 μF
cm–2. Such values are in agreement with the previously reported
works once the oxide layer thickness is taken into account.[23]
Similar to what was observed for smaller UCCaps, the meas-
ured capacitance of larger area devices is almost constant up
to 5 kHz for planar and rolled-up devices, and also agrees with
the previously reported results.[23] This suggests that the rolling
process neither adds defects to the devices nor any micro-
cracks in the dielectric layer. The phase angle for planar as well
as rolled up devices is close to –90° up to ≈5 kHz, which con-
firms the fully capacitive behavior and negligible losses of the
UCCaps in this range.
The technology demonstrated here also allows creating self-
rolled double-tube capacitors electrically connected in parallel
(see Figure 4b), opening possibilities for more versatile sys-
tems. Besides permitting a better use of the optimal aspect
ratios, this type of geometry also allows positioning the UCCaps
wherever they are needed. Furthermore, this novel double -tube
design satisfies the required architecture idealized to electri-
cally drive autonomous systems.[34] In terms of the overall
energy storage capacity, the double tube capacitor in Figure
4b presents the same capacitance value as the element shown
in Figure 4a (≈9 nF), which is divided in two interconnected
rolled-up structures. The two UCCaps are electrically contacted
in parallel and share the same bond pads. Figure 4c shows an
element consisting of two 1 mm long tubes comprising ≈10
windings each and summing up to a total capacitance of ≈18
nF and a Cpa of ≈180 μF cm–2, calculated by using the tube’s
footprint area. Considering that the Al2O3 thickness is set to
7 nm, in order to keep the leakage current under control, the
value obtained for Cpa is as good as the ones reported in pre-
viously reported rolled-up capacitors formed by 3–4 nm oxide
layers.[23] The ratio Croll/Cpl in this case is ≈1.8 and agrees with
the theoretical limit (≈1.9) considering the number of wind-
ings of each tube. This indicates that on average the presence
wileyonlinelibrary.com (5 of 8) 1301631
 www.advenergymat.de
FULL PAPER
of voids in between subsequent windings is responsible for
a loss of ≈6% of the interface area created during rolling. As
was shown for the smaller and single tube UCCaps, the pro-
cess can also be up-scaled for the double-tube devices. Figure
4d shows part of a large array of double-tube UCCaps fabricated
in parallel on a 4-inch Si/SiO2 platform (Figure 4e). A total of
1600 UCCaps were fabricated. Another approach to improve
the space required for device fabrication is the parallel rolling
of two (or more) UCCaps from the same substrate area.[55]
Two complete sacrificial/capacitor layer stacks are processed
on top of each other and then rolled in parallel. With the aid
of the patterning, the starting of the second tube is delayed
as shown in Figure 4e. After finishing the double rolling, the
final device consisting of the two parallel contacted UCCaps
is shown in Figure 4f. In summary, the total capacitance can
be increased upon rolling as well as exploring new geometries
such as fabricating two UCCaps contacted in parallel or two (or
more) stacked UCCaps. The capacitance per footprint can be
increased by longer rolling distances and is mainly limited by
the defect density of the deposited films.
After rolling of the planar structure, the empty area on the
wafer can be further processed. By a smart device layout, the
capacitors could be, for instance, fabricated on the cutting area
(dicing streets) between the dies which is typically between
200–300 μm, depending on the dicing blade thickness. The
capacitors can then be rolled onto the active dice area, mini-
mizing the occupied device footprint. Alternatively, it is pos-
sible to remove the devices from the host substrate and reas-
semble them to form compact energy storage cells using well-
established transfer methods.[56] Thus, much larger capaci-
tances per occupied footprint can be obtained which could be
explored for many micrometer sized electronic components
such as autonomous microsystems. This is not possible with
extended two-dimensional capacitor sheets. Such approach may
also allow the transfer onto flexible substrates as well as the ver-
tical reassembling of the UCCaps. Concerning the creation of
electrostatic ESE for MEAS, the incorporation of high-k oxide
multilayers into large rolled areas (e.g., Figure 4c) may lead to
an increase of the total capacitance to ≈40 nF and Cpa to ≈400
μF cm–2. So far, it was possible to roll up 1 mm long capacitors
stripes. By continuously improving the defect density to allow,
for instance, the rolled-up of structures with an active area of
≈10 mm2, it is possible to obtain Cpa as large as ≈1.5 mF cm–2,
considering the layer configuration as shown in Figure 1g,f.
3.2. TEM of the Rolled-up Capacitor Superlattice
To gain further insights into the material composition of the
final UCCap, we perform cross-sectional transmission electron
microscopy (TEM) images. The layer stacking can be nicely
visualized in the focused ion beam (FIB) cut along the UCCap
tube axis (Figure 5). The overview TEM in Figure 5a shows 14
subsequent windings closely packed. The high magnification
image in Figure 5b indicates the individual layers of three con-
secutive windings close to the surface of the inner, hollow core
of the UCCap. Both TEM images show interfaces with no vis-
ible defects between the subsequent windings of the UCCap.
The material composition of the multi-layered system is
1301631 (6 of 8) wileyonlinelibrary.com © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
www.MaterialsViews.com
Figure 5. Cross-sectional TEM images of 1 mm long rolled-up UCCaps.
a) Overview of a section of 14 stacked capacitor layers. b) High magnifica-
tion image of the region close to the inner hollow core of the tube indi-
cating three consecutive stacked multi-layers. c) Color-coded STEM-EDX
map of the same region as (b). The colors are pink for Ti (d), yellow for
Al (e), and blue for Cr (f). The scale bar for (b–f) is 20 nm.
evaluated by energy-dispersive X-ray spectroscopy (EDX) in the
scanning mode (STEM). The merged color-coded EDX maps
are shown in Figure 5c. The individual elementary maps are
shown in Figure 5d–f for Ti (pink), Al (yellow), and Cr (blue)
respectively. The top part of the images without EDX signal
originates from the hollow core of the UCCap. The deposited
layered capacitor system of a single winding consists of 10 nm
Ti, 7 nm Al2O3, 12 nm Cr, and 7 nm Al2O3. The evaluation of
the maps allows the clear distinction of each capacitor layer,
with thicknesses close to the targeted ones. The material com-
position is homogenous within each layer and no visible inter-
diffusion is observed. The closely packed layers supports the
conclusion that the rolling up creates an additional active area
which increases substantial the final capacitance of the devices.
4. Conclusion
Towards the creation of electrostatic energy storage elements
that can be effectively used in a variety of miniaturized autono-
mous systems, we demonstrated the feasibility of fabricating
ultracompact capacitors employing rolled-up nanotechnology.
The EDX spectra show a closely packed layered system without
material interdiffusion. While self-assembly is responsible for
increasing the capacitance per footprint area and the total capac-
itance of the devices, it is possible to tailor their electrical prop-
erties by incorporating high-k oxides such as TiO2 and HfO2. In
fact, the capacitance of UCCaps using multi-layered dielectrics
can be increased by over 100%. We have fabricated UCCaps
with nearly two orders of magnitude reduced footprints when
compared to their planar counterparts. Upon rolling up, the
capacitance can be further improved close to a value nearly
twice as large as the planar unrolled device. The rolling tech-
nique results in a substantial reduction of one device dimen-
sion that not only influences the UCCaps electrical properties
but also allows for a better integration of the devices into minia-
turized autonomous systems.
A total of 1600 UCCaps with various geometries were pre-
pared on a 4-inch Si/SiO2 wafer, highlighting the flexibility
Adv. Energy Mater. 2014, 1301631

www.MaterialsViews.com
of the parallel fabrication process. By further reducing defect
densities in both deposited layers and substrates, significantly
larger area devices can be prepared. Thus, not only the nominal
capacitance but also Cpa can be increased. Alternatively, very
high-k materials such as thin film ceramics[57] with dielectric
constants exceeding 100, can be incorporated in rolled-up struc-
tures. For applications where features like charge-discharging
times, number of performed cycles and lifetime are not critical,
the use of solid state electrolytes may be a route to the creation
of rolled-up supercapacitors.[58,59]
5. Experimental Section
Device Fabrication: The 20 nm Ge sacrificial layer was deposited by
RF sputtering (Moorfield Minilab S60A) on top of a Si/SiO2 substrate
previously patterned. After deposition, the Ge underwent a 12 h
oxidation procedure in an oven at 60 °C under oxygen atmosphere. The
first capacitor plate consisted of 5 nm Au and 15 nm Ti sequentially
deposited by electron-beam evaporation (IM9912-Micronova) at a base
pressure of p0 = 1 × 10−7 mbar and a rate of 1 Å s–1. All oxide layers
were grown by ALD (Cambridge Nanotech Savannah100) at 200 °C
using TMA (trimethyl aluminum), tetrakis (dimethylamido) hafnium(IV)
(Hf (NMe2)4) and tetrakis (dimethylamido) titanium(IV) (Ti (NMe2)4) as
precursors. All precursors were high purity and purchased from Sigma-
Aldrich. The multilayer stacks consisting of Al2O3, HfO2, and TiO2 were
deposited with rates of 1.1 Å, 0.8 Å, and 0.33 Å per cycle. The second
capacitor plate was formed by depositing 20 nm strained Cr by electron-
beam evaporation with a rate of 3 Å s–1 at p0 = 1 × 10−7 mbar. The oxide
removal, when necessary, was made by a quick dip in HF (3.3%). The
bonding pads were made of 20 nm Cr and 30 nm Au. For releasing the
nanomembrane, the planar capacitor structure was immersed in H2O2
(30%). After 2 min, the sample was transferred to a solution of H2O:
H2O2 (1:50) in order to maintain the rolling speed around 50 μm h–1.
Electrical Characterization: The current-voltage traces were measured
by using a Keithley 2611A source-meter while the capacitance-frequency
curves were obtained using a Hioki 3532–50 LCR meter.
Atomic Force Microscopy: All the AFM measurements were performed
with an Agilent 5600LS system, under an argon (Ar) controlled
environment. Measurements were performed in Tapping Mode using
special ultrasharp (4–10 nm tip radius) Olympus cantilevers, which
allowed high resolution measurements. Mapping of the topographic
characteristics was performed on different points of the samples over
the different oxide layers, in order to verify the uniformity and roughness
of the oxide structures on the different stages of the fabrication process.
Scanning Electron Microscopy: The as-processed devices were imaged
using a Zeiss Cross-beam or SII instrument SMI3050SE with 5–30 kV
acceleration voltage. Images were typically obtained using 5 kV to reduce
damage to the sample from the electron beam and enhance the surface
features. All images were obtained using the secondary electron (SE)
detector.
Focused Ion Beam: The cross-sectional images as well as TEM
lamellae were prepared by an attached Ga-ion FIB milling column for
vertical cutting, followed by SE imaging (Zeiss NVision40 dual-beam).
Transmission Electron Microscopy: The images were obtained using
the Scanning Transmission Electron Microscopy (HITACHI/HD-2300A)
with energy-dispersive X-ray detector (EDAX/Octane Plus). Typical
acceleration voltage was 200 kV.
Acknowledgements
The authors acknowledge Stefan Baunack, Frank Wendler, Markus
Freund, Nicole Köhler, Philip Düe, Sabine Engelmann, and Wolfgang
Borchardt for their technical support and fruitful discussions. This work
Adv. Energy Mater. 2014, 1301631 © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
www.advenergymat.de
FULL PAPER
was partially supported by the Cluster of Excellence MERGE and the U.S.
Air Force Office of Scientific Research MURI program.
Received: October 25, 2013
Revised: December 29, 2013
Published online:
[1] International Technology Roadmap for Semiconductors (ITRS) 2011
Edition International Technology Roadmap for Semiconductors
(ITRS) 2011 Edition.
[2] J. Rector, J. J. Dougherty, V. Brown, J. Galvagni, J. Prymak, in Proc.
47th Electronic Components and Technology Conference, San Jose,
IEEE, Piscataway, 1997, pp. 713.
[3] J. Lueke, W. A. Moussa, Sensors 2011, 11, 1433.
[4] M. Lallart, D. Guyomar, Smart Mater. Struct. 2008, 17.
[5] P. Valdastri, E. Susilo, T. Foerster, C. Strohhoefer, A. Menciassi,
P. Dario, IEEE Trans. Biomed. Eng. 2011, 58, 1846.
[6] M. Belleville, H. Fanet, P. Fiorini, P. Nicole, M. J. M. Pelgrom,
C. Piguet, R. Hahn, C. Van Hoof, R. Vullers, M. Tartagni,
E. Cantatore, Microelectron. J. 2010, 41, 740.
[7] J. Nurnus, in Smart Sensors, Actuators, and Mems Iv (Ed: U. Schmid,
C. Cane, H. Shea), Spie-Int Soc Optical Engineering, Bellingham
2009; Vol. 7362.
[8] B. Gyselinckx, C. Van Hoof, J. Ryckaert, R. F. Yazicioglu, P. Fiorini,
V. Leonov, Human++: Autonomous wireless sensors for body area net-
works IEEE, New York 2005.
[9] P. B. Ruffin, C. L. Brantley, E. Edwards, J. K. Roberts, W. Chew,
L. C. Warren, P. R. Ashley, H. O. Everitt, E. Webster, J. V. Foreman,
M. Sanghadasa, S. H. Crutcher, M. G. Temmen, V. Varadan,
D. Hayduke, P. C. Wu, C. G. Khoury, Y. Yang, T.-H. Kim, T. Vo-Dinh,
A. S. Brown, J. Callahan, in Nanosensors, Biosensors, and Info-Tech
Sensors and Systems 2011 (Ed: V. K. Varadan), Spie-Int Soc Optical
Engineering, Bellingham 2011; Vol. 7980.
[10] G. Waibel, J. Kohnle, R. Cernosa, M. Storz, M. Schmitt, H. Ernst,
H. Sandmaier, R. Zengerle, T. Strobelt, Sens. Actuators 2003, 103,
225.
[11] W. Liu, X. Yan, J. Lang, C. Peng, Q. Xue, J. Mater. Chem. 2012, 22,
17245.
[12] D. A. C. Brownson, D. K. Kampouris, C. E. Banks, J. Power Sources
2011, 196, 4873.
[13] S.-J. Ding, Y.-J. Huang, Y. Li, D. W. Zhang, C. Zhu, M.-F. Li, J. Vac.
Sci. Technol. B 2006, 24, 2518.
[14] J. W. Lee, A. S. Hall, J.-D. Kim, T. E. Mallouk, Chem. Mater. 2012, 24,
1158.
[15] S. Meng, C. Basceri, B. W. Busch, G. Derderian, G. Sandhu, Appl.
Phys. Lett. 2003, 83, 4429.
[16] X. Liu, P. G. Pickup, J. Power Sources 2008, 176, 410.
[17] M. Belleville, E. Cantatore, H. Fanet, P. Fiorini, P. Nicole,
M. Pelgrom, C. Piguet, R. Hahn, C. V. Hoof, R. Vullers, Rep.
CATRENE Work. Group Energy Auton. Syst. 2009.
[18] J. B. Bates, N. J. Dudney, B. Neudecker, A. Ueda, Solid State Ionics
2000, 135, 33.
[19] L. C. Haspert, S. B. Lee, G. W. Rubloff, ACS Nano 2012, 6, 3528.
[20] G. Frantz, IEEE Micro 2000, 20, 52.
[21] High-K gate dielectrics; Series in materials science and engineering,
(Ed: M. Houssa), Institute of Physics, Bristol, PA 2004.
[22] G. D. Wilk, R. M. Wallace, J. M. Anthony, J. Appl. Phys. 2001, 89,
5243.
[23] C. C. Bof Bufon, J. D. Cojal González, D. J. Thurmer, D. Grimm,
M. Bauer, O. G. Schmidt, Nano Lett. 2010, 10, 2506.
[24] D. Grimm, C. C. Bof Bufon, C. Deneke, P. Atkinson, D. J. Thurmer,
F. Schäffel, S. Gorantla, A. Bachmatiuk, O. G. Schmidt, Nano Lett.
2012.
wileyonlinelibrary.com (7 of 8) 1301631
 www.advenergymat.de
FULL PAPER
[25] S. Mendach, O. Schumacher, H. Welsch, C. Heyn, W. Hansen,
M. Holz, Appl. Phys. Lett. 2006, 88, 212113.
[26] K.-J. Friedland, A. Siddiki, R. Hey, H. Kostial, A. Riedel, D. K. Maude,
Phys. Rev. B 2009, 79, 125320.
[27] F. Cavallo, R. Songmuang, O. G. Schmidt, Appl. Phys. Lett. 2008, 93,
143113.
[28] C. C. Bof Bufon, J. D. Arias Espinoza, D. J. Thurmer, M. Bauer,
C. Deneke, U. Zschieschang, H. Klauk, O. G. Schmidt, Nano Lett.
2011, 11, 3727.
[29] F. Cavallo, M. G. Lagally, Soft Matter 2010, 6, 439.
[30] J.-H. Cho, M. D. Keung, N. Verellen, L. Lagae, V. V. Moshchalkov,
P. Van Dorpe, D. H. Gracias, Small 2011, 7, 1943.
[31] O. G. Schmidt, K. Eberl, Nature 2001, 410, 168.
[32] V. Y. Prinz, Microelectron. Eng. 2003, 69, 466.
[33] E. Smela, O. Inganäs, I. Lundström, Science 1995, 268, 1735.
[34] E. J. Smith, W. Xi, D. Makarov, I. Mönch, S. Harazim,
V. A. B. Quiñones, C. K. Schmidt, Y. Mei, S. Sanchez, O. G. Schmidt,
Lab Chip 2012, 12, 1917.
[35] O. G. Schmidt, US Patent 8136213, 2012.
[36] T. Tsutsumi, S. Sugitani, K. Nishimura, M. Ida, Jpn. J. Appl. Phys.
2011, 50, 04DF09.
[37] H. Kishi, Y. Mizuno, H. Chazono, Jpn. J. Appl. Phys. 2003, 42, 1.
[38] K. Suzuki, T. Okamoto, H. Kondo, N. Tanaka, A. Ando, J. Appl. Phys.
2013, 113, 064103.
[39] M. K. Murthy, H. Hill, J. Am. Ceram. Soc. 1965, 48, 109.
[40] B. Onsia, T. Conard, S. De Gendt, M. M. Heyns, I. Hoflijk,
P. W. Mertens, M. Meuris, G. Raskin, S. Sioncke, I. Teerlinck,
A. Theuwis, J. Van Steenbergen, C. Vinckier, Solid State Phenom.
2005, 103–104, 27.
[41] S. Pan, S.-J. Ding, Y. Huang, Y.-J. Huang, D. W. Zhang, L.-K. Wang,
R. Liu, J. Appl. Phys. 2007, 102, 073706.
[42] S.-J. Ding, D. W. Zhang, L.-K. Wang, J. Phys. Appl. Phys. 2007, 40,
1072.
1301631 (8 of 8) wileyonlinelibrary.com © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
www.MaterialsViews.com
[43] K. Ganesan, S. Ilango, S. Mariyappan, M. F. Baroughi,
M. Kamruddin, A. K. Tyagi, Appl. Phys. Lett. 2011, 98, 092902.
[44] M. D. Groner, J. W. Elam, F. H. Fabreguette, S. M. George, Thin
Solid Films 2002, 413, 186.
[45] J.-C. Woo, Y.-S. Chun, Y.-H. Joo, C.-I. Kim, Appl. Phys. Lett. 2012,
100, 081101.
[46] W. Kübler, Thin Solid Films 1991, 199, 247.
[47] M. Tyunina, J. Phys. Condens. Matter 2006, 18, 5725.
[48] H. Spahr, C. Nowak, F. Hirschberg, J. Reinker, W. Kowalsky,
D. Hente, H.-H. Johannes, Appl. Phys. Lett. 2013, 103,
042907.
[49] P. J. Harrop, D. S. Campbell, Thin Solid Films 1968, 2, 273.
[50] P. F. Siles, M. de Pauli, C. C. Bof Bufon, S. O. Ferreira, J. Bettini,
O. G. Schmidt, A. Malachias, Nanotechnology 2013, 24,
035702.
[51] M. D. Groner, F. H. Fabreguette, J. W. Elam, S. M. George, Chem.
Mater. 2004, 16, 639.
[52] S. Dueñas, H. Castán, H. García, E. S. Andrés, M. Toledano-Luque,
I. Mártil, G. González-Díaz, K. Kukli, T. Uustare, J. Aarik, Semicond.
Sci. Technol. 2005, 20, 1044.
[53] P. Cendula, S. Kiravittaya, I. Monch, J. Schumann, O. G. Schmidt,
Nano Lett. 2011, 11, 236.
[54] I. S. Chun, A. Challa, B. Derickson, K. J. Hsia, X. Li, Nano Lett. 2010,
10, 3927.
[55] C. Deneke, O. G. Schmidt, Phys. E 2004, 23, 269.
[56] A. Carlson, S. Wang, P. Elvikis, P. M. Ferreira, Y. Huang, J. A. Rogers,
Adv. Funct. Mater. 2012, 22, 4476.
[57] S. Ito, H. Funakubo, I. P. Koutsaroff, M. Zelner, A. Cervin-Lawry,
Appl. Phys. Lett. 2007, 90, 142910.
[58] L. Wang, X. Liu, X. Wang, X. Yang, L. Lu, J. Mater. Sci.-Mater. Elec-
tron. 2011, 22, 601.
[59] M. Jayalakshmi, K. Balasubramanian, Int. J. Electrochem. Sci. 2008,
3, 1196.
Adv. Energy Mater. 2014, 1301631