SEQUENTIAL LOGIC

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Sequential Logic
φ

FF’s
LOGIC
tp,comb
Out In

2 storage mechanisms
• positive feedback
• charge-based
Digital Integrated Circuits Sequential Logic © Prentice Hall 1995
 Positive Feedback: Bi-Stability
Vo1 =Vi2
Vi1 Vo2

Vi2 = Vo1
Vo1

Vi1 Vo2
Vi2 = Vo1

B
Vi1 = Vo2

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Vi2 = Vo1 Meta-Stability

Vi2 = Vo1
B

δ Vi1 = V o2 δ Vi1 = Vo2

Gain should be larger than 1 in the transition region

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 SR-Flip Flop
S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
Q 0 1 0 1
R
1 1 0 0

S Q S R Q Q
S Q
1 1 Q Q
R Q
Q 0 1 1 0
R
1 0 0 1
0 0 1 1

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 JK- Flip Flop

Jn Kn Qn+1
J S Q Q
0 0 Qn
φ 1
0 0
K R Q Q 1 0 1
1 1 Qn

(c)
(a) J Q
φ
K Q

(b)

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Other Flip-Flops

T J D J
Q Q
φ φ φ φ
Q Q
K K

T Q D Q

φ Q φ Q

Toggle Flip-Flop Delay Flip-Flop

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Race Problem
tloop
t

φ
D Q t

1 φ Q

Signal can race around during φ= 1

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Master-Slave Flip-Flop
MASTER SLAVE

SI
J S Q S Q Q

RI
K R Q R Q Q

PRESET

J Q
φ
Q
K

CLEAR

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

Propagation Delay Based Edge-Triggered

In

N1
N2
In X X tpLH

φ Out

Out

= Mono-Stable Multi-Vibrator
Digital Integrated Circuits Sequential Logic © Prentice Hall 1995
 Edge Triggered Flip-Flop

S Q Q

R Q Q

J
Q
>φ
Q
K

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Flip-Flop: Timing Definitions

t
tsetup thold
In

DATA
STABLE
t

tpFF
Out

DATA
STABLE
t

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Maximum Clock Frequency
φ

FF’s
LOGIC

tp,comb

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 CMOS Clocked SR- FlipFlop

VDD

M2 M4

Q
Q

M6 M8
φ φ
M1 M3

S M5 M7 R

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Flip-Flop: Transistor Sizing

(1.8/1.2)
4.0
(3.6/1.2)
(7.2/1.2)
VQ

2.0

0.0
0.0 1.0 2.0 3.0 4.0 5.0

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 6 Transistor CMOS SR-Flip Flop

VDD

M2 M4 φ
φ
Q
Q S
R M5

M1 M3

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Charge-Based Storage

φ D φ

In D

φ (b) Non-overlapping clocks

(a) Schematic diagram

Pseudo-static Latch
Digital Integrated Circuits Sequential Logic © Prentice Hall 1995
 Master-Slave Flip-Flop

φ φ D
A
In
B

φ φ

Overlapping Clocks Can Cause

•Race Conditions
•Undefined Signals

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 2 phase non-overlapping clocks

φ1 φ2 D

In

φ2 φ1

φ1

φ2

tφ12

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 2-phase dynamic flip-flop

φ1 φ2

In D

Input Sampled

φ1

φ2

Output Enable

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

Flip-flop insensitive to clock overlap

VDD VDD

M2 M6

φ M4 φ M8
X
In D
CL1 CL2
φ M3 φ M7

M1 M5

φ− section φ− section

C2 MOS LATCH
Digital Integrated Circuits Sequential Logic © Prentice Hall 1995
 C MOS
2 avoids Race Conditions

VDD VDD VDD VDD

M2 M6 M2 M6

0 M4 0 M8
X X
In D In D
1 M3 1 M7

M1 M5 M1 M5

(a) (1-1) overlap (b) (0-0) overlap

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Pipelining
REG

REG
a a

REG

REG

REG
. .

REG
φ log Out φ log Out

φ φ φ φ
REG

REG
b b
Non-pipelined version Pipelined version
φ φ

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Pipelined Logic using C MOS
2

VDD VDD VDD

In φ φ φ
F G Out
φ C1 φ C2 φ C3

NORA CMOS

What are the constraints on F and G?

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995
 Example

VDD VDD VDD

φ φ
1
φ φ

Number of a static inversions should be even

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 NORA CMOS Modules
VDD VDD VDD
φ φ

In1 φ Out
PUN
In2 PDN
In3 φ
φ φ (a) φ-module

Combinational logic Latch

VDD VDD VDD VDD

φ In4

In 1 φ Out
In 2 PDN
In 3 φ
φ In4 (b) φ-module

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Doubled C MOS
2 Latches

VDD VDD VDD VDD

Out
In In
φ φ φ φ Out

Doubled n-C2MOS latch Doubled n-C2 MOS latch

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

TSPC - True Single Phase Clock Logic

VDD VDD VDD VDD

PUN

In
Static
φ φ φ φ
Logic Out

PDN

Including logic into Inserting logic between

the latch latches

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Master-Slave Flip-flops

VDD VDD VDD VDD V DD VDD

φ φ
Y
D D
D X
φ φ φ φ
D
φ φ

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

VDD VDD VDD

D D
φ φ

(c) Positive edge-triggered D flip-flop

using split-output latches

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Schmitt Trigger

Vout V OH
In Out

•VTC with hysteresis V OL

•Restores signal slopes

VM– VM+ Vin

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Noise Suppression using
Schmitt Trigger

Vin Vout

VM+

VM–

t0 t t0 + tp t

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 CMOS Schmitt Trigger
V DD

M2 M4

Vin X Vout

M1 M3

Moves switching threshold

of first inverter

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Schmitt Trigger
Simulated VTC

5.0 6.0

4.0

4.0
3.0

Vout (V)
V M+
VX (V)

2.0
2.0
V M-
1.0

0.0 0.0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0
Vin (V) V in (V)

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 CMOS Schmitt Trigger (2)
VDD

M4

M6

M3
In Out

M2
X
M5 VDD
M1

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Multivibrator Circuits
R

S
Bistable Multivibrator
flip-flop, Schmitt Trigger

T
Monostable Multivibrator
one-shot

Astable Multivibrator
oscillator

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

Transition-Triggered Monostable

In
DELAY
Out
td td

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Monostable Trigger (RC-based)

VDD

In R
A B Out

(a) Trigger circuit.

C

In

B VM
(b) Waveforms.

Out
t
t1 t2

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Astable Multivibrators (Oscillators)
0 1 2 N-1

Ring Oscillator

V1 V3 V5
5.0
V (Volt)

3.0

1.0

-1.0
0 1 2 3 4 5
t (nsec)

simulated response of 5-stage oscillator

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

Voltage Controller Oscillator (VCO)

Schmitt Trigger
V DD VDD
restores signal slopes
M6 M4

M2
In
M1
Iref Iref

Vcontr M3
M5 Current starved inverter

6
t pH L (nsec)

propagation delay as a function

0.0
0.5 1.5 2.5 of control voltage
V contr (V)

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995

 Relaxation Oscillator

Out 1
Out 2
I1 I2

R C

Int

T = 2 (log3) RC

Digital Integrated Circuits Sequential Logic © Prentice Hall 1995