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l Functionality
l Reliability, Robustness
l Area
l Performance
» Speed (delay)
» Power Consumption
» Energy
VDD
v(t)
i(t)
(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise
V(y)
V(x) V(y)
V f
OH
V(y)=V(x)
V Switching Threshold
M
VOL
VOL V V(x)
OH
V V(y)
"1" OH Slope = -1
V V
IH OH
Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH
"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"
...
v0 v1 v2 v3 v4 v5 v6
f(v) finv(v)
finv(v) f(v)
(a) Fan-out N
M
(b) Fan-in M
N
Vout
Ri = ∞
Ro = 0
g= − ∞
Vin
5.0
4.0 NML
3.0
Vout (V)
2.0
VM
NMH
1.0
50%
t
t t
pHL pLH
Vout
90%
50%
10% t
tf tr
v0 v1 v2 v3 v4 v5
v0 v1 v5
T = 2 × tp × N
Vin
Vout
CL
PMOS
1.2µm
=2λ
Out
In
Metal1
Polysilicon
NMOS
GND
Ron
VDD VDD
Ron
VOH = VDD
Vout VOL= 0
Vout
Vin = V DD Vin = 0
VDD
Vout
Vout ln(0.5)
CL
1 VDD
Ron
0.5
0.36
Vin = V DD
t
RonCL
IDn
V in = V DD -VGSp
IDn = - IDp
V out = VDD -V DSp
Vout
IDp IDn I Dn
Vin=0 Vin=0
V in=3 Vin=3
VGSp=-5
Vin = VDD -VGSp Vout = VDD -V DSp
IDn = - IDp
In,p
V in = 0 Vin = 5
NMOS
PMOS
Vin = 4 Vin = 1
V in = 3 Vin = 2
Vin = 0
Vin = 5
5 NMOS sat
PMOS lin
4
NMOS sat
3
PMOS sat
2
NMOS lin
PMOS sat NMOS lin
1
PMOS off
1 2 3 4 5 Vin
4.0
Vout (V)
2.0
0.0
0.0 1.0 2.0 3.0 4.0 5.0
Vin (V)
Digital Integrated Circuits Inverter © Prentice Hall 1995
Gate Switching Threshold
4.0
3.0
VM
2.0
G D
+
vgs gmvgs ro
-
VDD
Vout
Vout ln(0.5)
CL
1 VDD
Ron
0.5
0.36
Vin = V DD
t
RonCL
tpHL = CL Vswing/2
Iav
Vout CL
~
Iav CL kn VDD
Vin = V DD
M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2
Cdb1 Cw Cg3
M1 M3
Interconnect
Fanout
Vin Vout
Simplified
Model CL
PMOS
1.2µm
=2λ
Out
In
Metal1
Polysilicon
NMOS
GND
Cgd1 Vout
∆V
∆V Vout
∆V
Vin 2Cgd1
M1
M1 ∆V
Vin
0.3
t pH L (nsec)
0.25
0.2
0.15
0 0.2 0.4 0.6 0.8 1
t rise (nsec)
28
24
20
Normaliz ed Delay
16
12
0
1.00 2.00 3.00 4.00 5.00
VDD (V)
•Leakage
Leaking diodes and transistors
Vin Vout
CL
Energy/transition = CL * Vdd2
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
RC Vout
V CC
RB Vout
Vin Q1
VTC of nonsaturating gate
VCE (sat )
Cutoff Saturation
F orward-active
3.0
Vout
2.0
1.0
0.0
0.0 1.0 2.0 3.0 4.0 5.0
Vin
VOH is function of fan-out
Digital Integrated Circuits Inverter © Prentice Hall 1995
Transient Response of RTL Inverter
5.0
4.0
3.0
Vout
2.0
1.0
0.0
0.00e+00 5.00e-10 1.00e-09 1.50e-09 2.00e-09
t
RC RC
Vou t1 Vout 2
Core of gate:
Vin Q1 Q2 Vref The differential pair
Vx
or “current switch”
IEE
VEE
Vou t 1
Vo ut1 Vout2
Vo ut1 Vout2
Single-ended Differential
Digital Integrated Circuits Inverter © Prentice Hall 1995
Complete ECL Gate
Vcc Vcc Vcc Vcc
RC RC
VC 1 V C2
Q3 Q4
Vin Q1 Q2 Vre f
Vx
Vout 1 Vout 2
RB
VEE
IEE Emitter-follower
output driver
VEE
R1
Q5
Vre f D1
Issues:
D2
•Temperature variations
R3 R2 •Device variations
VEE
Q 1 s a turates
Vout1
VC C – VBE(on) – IEE R C
V ref Vin
Vswing = I EE RC
–0.80 Vout 1 Vo u t2
–0.90
Vou t (V)
–1.00
–1.10
–1.20
–1.30
–1.5 –1.3 –1.1 –0.9 –0.7 –0.5
Vin (V)
RC C bc RC
VC 1
C bc Q3 Cb c
Cc s Vout1
C be
Vin Q1 Q1 FAN-O UT
Vx
Cd C be Cd C be
IE E RB IEE
VEE
VE E VEE
1 IC 2
10 mA 5 mA
1 mA
0.5 mA
–1
0 0.1 0.2
Time (nse c )
V in V out1
–0.90
V (Vo lt )
–1.10
–1.30
0 0. 2 0.4 0.6 0. 8 1.0
t (ns e c )
150
tp LH (p s ec)
100
50
0
0 5 10 15 20
IE E (m A)