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Chapter 9.

Controller Design

9.1. Introduction
9.2. Effect of negative feedback on the network transfer
functions
9.2.1. Feedback reduces the transfer function from disturbances
to the output
9.2.2. Feedback causes the transfer function from the reference
input to the output to be insensitive to variations in the gains
in the forward path of the loop
9.3. Construction of the important quantities 1/(1+T) and
T/(1+T) and the closed-loop transfer functions

Fundamentals of Power Electronics 1 Chapter 9: Controller design


Controller design

9.4. Stability
9.4.1. The phase margin test
9.4.2. The relation between phase margin and closed-loop
damping factor
9.4.3. Transient response vs. damping factor
9.5. Regulator design
9.5.1. Lead (PD) compensator
9.5.2. Lag (PI) compensator
9.5.3. Combined (PID) compensator
9.5.4. Design example

Fundamentals of Power Electronics 2 Chapter 9: Controller design


Controller design

9.6. Measurement of loop gains


9.6.1. Voltage injection
9.6.2. Current injection
9.6.3. Measurement of unstable systems
9.7. Summary of key points

Fundamentals of Power Electronics 3 Chapter 9: Controller design


9.1. Introduction

Switching converter Load


Output voltage of a
+ iload(t) switching converter
depends on duty cycle
vg(t) + v(t) d, input voltage vg, and

load current iload.

Transistor
gate driver Switching converter
δ(t) δ(t) Pulse-width vc(t) v(t) = f(vg , iload , d)
modulator vg(t)
dTs Ts t
iload (t) } Disturbances
v(t)

d(t)
} Control input
Fundamentals of Power Electronics 4 Chapter 9: Controller design
The dc regulator application

Switching converter
Objective: maintain constant v(t) = f(vg , iload , d)
output voltage v(t) = V, in spite vg(t)
of disturbances in vg(t) and
iload(t).
Typical variation in vg(t): 100Hz
iload (t) } Disturbances
v(t)

or 120Hz ripple, produced by d(t)


rectifier circuit.
} Control input
Load current variations: a significant step-change in load current, such
as from 50% to 100% of rated value, may be applied.
A typical output voltage regulation specification: 5V ± 0.1V.
Circuit elements are constructed to some specified tolerance. In high
volume manufacturing of converters, all output voltages must meet
specifications.

Fundamentals of Power Electronics 5 Chapter 9: Controller design


The dc regulator application

So we cannot expect to set the duty cycle to a single value, and obtain
a given constant output voltage under all conditions.
Negative feedback: build a circuit that automatically adjusts the duty
cycle as necessary, to obtain the specified output voltage with high
accuracy, regardless of disturbances or component tolerances.

Fundamentals of Power Electronics 6 Chapter 9: Controller design


Negative feedback:
a switching regulator system

Power Switching converter Load


input
+
iload

vg + v

Sensor
– H(s) gain

Transistor Error
gate driver signal
δ Pulse-width vc G (s) ve –+ Hv
modulator c

Compensator
Reference
input vref
Fundamentals of Power Electronics 7 Chapter 9: Controller design
Negative feedback

Switching converter
v(t) = f(vg , iload , d)
vg(t)
Error
signal
ve(t)
iload (t)
vc Pulse-width d(t)
} Disturbances
v(t)

vref +– Compensator
modulator
} Control input
Reference
input
Sensor
gain

Fundamentals of Power Electronics 8 Chapter 9: Controller design


9.2. Effect of negative feedback on the
network transfer functions

Small signal model: open-loop converter


e(s) d(s) Le
buck converter

1 : M(D)
+

+

vg(s) + j(s) d(s) C v(s) iload (s)


– R


Output voltage can be expressed as
v(s) = Gvd(s) d(s) + Gvg(s) vg(s) – Z out(s) i load(s)
where
v(s) v(s) v(s)
Gvd(s) = Gvg(s) = Z out(s) = –
d(s) vg = 0 vg(s) d=0 i load(s) d=0
i load = 0 i load = 0 vg = 0

Fundamentals of Power Electronics 9 Chapter 9: Controller design


Voltage regulator system small-signal model

e(s)d(s) Le
1 : M(D)

+

• Use small-signal +
converter model
vg(s) + j(s)d(s) C v(s) iload (s)
– R
• Perturb and
linearize remainder –
of feedback loop:
d(s)
Error
vref (t) = Vref + vref (t) signal
vref (s) +– ve (s) vc (s) 1
Gc (s)
ve(t) = Ve + ve(t) Reference
VM
input Compensator Pulse-width
etc. modulator

H(s)v(s)
H(s)

Sensor
gain

Fundamentals of Power Electronics 10 Chapter 9: Controller design


Regulator system small-signal block diagram

iload (s) Load current


variation

vg (s) Zout (s)


Gvg(s)
ac line
variation
Pulse-width
Compensator modulator –
vref (s) + ve (s) vc (s) 1 d(s) + v(s)
– Gc(s) VM Gvd (s)
Reference Error Duty cycle + Output voltage
input signal variation variation
Converter power stage

H(s) v(s)
H(s)
Sensor
gain

Fundamentals of Power Electronics 11 Chapter 9: Controller design


Solution of block diagram

Manipulate block diagram to solve for v(s) . Result is

GcGvd / VM Gvg Z out


v = vref + vg – i load
1 + HGcGvd / VM 1 + HGcGvd / VM 1 + HGcGvd / VM

which is of the form


Gvg Z
v = vref 1 T + vg – i load out
H 1+T 1+T 1+T

with T(s) = H(s) Gc(s) Gvd(s) / VM = "loop gain"

Loop gain T(s) = products of the gains around the negative


feedback loop.

Fundamentals of Power Electronics 12 Chapter 9: Controller design


9.2.1. Feedback reduces the transfer functions
from disturbances to the output

Original (open-loop) line-to-output transfer function:


v(s)
Gvg(s) =
vg(s) d=0
i load = 0

With addition of negative feedback, the line-to-output transfer function


becomes:
v(s) Gvg(s)
=
vg(s) vref = 0 1 + T(s)
i load = 0

Feedback reduces the line-to-output transfer function by a factor of


1
1 + T(s)

If T(s) is large in magnitude, then the line-to-output transfer function


becomes small.

Fundamentals of Power Electronics 13 Chapter 9: Controller design


Closed-loop output impedance

Original (open-loop) output impedance:


v(s)
Z out(s) = –
i load(s) d=0
vg = 0

With addition of negative feedback, the output impedance becomes:

v(s) Z out(s)
=
– i load(s) vref = 0 1 + T(s)
vg = 0

Feedback reduces the output impedance by a factor of


1
1 + T(s)

If T(s) is large in magnitude, then the output impedance is greatly


reduced in magnitude.

Fundamentals of Power Electronics 14 Chapter 9: Controller design


9.2.2. Feedback causes the transfer function from the
reference input to the output to be insensitive to
variations in the gains in the forward path of the loop

Closed-loop transfer function from vref to v(s) is:


v(s) 1 T(s)
=
vref (s) vg = 0 H(s) 1 + T(s)
i load = 0

If the loop gain is large in magnitude, i.e., || T || >> 1, then (1+T) ≈ T and
T/(1+T) ≈ T/T = 1. The transfer function then becomes
v(s)
≈ 1
vref (s) H(s)

which is independent of the gains in the forward path of the loop.


This result applies equally well to dc values:

V = 1 T(0)
≈ 1
Vref H(0) 1 + T(0) H(0)

Fundamentals of Power Electronics 15 Chapter 9: Controller design


9.3. Construction of the important quantities
1/(1+T) and T/(1+T)

Example
80 dB
1 + ωs
z

|| T || T(s) = T0
QdB 1+ s + s 2
1 + ωs
60 dB | T0 |dB Qω p1 ω p1 p2

fp1
40 dB
– 40 dB/decade
20 dB
fz
– 20 dB/decade
0 dB
fc fp2
–20 dB Crossover – 40 dB/decade
frequency

–40 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz

At the crossover frequency fc, || T || = 1 f

Fundamentals of Power Electronics 16 Chapter 9: Controller design


Approximating 1/(1+T) and T/(1+T)

T ≈ 1 for || T || >> 1
1+T T for || T || << 1

1 for || T || >> 1
1 ≈ T(s)
1+T(s) 1 for || T || << 1

Fundamentals of Power Electronics 17 Chapter 9: Controller design


Example: construction of T/(1+T)

80 dB
T ≈ 1 for || T || >> 1
1+T T for || T || << 1
60 dB

fp1 || T ||
40 dB

Crossover
20 dB frequency
fz
– 20 dB/decade fc
0 dB
T fp2
–20 dB 1+T – 40 dB/decade

–40 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 18 Chapter 9: Controller design
Example: analytical expressions for approximate
reference to output transfer function

At frequencies sufficiently less that the crossover frequency, the loop


gain T(s) has large magnitude. The transfer function from the reference
to the output becomes
v(s) T(s)
= 1 ≈ 1
vref (s) H(s) 1 + T(s) H(s)
This is the desired behavior: the output follows the reference
according to the ideal gain 1/H(s). The feedback loop works well at
frequencies where the loop gain T(s) has large magnitude.
At frequencies above the crossover frequency, || T || < 1. The quantity
T/(1+T) then has magnitude approximately equal to 1, and we obtain
v(s) T(s) T(s) Gc(s)Gvd (s)
= 1 ≈ =
vref (s) H(s) 1 + T(s) H(s) VM
This coincides with the open-loop transfer function from the reference
to the output. At frequencies where || T || < 1, the loop has essentially
no effect on the transfer function from the reference to the output.
Fundamentals of Power Electronics 19 Chapter 9: Controller design
Same example: construction of 1/(1+T)

80 dB
1 for || T || >> 1
60 dB | T0 |dB QdB 1 ≈ T(s)
1+T(s) 1 for || T || << 1
fp1
40 dB
|| T ||
– 40 dB/decade
20 dB
fz
– 20 dB/decade
0 dB
+ 20 dB/decade fc fp2
–20 dB
fz Crossover – 40 dB/decade
frequency
+ 40 dB/decade
–40 dB
– | T0 |dB fp1 1
1+T
–60 dB QdB

–80 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 20 Chapter 9: Controller design
Interpretation: how the loop rejects disturbances

Below the crossover frequency: f < fc


and || T || > 1 1 for || T || >> 1
1 ≈ T(s)
Then 1/(1+T) ≈ 1/T, and 1+T(s) 1 for || T || << 1
disturbances are reduced in
magnitude by 1/ || T ||
Above the crossover frequency: f > fc
and || T || < 1
Then 1/(1+T) ≈ 1, and the
feedback loop has essentially
no effect on disturbances

Fundamentals of Power Electronics 21 Chapter 9: Controller design


Terminology: open-loop vs. closed-loop

Original transfer functions, before introduction of feedback (“open-loop


transfer functions”):

Gvd(s) Gvg(s) Z out(s)

Upon introduction of feedback, these transfer functions become


(“closed-loop transfer functions”):

1 T(s) Gvg(s) Z out(s)


H(s) 1 + T(s) 1 + T(s) 1 + T(s)

The loop gain:


T(s)

Fundamentals of Power Electronics 22 Chapter 9: Controller design


9.4. Stability

Even though the original open-loop system is stable, the closed-loop


transfer functions can be unstable and contain right half-plane poles. Even
when the closed-loop system is stable, the transient response can exhibit
undesirable ringing and overshoot, due to the high Q -factor of the closed-
loop poles in the vicinity of the crossover frequency.
When feedback destabilizes the system, the denominator (1+T(s)) terms in
the closed-loop transfer functions contain roots in the right half-plane (i.e.,
with positive real parts). If T(s) is a rational fraction of the form N(s) / D(s),
where N(s) and D(s) are polynomials, then we can write
N(s)
T(s) D(s) N(s) • Could evaluate stability by
= = evaluating N(s) + D(s), then
1 + T(s) N(s) N(s) + D(s)
1+
D(s) factoring to evaluate roots.
1 1 D(s) This is a lot of work, and is
= =
1 + T(s) N(s) N(s) + D(s) not very illuminating.
1+
D(s)

Fundamentals of Power Electronics 23 Chapter 9: Controller design


Determination of stability directly from T(s)

• Nyquist stability theorem: general result.


• A special case of the Nyquist stability theorem: the phase margin test
Allows determination of closed-loop stability (i.e., whether 1/(1+T(s))
contains RHP poles) directly from the magnitude and phase of T(s).
A good design tool: yields insight into how T(s) should be shaped, to
obtain good performance in transfer functions containing 1/(1+T(s))
terms.

Fundamentals of Power Electronics 24 Chapter 9: Controller design


9.4.1. The phase margin test

A test on T(s), to determine whether 1/(1+T(s)) contains RHP poles.


The crossover frequency fc is defined as the frequency where
|| T(j2πfc) || = 1 ⇒ 0dB

The phase margin ϕm is determined from the phase of T(s) at fc , as


follows:
ϕm = 180˚ + ∠T(j2πfc)

If there is exactly one crossover frequency, and if T(s) contains no


RHP poles, then
the quantities T(s)/(1+T(s)) and 1/(1+T(s)) contain no RHP poles
whenever the phase margin ϕm is positive.

Fundamentals of Power Electronics 25 Chapter 9: Controller design


Example: a loop gain leading to
a stable closed-loop system
60 dB
|| T || ∠T
|| T ||
40 dB
fp1
Crossover
20 dB fz frequency
fc
∠T
0 dB 0˚

–20 dB –90˚
ϕm
–40 dB –180˚

–270˚

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz


f
∠T(j2πfc) = – 112˚
ϕm = 180˚ – 112˚ = + 68˚

Fundamentals of Power Electronics 26 Chapter 9: Controller design


Example: a loop gain leading to
an unstable closed-loop system
60 dB
|| T || ∠T
|| T ||
40 dB
fp1
Crossover
20 dB frequency

∠T fp2 fc
0 dB 0˚

–20 dB –90˚

–40 dB –180˚
ϕm (< 0)
–270˚

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz


f
∠T(j2πfc) = – 230˚
ϕm = 180˚ – 230˚ = – 50˚

Fundamentals of Power Electronics 27 Chapter 9: Controller design


9.4.2. The relation between phase margin
and closed-loop damping factor

How much phase margin is required?


A small positive phase margin leads to a stable closed-loop system
having complex poles near the crossover frequency with high Q. The
transient response exhibits overshoot and ringing.
Increasing the phase margin reduces the Q. Obtaining real poles, with
no overshoot and ringing, requires a large phase margin.
The relation between phase margin and closed-loop Q is quantified in
this section.

Fundamentals of Power Electronics 28 Chapter 9: Controller design


A simple second-order system

40 dB || T || f0
|| T || ∠T
f
20 dB
– 20 dB/decade
f0
Consider the 0 dB
case where T(s) f2 f0 f2
–20 dB f2
can be well-
approximated in –40 dB 0˚
– 40 dB/decade
the vicinity of the ∠T – 90˚
f2 /10
–90˚
crossover f2
ϕm
frequency as –180˚
10f2
T(s) = 1
s 1 + ωs
–270˚
ω0 2 f

Fundamentals of Power Electronics 29 Chapter 9: Controller design


Closed-loop response

If
T(s) = 1
s 1 + ωs
ω0 2

Then
T(s) 1 1
= =
1 + T(s) 1+ 1 1 + s + s2
T(s) ω 0 ω 0ω 2
or,
T(s) 1
=
1 + T(s) 1 + s + ωs
2

Qωc c

where
ω ω0
ωc = ω0ω2 = 2π fc Q = ω0 = ω2
c

Fundamentals of Power Electronics 30 Chapter 9: Controller design


Low-Q case

ω ω0
Q = ω0 =
c ω2 low-Q approximation: Q ωc = ω0 ωc
= ω2
Q
40 dB || T || f0
f
20 dB
– 20 dB/decade
fc = f0 f2
0 dB
T f0 Q = f0 / fc
1+T
–20 dB
f2
–40 dB f0 f2 – 40 dB/decade
f2

f
Fundamentals of Power Electronics 31 Chapter 9: Controller design
High-Q case

ω ω0
ωc = ω0ω2 = 2π fc Q = ω0 = ω2
c

60 dB f0
|| T || f
40 dB
– 20 dB/decade
20 dB f2
Q = f0 /fc
0 dB
T fc = f0 f2 f0
1+T
–20 dB
f0 f2 – 40 dB/decade
f2
–40 dB
f
Fundamentals of Power Electronics 32 Chapter 9: Controller design
Q vs. ϕm

Solve for exact crossover frequency, evaluate phase margin, express


as function of ϕm. Result is:

cos ϕ m
Q=
sin ϕ m

1+ 1 + 4Q 4
ϕ m = tan -1
2Q 4

Fundamentals of Power Electronics 33 Chapter 9: Controller design


Q vs. ϕm
20 dB
Q
15 dB

10 dB

5 dB

0 dB Q = 1 ⇒ 0 dB
ϕm = 52˚
–5 dB
Q = 0.5 ⇒ –6 dB

–10 dB ϕm = 76˚

–15 dB

–20 dB
0° 10° 20° 30° 40° 50° 60° 70° 80° 90°
ϕm
Fundamentals of Power Electronics 34 Chapter 9: Controller design
9.4.3. Transient response vs. damping factor

Unit-step response of second-order system T(s)/(1+T(s))

2Q e -ωct/2Q 4Q 2 – 1
v(t) = 1 + sin ωc t + tan -1 4Q 2 – 1 Q > 0.5
4Q 2 – 1 2Q

ω ω Q < 0.5
v(t) = 1 – ω –2ω e –ω1t – ω –1ω e –ω2t
2 1 1 2

ωc
ω 1, ω 2 = 1± 1 – 4Q 2
2Q

For Q > 0.5 , the peak value is


4Q 2 – 1
peak v(t) = 1 + e – π /

Fundamentals of Power Electronics 35 Chapter 9: Controller design


Transient response vs. damping factor

2
Q = 50
v(t) Q = 10

Q=4
1.5
Q=2

Q=1
1
Q = 0.75
Q = 0.5
Q = 0.3
Q = 0.2
0.5
Q = 0.1

Q = 0.05
Q = 0.01
0
0 5 10 15
ωc t, radians

Fundamentals of Power Electronics 36 Chapter 9: Controller design


9.5. Regulator design

Typical specifications:
• Effect of load current variations on output voltage regulation
This is a limit on the maximum allowable output impedance
• Effect of input voltage variations on the output voltage
regulation
This limits the maximum allowable line-to-output transfer
function
• Transient response time
This requires a sufficiently high crossover frequency
• Overshoot and ringing
An adequate phase margin must be obtained
The regulator design problem: add compensator network Gc(s) to
modify T(s) such that all specifications are met.

Fundamentals of Power Electronics 37 Chapter 9: Controller design


9.5.1. Lead (PD) compensator

1 + ωs fp
z
Gc(s) = Gc0 Gc0
1 + ωs fz fp
p || Gc || Gc0
fϕmax
fz
= fz fp
Improves phase
margin
fp /10 10fz
+ 45˚/decade
fz /10
0˚ – 45˚/decade
∠ Gc

Fundamentals of Power Electronics 38 Chapter 9: Controller design


Lead compensator: maximum phase lead

Maximum phase occurs at


Maximum 90˚
phase lead fϕmax = fz fp
75˚

60˚
fp fz

45˚
fz fp
∠ Gc( fϕmax) = tan -1
2
30˚

15˚
fp 1 + sin θ
=
fz 1 – sin θ

1 10 100 1000 θ =-Gc( fϕmax)

fp / fz

To obtain the maximum improvement in phase margin, we should design our compensator so that the frequency fϕmax coincides with the loop gain crossover frequency fc

Fundamentals of Power Electronics 39 Chapter 9: Controller design


Lead compensator design

To optimally obtain a compensator phase lead of θ at frequency fc, the


pole and zero frequencies should be chosen as follows:

1 – sin θ fp
fz = fc Gc0
fz fp
1 + sin θ || Gc || Gc0
fϕmax
1 + sin θ fz
= fz fp
fp = fc
1 – sin θ
fp /10 10fz
If it is desired that the magnitude + 45˚/decade
of the compensator gain at fc be fz /10
0˚ – 45˚/decade
unity, then Gc0 should be chosen ∠ Gc
as
fz f
Gc0 =
fp

Fundamentals of Power Electronics 40 Chapter 9: Controller design


Example: lead compensation

60 dB
T0
40 dB || T || T0 Gc0 Original gain
|| T || ∠T
20 dB
Compensated gain f0

0 dB fz
fc
–20 dB fp
Compensated phase asymptotes

–40 dB 0˚
∠T
Original phase asymptotes –90˚

ϕm
–180˚

–270˚
f

Fundamentals of Power Electronics 41 Chapter 9: Controller design


9.5.2. Lag (PI) compensation

|| Gc ||
ω
Gc(s) = Gc∞ 1 + sL
– 20 dB /decade Gc∞
Improves low- fL
frequency loop gain
and regulation
10fL 0˚
∠ Gc
+ 45˚/decade
– 90˚
fL /10

Fundamentals of Power Electronics 42 Chapter 9: Controller design


Example: lag compensation

original
|| T ||
(uncompensated) 40 dB
loop gain is Gc∞Tu0
Tu0 20 dB fL f0
Tu(s) =
1 + ωs || Tu || Tu0 fc
0 0 dB
f0
compensator: –20 dB 90˚
ω
Gc(s) = Gc∞ 1 + sL ∠ Tu
–40 dB 0˚
10fL
Design strategy:
–90˚
choose ∠T 10f0 ϕm
Gc∞ to obtain desired –180˚

crossover frequency
ωL sufficiently low to 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz

maintain adequate f
phase margin
Fundamentals of Power Electronics 43 Chapter 9: Controller design
Example, continued

Construction of 1/(1+T), lag compensator example:

|| T ||
40 dB
Gc∞Tu0
20 dB fL f0
fc
0 dB

–20 dB fL f0
1 1
1+T G c∞ T u0
–40 dB

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz


f

Fundamentals of Power Electronics 44 Chapter 9: Controller design


9.5.3. Combined (PID) compensator

ω
1 + sL 1 + ωs
z
Gc(s) = Gcm
1 + ωs 1 + ωs
40 dB p1 p2

|| Gc || ∠ Gc
|| Gc || fp2
20 dB fp1
Gcm fc
0 dB
fL fz

–20 dB 10 fz f /10 90˚


10 fL
45˚/decade p2

–40 dB 0˚
fp1 /10
– 90˚/decade
– 90˚ 90˚/decade
fz /10 10 fp1 –90˚
∠ Gc fL /10
–180˚

f
Fundamentals of Power Electronics 45 Chapter 9: Controller design
9.5.4. Design example

L
50 µH
+
iload
vg(t) + C R
v(t)
28 V – 500 µF 3Ω
Sensor
– H(s) gain
fs = 100 kHz
Transistor Error
gate driver signal
δ Pulse-width vc G (s) ve –+ Hv
modulator c

VM = 4 V Compensator vref
5V

Fundamentals of Power Electronics 46 Chapter 9: Controller design


Quiescent operating point

Input voltage Vg = 28V


Output V = 15V, Iload = 5A, R = 3Ω
Quiescent duty cycle D = 15/28 = 0.536
Reference voltage Vref = 5V
Quiescent value of control voltage Vc = DVM = 2.14V
Gain H(s) H = Vref/V = 5/15 = 1/3

Fundamentals of Power Electronics 47 Chapter 9: Controller design


Small-signal model

V d
D2 1:D
L

+

+

vg(s) + V d C v(s) iload (s)


– R
R

Error d(s)
signal
vref (= 0) + ve (s) vc (s) 1
– Gc(s) VM
T(s)
Compensator VM = 4 V

H(s) v(s)
H(s)

H=1
3

Fundamentals of Power Electronics 48 Chapter 9: Controller design


Open-loop control-to-output transfer function Gvd(s)

60 dBV
|| Gvd || ∠ Gvd
40 dBV || Gvd || Q0 = 9.5 ⇒ 19.5 dB
Gd0 = 28 V ⇒ 29 dBV
Gvd(s) = V 1
f0
D 1 + s L + s 2LC 20 dBV
R ∠ Gvd 10 –1/2Q 0 f0 = 900 Hz
0 dBV 0˚
standard form:
–20 dBV –90˚
Gvd(s) = Gd0 1
1+ s + s 2
–40 dBV –180˚
Q 0 ω0 ω0 10 1/2Q 0
f0 = 1.1 kHz
–270˚
salient features:

Gd0 = V = 28V 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz


D f
ω0 1
f0 = = = 1kHz
2π 2π LC
Q0 = R C = 9.5 ⇒ 19.5dB
L

Fundamentals of Power Electronics 49 Chapter 9: Controller design


Open-loop line-to-output transfer function
and output impedance

Gvg(s) = D 1
1 + s L + s 2LC
R

—same poles as control-to-output transfer function


standard form:

Gvg(s) = Gg0 1
1+ s + s 2

Q 0 ω0 ω0

Output impedance:

Z out(s) = R || 1 || sL = sL
sC 1 + s L + s 2LC
R

Fundamentals of Power Electronics 50 Chapter 9: Controller design


System block diagram

T(s) = Gc(s) 1 G (s) H(s)


vd
VM
iload (s) Load current
variation
Gc(s) H(s) V 1
T(s) =
VM D 1+ s + s 2
Zout (s)
Q 0 ω0 ω0 vg(s)
Gvg (s)
ac line
variation

VM = 4 V –
vref ( = 0 ) + ve(s) vc(s) +
1 d(s) v(s)
– Gc(s) VM Gvd (s)
Duty cycle +
variation
Converter power stage
T(s)
H=1
3
H(s)

Fundamentals of Power Electronics 51 Chapter 9: Controller design


Uncompensated loop gain (with Gc = 1)

40 dB
|| Tu || ∠ Tu
20 dB Q0 = 9.5 ⇒ 19.5 dB
|| Tu || Tu0 2.33 ⇒ 7.4 dB

0 dB f0
1 kHz
–20 dB
With Gc = 1, the – 1
10 2Q f0 = 900 Hz
– 40 dB/decade

loop gain is –40 dB 0˚
∠ Tu

Tu(s) = Tu0 1 –90˚

1+ s + s 2

Q 0 ω0 ω0 –180˚
1
10 2Q f0 = 1.1 kHz
Tu0 = H V = 2.33 ⇒ 7.4dB –270˚
D VM 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f

fc = 1.8 kHz, ϕm = 5˚

Fundamentals of Power Electronics 52 Chapter 9: Controller design


Lead compensator design

• Obtain a crossover frequency of 5 kHz, with phase margin of 52˚


• Tu has phase of approximately – 180˚ at 5 kHz, hence lead (PD)
compensator is needed to increase phase margin.
• Lead compensator should have phase of + 52˚ at 5 kHz
• Tu has magnitude of – 20.6 dB at 5 kHz
• Lead compensator gain should have magnitude of + 20.6 dB at 5 kHz
• Lead compensator pole and zero frequencies should be
1 – sin (52°)
fz = (5kHz) = 1.7kHz
1 + sin (52°)
1 + sin (52°)
fp = (5kHz) = 14.5kHz
1 – sin (52°)
2
fc 1 fz
• Compensator dc gain should be G c0 = = 3.7 ⇒ 11.3dB
f0 Tu0 fp

Fundamentals of Power Electronics 53 Chapter 9: Controller design


Lead compensator Bode plot

40 dB
|| Gc || fp ∠ Gc
Gc0
fz fp
20 dB || Gc || Gc0
fc
0 dB
fz = fz fp

–20 dB fp /10 10fz 90˚


fz /10

–40 dB 0˚
∠ Gc
–90˚

–180˚

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz


f
Fundamentals of Power Electronics 54 Chapter 9: Controller design
Loop gain, with lead compensator

1 + ωs
z
T(s) = Tu0 Gc0
1 + ωs s + s 2
1+ ω0
p Q 0 ω0
40 dB
|| T || Q0 = 9.5 ⇒ 19.5 dB
∠T
|| T || T0 = 8.6 ⇒ 18.7 dB
20 dB
f0
0 dB 1 kHz fz
1.7 kHz fc
–20 dB 5 kHz fp
900 Hz 14 kHz

–40 dB 0˚
∠T 170 Hz
–90˚
1.4 kHz 17 kHz
ϕm=52˚
1.1 kHz –180˚

–270˚
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 55 Chapter 9: Controller design
1/(1+T), with lead compensator

40 dB
Q0 = 9.5 ⇒ 19.5 dB
• need more
20 dB
|| T || T0 = 8.6 ⇒ 18.7 dB low-frequency
f0 loop gain
0 dB fz
1 fc • hence, add
1+T 1/T0 = 0.12 ⇒ – 18.7 dB inverted zero
–20 dB fp
Q0 (PID controller)
–40 dB

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz


f

Fundamentals of Power Electronics 56 Chapter 9: Controller design


Improved compensator (PID)

ω
1 + ωs 1 + sL
z
Gc(s) = Gcm
1 + ωs
40 dB p

|| Gc || || Gc || ∠ Gc
20 dB fp
fc • add inverted
Gcm
0 dB
fL fz zero to PD
compensator,
–20 dB
10fL 10fz 90˚ without
45˚/decade – 45˚/dec changing dc
–40 dB 0˚ gain or corner
fp /10
∠ Gc – 90˚ 90˚/decade frequencies
fz /10 –90˚
fL /10
• choose fL to be
–180˚
fc/10, so that
phase margin
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz is unchanged
f
Fundamentals of Power Electronics 57 Chapter 9: Controller design
T(s) and 1/(1+T(s)), with PID compensator

60 dB

40 dB || T ||
Q0
20 dB
fL f0
0 dB fz
fc
–20 dB fp
1 Q0
–40 dB 1+T

–60 dB

–80 dB
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
f
Fundamentals of Power Electronics 58 Chapter 9: Controller design
Line-to-output transfer function

v 20 dB
vg Q0
0 dB Gvg(0) = D
Open-loop || Gvg || f0
–20 dB D
T u0G cm
fL fz
–40 dB
fc
20 dB/decade
–60 dB

G vg – 40 dB/decade
–80 dB Closed-loop
1+T
–100 dB

1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz


f

Fundamentals of Power Electronics 59 Chapter 9: Controller design


9.6. Measurement of loop gains

Block 1 Block 2
A
Z1(s)
+

vref (s) +– ve (s) G2 (s) vx (s) = v(s)


G1 (s) ve (s) + vx (s) Z2(s)

T(s)

H(s)

Objective: experimentally determine loop gain T(s), by making


measurements at point A
Correct result is
Z 2(s)
T(s) = G1(s) G2(s) H(s)
Z 1(s) + Z 2(s)

Fundamentals of Power Electronics 60 Chapter 9: Controller design


Conventional approach: break loop,
measure T(s) as conventional transfer function
VCC
Block 1 Block 2
dc bias
Z1(s)
0 – +

vref (s) +– ve (s) G2 (s)vx (s) = v(s)


G1 (s)ve (s) + vy (s) vx (s) Z2(s)

vz
+ –

Tm (s)

H(s)

measured gain is
vy(s)
Tm(s) = Tm(s) = G1(s) G2(s) H(s)
vx(s) vref = 0
vg = 0

Fundamentals of Power Electronics 61 Chapter 9: Controller design


Measured vs. actual loop gain

Actual loop gain:


Z 2(s)
T(s) = G1(s) G2(s) H(s)
Z 1(s) + Z 2(s)
Measured loop gain:
Tm(s) = G1(s) G2(s) H(s)

Express Tm as function of T:
Z 1(s)
Tm(s) = T(s) 1 +
Z 2(s)

Tm(s) ≈ T(s) provided that Z 2 >> Z 1

Fundamentals of Power Electronics 62 Chapter 9: Controller design


Discussion

• Breaking the loop disrupts the loading of block 2 on block 1.


A suitable injection point must be found, where loading is not
significant.
• Breaking the loop disrupts the dc biasing and quiescent operating
point.
A potentiometer must be used, to correctly bias the input to block 2.
In the common case where the dc loop gain is large, it is very
difficult to correctly set the dc bias.
• It would be desirable to avoid breaking the loop, such that the biasing
circuits of the system itself set the quiescent operating point.

Fundamentals of Power Electronics 63 Chapter 9: Controller design


9.6.1. Voltage injection

Block 1 – vz + Block 2
i(s)
Z1(s) Zs(s)
0 – +

vref (s) +– ve (s) G2 (s) vx (s) = v(s)


G1 (s) ve (s) + vy (s) vx (s) Z2(s)

+ –

Tv (s)

H(s)

• Ac injection source vz is connected between blocks 1 and 2


• Dc bias is determined by biasing circuits of the system itself
• Injection source does modify loading of block 2 on block 1

Fundamentals of Power Electronics 64 Chapter 9: Controller design


Voltage injection: measured transfer function Tv(s)

Block 1 – vz + Block 2
i(s)
Network analyzer 0
Z1(s)

Zs(s)
+
measures vref (s) +– ve (s) G2 (s) vx (s) = v(s)
G1 (s) ve (s) + vy (s) vx (s) Z2(s)

vy(s)
Tv(s) = + –
vx(s) vref = 0
vg = 0 Tv (s)

H(s)
Solve block diagram:
ve(s) = – H(s) G2(s) vx(s)

– vy(s) = G1(s) ve(s) – i(s) Z 1(s) Substitute:


Z 1(s)
Hence vy(s) = vx(s) G1(s) G2(s) H(s) +
Z 2(s)
– vy(s) = – vx(s) G2(s) H(s) G1(s) – i(s) Z 1(s)
which leads to the measured gain
with Z (s)
vx(s) Tv(s) = G1(s) G2(s) H(s) + 1
i(s) = Z 2(s)
Z 2(s)

Fundamentals of Power Electronics 65 Chapter 9: Controller design


Comparison of Tv(s) with T(s)

Actual loop gain is Gain measured via voltage


injection:
Z 2(s) Z (s)
T(s) = G1(s) G2(s) H(s) Tv(s) = G1(s) G2(s) H(s) + 1
Z 1(s) + Z 2(s) Z 2(s)

Express Tv(s) in terms of T(s):


Z 1(s) Z (s)
Tv(s) = T(s) 1 + + 1
Z 2(s) Z 2(s)

Condition for accurate measurement:


Tv(s) ≈ T(s) provided (i) Z 1(s) << Z 2(s) , and

Z 1(s)
(ii) T(s) >>
Z 2(s)

Fundamentals of Power Electronics 66 Chapter 9: Controller design


Example: voltage injection

Block 1 Block 2
vz
50 Ω Z 1(s) = 50Ω

+

– + Z 2(s) = 500Ω
Z 1(s)
+ = 0.1 ⇒ – 20dB
– vy (s) vx (s) 500 Ω Z 2(s)
Z 1(s)
+ – 1+ = 1.1 ⇒ 0.83dB
Z 2(s)

suppose actual T(s) = 10 4


1+ s 1+ s
2π 10Hz 2π 100kHz

Fundamentals of Power Electronics 67 Chapter 9: Controller design


Example: measured Tv(s) and actual T(s)

100 dB
Z 1(s) Z (s)
Tv(s) = T(s) 1 + + 1
80 dB Z 2(s) Z 2(s)

60 dB || Tv ||
|| T ||
40 dB

20 dB

0 dB Z1
⇒ – 20 dB || Tv ||
Z2
–20 dB

|| T ||
–40 dB
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
f

Fundamentals of Power Electronics 68 Chapter 9: Controller design


9.6.2. Current injection

i y(s)
Ti(s) =
i x(s) vref = 0
vg = 0

Block 1 Block 2
iy (s) ix (s)
Z1(s)
0 iz (s)
vref (s) +– ve (s) G2 (s) vx (s) = v(s)
G1 (s) ve (s) + Z2(s)
– Zs(s)

Ti (s)

H(s)

Fundamentals of Power Electronics 69 Chapter 9: Controller design


Current injection

It can be shown that Injection source impedance Zs


is irrelevant. We could inject
Z 2(s) Z (s) using a Thevenin-equivalent
Ti(s) = T(s) 1 + + 2 voltage source:
Z 1(s) Z 1(s)

iy (s) iz (s) ix (s)


Conditions for obtaining accurate Cb
measurement:
Rs
(i) Z 2(s) << Z 1(s) , and

(ii) T(s) >>


Z 2(s) vz (s)
Z 1(s)

Fundamentals of Power Electronics 70 Chapter 9: Controller design


9.6.3. Measurement of unstable systems

• Injection source impedance Zs • Original (unstable) loop gain is


does not affect measurement measured (not including Zs ),
while circuit operates stabily
• Increasing Zs reduces loop
gain of circuit, tending to
stabilize system
– vz +
Block 1 Block 2
Rext
Z1(s) Zs(s)
0 – +

vref (s) Lext


+– ve (s) G2 (s) vx (s) = v(s)
G1 (s) ve (s) + vy (s) vx (s) Z2(s)

+ –

Tv (s)

H(s)

Fundamentals of Power Electronics 71 Chapter 9: Controller design


9.7. Summary of key points

1. Negative feedback causes the system output to closely follow the


reference input, according to the gain 1/H(s). The influence on the
output of disturbances and variation of gains in the forward path is
reduced.
2. The loop gain T(s) is equal to the products of the gains in the
forward and feedback paths. The loop gain is a measure of how well
the feedback system works: a large loop gain leads to better
regulation of the output. The crossover frequency fc is the frequency
at which the loop gain T has unity magnitude, and is a measure of
the bandwidth of the control system.

Fundamentals of Power Electronics 72 Chapter 9: Controller design


Summary of key points

3. The introduction of feedback causes the transfer functions from


disturbances to the output to be multiplied by the factor 1/(1+T(s)). At
frequencies where T is large in magnitude (i.e., below the crossover
frequency), this factor is approximately equal to 1/T(s). Hence, the
influence of low-frequency disturbances on the output is reduced by a
factor of 1/T(s). At frequencies where T is small in magnitude (i.e.,
above the crossover frequency), the factor is approximately equal to 1.
The feedback loop then has no effect. Closed-loop disturbance-to-
output transfer functions, such as the line-to-output transfer function or
the output impedance, can easily be constructed using the algebra-on-
the-graph method.
4. Stability can be assessed using the phase margin test. The phase of T
is evaluated at the crossover frequency, and the stability of the
important closed-loop quantities T/(1+T) and 1/(1+T) is then deduced.
Inadequate phase margin leads to ringing and overshoot in the system
transient response, and peaking in the closed-loop transfer functions.

Fundamentals of Power Electronics 73 Chapter 9: Controller design


Summary of key points

5. Compensators are added in the forward paths of feedback loops to


shape the loop gain, such that desired performance is obtained.
Lead compensators, or PD controllers, are added to improve the
phase margin and extend the control system bandwidth. PI
controllers are used to increase the low-frequency loop gain, to
improve the rejection of low-frequency disturbances and reduce the
steady-state error.
6. Loop gains can be experimentally measured by use of voltage or
current injection. This approach avoids the problem of establishing
the correct quiescent operating conditions in the system, a common
difficulty in systems having a large dc loop gain. An injection point
must be found where interstage loading is not significant. Unstable
loop gains can also be measured.

Fundamentals of Power Electronics 74 Chapter 9: Controller design

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