Design Considerations for High

Step-Down Ratio Buck Converters

Ramesh Khanna – National Semiconductor, Richardson, TX

&
Satish Dhawan – Yale University, CT, USA
Buck converter

IL1
Q1 Vm 10A In Non-Synchronous buck converter
L1 Q2 is replaced with diode
12V Q2 Co 1.2V

Duty cycle D = 0.1

Q1
Vm
on on on
Vin = 12V Q1 on & Q2 off Q1 off & Q2 on

IL1
VL  Vin  Vout
VL  Vout
T
D  on Ton
Vo Ts D '  (1  D )  (1  )
Ts

Vin  Vo (Vin  Vout )Ton  (VoutToff )

VL DTs
(Vin  Vout ) DTs  Vout (1  D)Ts
Vout
Vo D 'TS D
volt  sec balance Vin DC gain

Vin = 12V

2
Continuous vs Discontinuous mode of
Operation
When Q1 is turned on Input source charges the inductor and supplies the Output load
When Q1 turns-off Voltage across the inductor changes polarity and forward biases
the sync diode, Q2 is allowed to turn-on. Energy stored in the inductor is supplies to
the load.

3
Buck converter in Discontinuous mode

4
Specifications / Design considerations

Min Max Tolerance Req'd

Vin 3.3 15

Vout 1.8 +/-3%

Output Ripple 50mV

Efficiency 85%

Transient 100A/usec

Ambient Temp 55C

Size HxLxW

Enable x

Tracking x

OV Protection x

Current Limit x

Cost Target

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5
Need for Efficiency Improvement

Efficiency Improvement is
critical for any designs.
In order to maintain same heat
dissipation improving
efficiency from
85% to 91.9% doubles the
output power.
Output power delivered doubles from • Less issues with regards to
40W to 80W for fixed power dissipation thermal management
(loss) of 7W. If the converter efficiency • Improved reliability.
increases from 85% to 92%

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6
Small Signal Model of Buck Converter
• PWM Switch
V1 (t )
I1 I2
Vin
+ +  V1 Ts  Vin 
rc
Vin V1 V2 RL Vo
PWM Co V2 (t )
- switch -

 V2 Ts  d  [ V1 (t ) ]

V2  dependent variable d
i1 (t ) d'
I1  dependent variable
 i1 Ts  i2  d
V1  independent variable
I 2  independent variable i2 (t )
 i2 Ts  d   i2   d '  i 2 
 i2 Ts  (d  d ' )  i2 

Express dependent sources  V2 (t )  and  I1 (t )  as a function of

independent sources  V1 (t )  ,  I 2 (t )  and d duty cycle

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7
PWM switch model
• Next step we perturb and linearize the equations, where we
assume average voltage consists of constant “dc”
component and small signal “ac” variation around the dc
component.

 v1 (t ) Ts  V1  v1 (t )

 i1 (t )  I1  i1 (t ) d (t )  D  d(t )

D(V1  v1 (t ))
 v2 (t ) Ts  V2  v2 (t ) d '  D '  d(t ) V1 d
-+
 i2 (t )  I 2  i2 (t )
+ V2  v2 (t )
 v 2 (t ) Ts  v1 (t ) Ts d (t )
-
V2  v2 (t )  ( D  d(t ))  (V1  v1 (t ))

V2  v2 (t )  D(V1  v1 (t ))  d(t )  V1

I1  i1 (t )
 i1 (t ) Ts  d   i2 (t ) 

I1   i1 (t )  ( I 2 i2 (t ))  ( D  d(t ))

I 2 dˆ
I1   i1 (t )  D  ( I 2  i2 (t ))  I 2  d
D( I 2 
8
PWM switch model
• Combining the two sections, we have the small signal mode
of PWM switch
I1   i1 (t )  D  ( I 2  i2 (t ))  I 2  d V2  v2 (t )  D(V1  v1 (t ))  d(t )  V1

D(V1  v1 (t ))
I1  i1 (t ) V1 d
V1  v1 (t )

-+

I 2 dˆ + V2  v2 (t )

-
D( I 2  i2 (t ))

V1 d
D ( I 2  i2 (t ))
I1  i1 (t )
V1  v1 (t )

1: D Active
-+ Common

I 2 dˆ V2  v2 (t )

Passive

9
Incorporating PWM switch in Buck Circuit
• Small signal model of Buck converter - DC Analysis
Vap d
Ia a D c Ic ro LF For DC Analysis
1: D
-+ L = Short circuit
CF C = Open circuit
Vin I c dˆ
VCP RL V
o
d  0
Vap

rC

Vap  Vin
Vcp  DVap  DVin
Vcp  Vo
Vo  DVin
Vo
D
Vin

10
Incorporating PWM switch in Buck Circuit
• Small signal model of Buck converter – AC Analysis
• For AC analysis we short the input source
Vap d
Ia a D c Ic ro LF
1: D
-+

CF
I c dˆ
vcp RL v
o
vap

rC

RL ( sCo rC  1)
Zx  Z L  ro  sL
(1  sCo ( rC  RL ))
vo Z x ( s)

 vcp
vcp Z x ( s)  Z L ( s) ( s )  Vin
d
v0 vcp v
( s)  (s)  o (s)
d d v cp Control to output is the most important transfer function as it is necessary for the design of stable
feedback loop.

11
Incorporating PWM switch in Buck Circuit
• Small signal model of Buck converter – AC Analysis Alternate Approach
• For AC analysis we short the input source

Vap d
Ia a D c Ic ro LF
1: D
-+

CF
I c dˆ
vcp RL v
o
vap

rC

Write differential equation for Voltage across inductor Lf RL

Den 
R
Write differential equation for Current thru the output capacitor Cf (1  L )
rC
diL  V
L  iL (ro  Den)  Den c  Vap d
dt rC
dv  Den 1 1
C  iL ( )  vc ( 2  )
dt rC rC Den rC

12
Incorporating PWM switch in Buck Circuit
• Write the two equations in matrix form
• Solve matrix using cramers rule to obtain control to output transfer function.

 diL   ro  Den  Den 

 V ap 
 dt   LF rC LF  i
    L    L  d
 dv   Den 1 1 1  vC   F  RL
   (  )  0 
Den 
 dt   CF RL CF rC 2 Den rC  R
(1  L )
rC

sX ( s )  AX ( s )  Bd ( s )
sIX ( s )  AX ( s)  Bd ( s )
( sI  A) x( s )  Bd ( s)
x( s )
( sI  A) B
d (s)

 ro  Den Den 

 s  ( )  i (s)
LF rC LF
   L   V in  vo
  ( )
  1 1    d ( s)    L 
  r Den r     v ( s)   F  vo ( s ) 
d
 
Den
s C
2
C
   o   0  
 CF rC  CF    d ( s)  d (s) 
   


13
MOSFET Selecton

• MOSFET – switching model

D

Ld Model highlights the MOSFET

Cgd
critical parameters
G Cds
CGD  CRSS Miller Capacitor
Rg

Cgs CGS  C ISS CRSS

Ls CDS  COSS  C RSS

S
Junction capacitors of semiconductor
Coss

devices are non-linear

C 1
Vc
V0
C  f (Vc )  CO VC

Co At Vc there is twice the charge that a linear

capacitor of value Co would have at Vo

Vds spec Vds spec

Vo C gd (Vin)  2Crss _ spec Coss (Vin )  2Coss _ spec
Vc Vin Vin

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14
Critical MOSFET parameters
• Rg – MOSFET gate resistor along with gate driver resistance are extremely critical for
high speed applications.
• MOSFET gate resistance is temperature dependent thus increases with temperature -
vendors provide curves Rdson vs temperature for better approximation.

dI D
g fs  Forward Transconductance and has
dVGS
units of (mho) Siemens

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15
Non-Linear junction capacitor in MOSFET

CGD  CRSS Miller Capacitor

CGS  C ISS CRSS

Coss

CDS  COSS  CRSS

C 1
Vc

Co Junction capacitors of semiconductor

devices are non-linear
V0
Vo
Vc C  f (Vc )  CO VC

At Vc there is twice the charge that a linear

vc
V0 capacitor of value Co would have at Vo
Q   C0 dVc
0
Vc
vc
1 Vds spec Vds spec
Q  C0 Vo  dVc C gd (Vin)  2Crss _ spec Coss (Vin )  2Coss _ spec
Vc Vin Vin
0

Q  C0 Vo  2 Vc  2 0  dQc
C
dVc
Q  2Co Vo Vc

Vc  Vo
Q  2C0Vo

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16
MOSFET Switching Behavior : Turn-on
1. Turn-On Delay –
• Input capacitor is
charged from 0V to Vth.

2. Linear Operation
• Vg increases from Vth
to Miller Capacitor
• Mosfet is carrying the
entire Inductor
current.

MOSFET Turn-On 4 3. Vgs is Steady

stages • Driver current

Reduce transition time
during stage 2 to minimize
switching losses
Critical Gate Drivers
ability to source current
diverted to discharge
Cgd
• Drain Voltage falls
4. Vgs increased from
Vmiller to Vfinal
• Mosfet fully enhanced
• Cgs and Cgd charged
• Rds_on reduced.

17
Mosfet Switching Behavior : Turn-Off
1. Turn-off Delay
• Ciss is discharged from initial
value to Miller Plateau.

2. Vds rises
• Gate current is charging
Cgd
• Gate in its Miller Plateau

3. Mosfet in Linear mode

• Vg falls from Miller to Vth
MOSFET Turn-Off 4 stages
• Cgs capacitor is started to
Reduce transition time discharged
during stage 3 to minimize 4. Turn-off Stage
switching losses • Vgs is further decreased with
Critical Gate drivers ability to current coming out of Cgs
capacitor.
sink current.

18
Diode Reverse recovery

VD
• Current can flow from
cathode to anode until
ID
diode turns off.
• This can produce
– High peak currents VD

– High dissipation:
• In the diode
• In other circuit
components
ID

19
High Side Fet Losses

• Conduction and Switching Losses

Pconduction _ HS Iqrms _ HS 2 Rdson  I 02 Rdson D
Switch conduction losses

Psw  (1 2)Vin f sw{[ I q min t2 ]  [ I q max t3 ]} Switching losses during turn-on and turn-off

Psw _ drv  Vdrv f swQg Driver losses

Pcos s  0.5Coss f swVin 2 Capacitor drain-source losses

PQrr  QrrVin f sw Reverse recovery losses

Qg _ sw  Qgd  0.5Qgs

tsw  Qgsw I g
V drv (Vth  ( I q min (1/ g m )) Vth  I qpk (1/ g m )
Ig _t2  I g _ t3 
Rg  Rgext  Rdrv Rgfet  Rgext  Rdrv
20
Low Side Losses
• Profile of Loss in High side and Low side are quite
different especially for Low output voltages.
• Low side losses are dominated by conduction
losses
• High side conduction and switching losses

Pconduction _ LS  I 2 qrms _ LS Rdson  I o2 Rdson (1  D)

Select HS Mosfet for low Qg

Select LS Mosfet for low Rds_on

21
Mangetic Materials

• There are two classes of materials

• 1. Alloys of iron, which contain silicon (Si), Nickel
(Ni), Chrome (Cr) and Cobolt (Co)
• 2. Ferrites – ceramic materials mixture of iron,
Manganes (Mn), Zinc (Zn), Nickel (Ni) and Cobolt
(Co)

22
Inductor Losses ( Conduction and Core)
Inductor _ PL  I LF _ RMS 2 r0
DCR losses
r0  Inductor _ DCR

• Core losses
• Core losses can be calculated based
upon flux density, frequency of
operation, core volume
• Core vendors provide core loss data vs
frequency used to estimate core losses
• For Ferrite cores: Steinmetz equation
defines core losses

  flux _ density
f b Ve
PL  K  a ( ) ( ) Ve  core _ volume(cm)
106 1000
f  frequency (khz )

23
Output Inductor saturation behavior

I1 I2

+ + Waveform shows
rc
RL Vo
output inductor
Vin V1 V2

Co
waveform in
PWM
- switch -
1) normal
operation
Inductor
Saturation 2) Inductor is
saturated.
3) Saturation is
reduction in
inductance as
function of
No current, which
Inductor
Saturation can destroy the
MOSFET

24
Capacitor - Input / output

Ideal
Input Capacitor selection
C Ideal Capacitor criteria is to meet:
Real World

• Input capacitor rms ripple

RL

Real World Capacitor current rating

esr

esl
C

Output Capacitor
selection criteria is based
upon
• esr of the capacitor ( in
order to meet o/p ripple
voltage specification)
• Bulk capacitance to
ensure it meets maximum
overshoot/ undershoot
during transient conditions.

25
Current Mode Control

• Current mode Control has two loops

– Inner current loop
– Outer voltage loop

26
Current mode control
• Current loop stable for duty cycle less than 50% for Vin=12V Vout = 1.2V Duty cycle is
10%
• Current loop un-stable for duty cycle greater than 50% - requires slope compensation

27
Adding slope compensation
• For duty cycle > 0.5 slope compensation required.
• Minimum slope required is ½ downslope of inductor current

28
Current loop
• Current loop is sampled data loop
– Peak inductor current is sampled and held until next switchng cycle
– Transfer function He models sampling nature of current loop

29
Buck Regulator with Current Mode Control

Vin Q1 L1 Vout

D1
SWITCH
CURRENT
MEASURE

SWITCH
DRIVER PWM ERROR
COMPARATOR AMP

Q R

S
1.25V
CLOCK REFERENCE

30
 Why Emulated Current Mode?

• Step down switching regulators designed for high input voltages must control very short
minimum on-times to operate at high frequencies.
• The maximum switching frequency (and size of the inductor and output capacitor) are
function of the minimum on-time.
• The on-time of conventional current mode controllers is limited by current measurement
delays and the leading edge spike on the current sense signal. When the Buck FET
turns on and the diode turns off, a large reverse recovery current flows, this current
can trip the PWM comparator. Additional filtering and / or leading edge blanking is
necessary to prevent premature tripping of the PWM. The emulated current signal is
free of noise and turn-on spikes.

Leading edge spike,

conventional current
mode control.

31
 Current Mode Control
Advantages / Disadvantages

ADVANTAGES
• Current mode control is a single pole system. The current loop forces the inductor to act as
constant current source.
• Current mode control remains a single pole system regardless of conduction mode
(continuous mode or discontinuous).
• Inherent line feed-forward since the ramp slope is set by the line voltage.
• By clamping the error signal, peak current limiting can be implemented.
• Ability to current share multiple power converters.

DISADVANTAGES
• Susceptibility to noise on the current signal is a very common problem, reducing the
ability to process small on-times (large step-down ratios).
• As the duty cycle approaches 50% current mode control exhibits sub-harmonic
oscillations. A fixed slope ramp signal (slope compensation) is generally added to the
current ramp signal.

32
 Emulated Current Mode, How
Does it Work?
di/dt = (Vin - Vout) / L1

Vin Q1 L1 Vout

Cout

A=1
Vout
Vin - Vout
Vin dv/dt = (Vin - Vout) / CRAMP
5u x (Vin - Vout) 25uA

CRAMP RAMP

C
ONTROL
TIMING
D1 RAMP SIGNAL FOR PWM
AND CURRENT LIMIT

Is

0.5 V/ A SAMPLE RAMP

Rs &
HOLD
Sample and Hold
DC Level

TON

33
 Emulated Current Mode
Waveforms

SW

Emulated Current IL
Mode Controller
Timing

IDIODE

Sample and Hold

of Diode (Inductor)
IBUCK SWITCH
Current

EMULATED
RAMP
0.5 V/A

34
 Maximum Input Voltage vs Operating Frequency

• For a minimum on-time capability of 80ns, the minimum duty cycle is therefore 80ns
x Fsw. For low output voltage, high frequency applications the maximum switching
frequency may be limited. If VinMAX is exceeded pulses will have to skip.

80ns

Tsw

To calculate the maximum switching frequency use:

Vout  VD
Fsw MAX 
VinMAX  80ns

Where VD is the diode forward drop

35
Maximum Operating Frequency vs Output Voltage

For high input voltage Max Operating Frequency vs

applications the real Output Voltage (Vin = 36V)
maximum operating
frequency is determined by 1200

Max Operating Frequency (KHz)

the minimum on-time
(TON(MIN)) of the controller. 1000

Fsw = (Vout+Vd) / (TON(MIN) x Vin) 800

Max operating frequency 600

vs output voltage for the
LM2557X family. 400
(TON(MIN) = 80ns)
200

Max operating frequency 0

vs output voltage for a 1 2 3 4 5
“2.8MHz” device. Output Voltage
(TON(MIN) = 150ns)

36
 Minimum Input Voltage vs Operating Frequency

• A forced off-time of 500ns is implemented each cycle, to allow time for the sample &
hold of the diode current. The maximum duty cycle is therefore limited to; 1 – (500ns
x Fsw). For high frequency applications the minimum input voltage may be limited. If
Vin is less than VinMIN the output voltage will droop.

Tsw - 500ns

500ns

Tsw

To calculate the minimum input voltage use:

Vout  VD
VinMIN 
1  Fsw  500ns
Where VD is the diode forward drop

37
 Slope Compensation

Background: Current mode controlled

power converters operating at duty
cycles >50% are prone to sub-harmonic Solution: A 25uA offset in the RAMP current
oscillation. Disturbances in peak rising source provides additional slope for the
current ( I) increase at the end of the cycle. emulation ramp.

A=1
Vout Vin - Vout
Vin
5u x (Vin - Vout) 25uA

RAMP

CRAMP
CONTROL
TIMING

38
 Emulated Current Mode Advantages /
Disadvantages

ADVANTAGES
• Reliably achieves small on-times necessary for large step-down applications.
• All of the intrinsic advantages of current mode control are retained without the noise susceptibility
problems often encountered from; diode reverse recovery current, ringing on the switch node and
current measurement propagation delays.
• During short circuit overload conditions there is no chance of a current run-away condition since
the inductor current is sampled BEFORE the buck switch is turned on. If the inductor current is
excessive, cycles will be skipped until the current decays below the over-current threshold.

DISADVANTAGES
• The maximum duty cycle is limited to less than 100% since off-time is required for the sample
and hold measurement of the diode current.
• If the inductor saturates, it will not be detected.

39
 Constant Frequency, COT
Switching Regulator
VIN

LM5010/10A
On-Time
+
+ Inversely L
VREF - V OUT
Proportional
- to Vin
Feedback
Comparator RL
C

+ RC
(ESR)
-
I-Limit
Comparator - +
Vth

R F1
R F2

Nearly constant operating frequency plus

all of the benefits of the conventional
Constant On Time regulator.

40
 Constant Frequency COT Regulator
Waveforms (CCM)

VSW
VIN
tON

-0.3V
Buck switch ON T
time: IL
tON = K / Vin
IOUT I RIPPLE

VOUT

Buck switch turns

on at the VFB VOUT(DC)
threshold V RIPPLE

Freq * tON = Vout / Vin

but tON = K / Vin
Freq * K / Vin = Vout / Vin
Freq = Vout / K = constant for given Vout
41
Summary

• Synchronous Buck converter is reviewed

• All critical Component and their
selection criterias are highlighted.
• Small-signal model of converter is
developed
• Various control architectures are
reviewed for high-step down voltage
ratios.

42
43
Backup

44
45
 LM5010A High Voltage Step Down
Switching Regulators

Features
Input
6V - 75 V
LM5010A
VIN START-UP VCC
• Delivers 1A Continuous to Load REGULATOR
VCC UVLO
• Operates from 6V to 75V Input Supply THERMAL
• Constant On-Time Control DISABLE
SHUTDOWN

• No Control Loop Compensation ON/OFF

0.7V
TIMERS
RON/SD
• Nearly Constant Switching Frequency 2.5V
BST

• Adjustable Output Voltage (2.5V – 65V)

• Adjustable Soft-start SS
VIN

• Precision 2.5V Feedback Reference DRIVER

LOGIC
SW
• Low Bias Current (350uA, typ.) FB
FEEDBACK
VOUT

• Adjustable Valley Current Limit

• Thermal Shutdown OVER-VOLTAGE CURRENT LIMIT
+
• 125C Max. Junction Temperature - ISEN

2.9V 60 mV 50 m
RTN
SGND
Package
TSSOP – 14EP (4mm x 5mm)
LLP - 10 (4mm x 4mm)

46
Operating Frequency vs Input
Voltage (CCM)

47