Brno Flyback Design Rev1 PDF

Step by Step Design Tutorial of a
fixed-frequency adapter < 75 W

with very low power consumption
Presented by: Petr Papica
Agenda
• Application and requirements
• Flyback converter basics
• Flyback converter parasitic
• Design step 1: Power stage
• Design step 2: Efficiency optimization
• Design step 3: Control mode and protections
• Design step 4: No Load Input Power
• Design step 5: Magnetics
• Design step 6: EMI
• Demoboard example
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The flyback, a popular structure
The flyback converter is widely used in consumer products
Ease of design, low-cost, well-known struture
Poor EMI signature, bulky transformer, practical up to 150 W
DVD player
flyback ≈ 10 – 35 W
charger
notebook
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EPA 2.0 (External Power Supplies)
(was > 0.84 in previous version 1.1)
(< 0.5 W in 1.1)
(< 0.75 W in 1.1)
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EPS 5.0 (ENERGY STAR® Program Requirements
for Computers)
• Defines ETEC for different types of products as a Typical Energy Consumption
• For the desktop and notebook product categories TEC will be determined by the following formula:
ETEC = (8760/1000) * (Poff * Toff + Psleep * Tsleep + Pidle * Tidle)
• where all Px are power values in watts, all Tx are Time values in % of year, and the TEC ETEC is in units
of kWh and represents annual energy consumption based on mode weightings
• The light load efficiency and no load consumption is more important
ETEC requirement desktops and notebooks
Desktops and Integrated Computers (kWh) Notebook Computers (kWh)

Category A: ≤ 148.0 Category A: ≤ 40.0
TEC (kWh) Category B: ≤ 175.0 Category B: ≤ 53.0
Category C: ≤ 209.0 Category C: ≤ 88.5
Category D: ≤ 234.0
• Effective from July 1, 2009 (except: game consoles from July 1, 2010)
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Agenda
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An isolated buck-boost
2 7 8
11
drv SW1 L C
Vout 1 N C Vout
D
Vin 1 4 Vin Vin
5 9 12
D Vout gnd gnd
L C drv
D drv
a b SW1 c SW1
buck-boost buck-boost flyback

ground referenced input referenced isolated ground referenced
The flyback converter is an isolated version of the buck-boost cell

By rotating the switch, we obtain a ground-referenced isolated converter
Keep this in mind for the small-signal analysis!
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On-time and freewheel
V(SW / D) = Vout
V(SW / D) = Vin
SW IL
Vout IL D
Vout
L VL L VL
Vin Vin
R R Vout
C C
IL IL
IL IL
Circulates in the
Vin same direction
I peak = I valley + ton I valley = I peak −
Vout
toff
L L
SW is closed, D is blocked SW is open, D is closed
When the switch closes, current ramps-up in L

At the switch opening, the stored energy is dumped into C
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The flyback circuit
1:N D1
Vout
.
Cout Rload
.
Vin
drv
Similar buck-boost equations hold when scaled by the turn ratio N

The switch is now ground referenced for an easier drive
We have galvanic isolation between the primary and the secondary
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The turn-on event
-Vin.N Vout
ILp Vin
IC Son =
Lp
.
Lp Ls VLs R Vin
VLp (Np) . (Ns) C Vout I peak = I valley + ton CCM
Vin
Lp
ILs = 0 IR
Vin
0
D I peak = ton DCM
N = Ns / Np
Lp
SW
S
ILp
PIV = Vin N + Vout Reverse voltage on the diode
The controller instructs the power switch to turn on

The current increases in the inductor in relationship to Vin and Lp
The output capacitor supplies the load on its own
Simplified, no leakage
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Applying volt-second balance, CCM
VLp(t)
Vin
ILs = ILp / N IC IR
Lp
. Ls R
VLs C
VLp=Vout/N (Np) . (Ns) Vout
Vin Vout/N
D
Vin+VLp
ton = DTsw toff = (1-D)Tsw
N = Ns / Np
Vout Reflected
ILp=0
S
VDS ,off = Vin + = Vin + Vr
N voltage
Vout Nton NDTsw ND

= = =
Vin toff (1 − D ) Tsw (1 − D )
dc transfer function in CCM Simplified, no leakage
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Applying volt-second balance, DCM
VLp(t)
ILs = 0 IC
Vin
IR
. DT
Lp Ls VLs R
VLp=0 C
(Np) . (Ns) Vout
Vin
Vout /N
Vin
N = Ns / Np ton = DTsw toff = (1-D)Tsw
VDS ,off = Vin
dc transfer function in DCM

Vout Rload
=D N no longer plays a role
Vin 2 L p Fsw Rload, Lp and Fsw do
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Flyback, typical waveforms
X2
XFMR
RATIO = -0.1 D1
6 1
Vout
Lp
. 3
Cout Rload
2.2m Ls 470u 2
. IC = 10
5
IIn
Vin Vds
100
D
4 2 X1
PSW1
V2 RON = 10m
ROFF = 1Meg
S
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
A simple flyback circuit without parasitic elements

It runs open-loop for the sake of simplicity
Vout = 8 V
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Flyback, typical waveforms, CCM
1.60
Ipeak Iin(t)
iin in amperes
1.20
plot1
800m
400m
Input current
0 1
1.15
∆I L Ivalley
i(lp) in amperes
1.05 ILp(t)
plot2
950m
850m
2
750m Epeak
Diode blocks
Vout N + Vin
250 E valley
Vout N
vds in volts
190 3
Vin
plot3
130
70.0
10.0
VDS(t)
8.89
4
vout in volts
8.87
plot4
8.85
8.83
8.81
Output cap.
refueling
Output capacitor
supplies the load
Vout(t)
16.0
id(d1) in amperes
12.0 Ipeak / N Id(t)

plot5
8.00 5
4.00
0
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
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Flyback, typical waveforms, DCM
iin in amperes 400m
300m
Ipeak Iin(t)
Plot1
200m
100m Input current
0 1
400m
∆I L
i(lp) in amperes
DCM (core reset)

300m ILp(t)
Plot2
200m
100m
0 Epeak 2
Evalley = 0
Vout N + Vin
400
Diode blocks
Vout N VDS(t)
vds in volts
300
Plot3
200
100
Vin
3
0
12.648
4
vout in volts
12.644 VDS is back

Plot4
12.640
to Vin when
12.636 Output capacitor
12.632
Output cap.
refueling supplies the load Vout(t) all SW are
3.00 blocked.
id(d1) in amperes
2.00 Ipeak / N Id(t)

Plot5
1.00
0 5
-1.00
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
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Energy transfer in CCM and DCM
1
ELp ,valley = L p I valley 2 Initially stored energy
2
1
ELp , peak = L p I peak 2 Stored energy at ton
2
ELp , accu = L p I peak 2 − L p I valley 2 = L p ( I peak 2 − I valley 2 ) Accumulated energy at Tsw
1 1 1
2 2 2
Power (watts) is energy (joules) averaged over time (a switching cycle, seconds)
( )
1 1
Pout = I peak 2 − I valley 2 Lp Fswη Pout = I peak 2 L p Fswη
2 2
CCM DCM, Ivalley = 0
Eta, the efficiency
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Agenda
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The leakage inductance
The coupling in a transformer is not perfect

Some induction lines couple in the air: leakage flux
Closed path
in the air Leakage flux
Closed path
Leakage flux in the air
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An equivalent transformer model
For a two-winding transformer, the model is simple:

Two leakage inductors
One magnetizing inductor
Lleak1 Lleak2
Lp
primary secondary
1:N
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The leakage role
ILp
. Lp
VLp (Vout+Vf) / N
VLp
Lp Ipeak
(Np)
ILp
Vin
Lleak
Vin Lleak Lleak
Ipeak
D
0
D
ILp SW
Clump
Clump VDS
S
ILp
S
The switch closes: The switch opens:

Current flows in Lleak and Lp The current charges the lump capacitor
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Drain-source excursion
X4
XFMR-AUX
RATIO_POW = -0.05 D5
Rprim
RATIO_AUX = -0.06 1N5822
0.5
Vout
12 7
16 V
9
1 Icoil
Resr1
60m Rload
Lprim 9
3m 10 dem
R6 5
4.7k C6 Cout1
3
600p 2.2mF
Vin
Lleak
15u Vdrain
800
VDS,max
350 V 600
750 V VDS(t)
vdrain, v(9) in volts

8
400
Vin
Id 200
11 0 Valley switching
IReso
X3
drv 6 MTP4N85m Creso
1.5n
800m
Ipeak = 695 mA
4
400m
ILp(t)
Rsense
0.5
0
-400m
ILleak(t)
-800m
Reflected Vout 7.940m 7.944m 7.949m

time in seconds
7.953m 7.957m
( +Vf )
Characteristic
V Lleak impedance
=V + + I peak
out
VDS,max in Need to limit the excursion!
N Clump
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The need of a clamp
X2
Rclp Cclp Rs XFMR D1
1n5819
250m RATIO = -0.1
2 1 Vout
5
Vclamp Lp . 3
Cout
{Lp} Ls 470u
∆
IIn 150 VLp
ILp . IC = 10
Vclamp ID1 7
Rload
1k
10 6
Lleak Resr
9 D3 150m
∆
MUR160 VLeak ILeak {Leak}
Vin
100
Lp
Vds
4 8
parameters
Dclp Dbody
C2 Lp=2.2m
V2 100p
k=0.02
Leak=Lp*k
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
The clamp is made by a low impedance voltage source

When the drain reaches Vin + Vclamp, the clamp diode conducts
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A reduced secondary-side current
260m
ilp in amperes
plot1 180m ILp(t) Ipeak = 236 mA I’peak = 210 mA
100m
20.0m 2
-60.0m
∆t = 480 ns
260m
Leakage inductor Ileak(t)
illeak in amperes
180m
reset sequence
Plot3
100m
20.0m 0 3
-60.0m
trr
2.50
Id,peak=2.1 A Id(t)
id1 in amperes
1.90
plot2
1.30
700m
100m 4
280
200
VDS(t)
vds in volts
Plot4
120
1
40.0
-40.0
3.011m 3.015m 3.019m 3.023m 3.027m
time in seconds
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Ringing and turn-on in the valleys?
570
Vin + Vclamp R
−
2L
Vr + Vin e
410
Vr Vin
Vr
vdrain in volts
plot1
250
tv
90.0
valleys
1
(L + Lleak ) Clump
1
tv = =π p
-70.0
VDS(t) 2 f0
1.002m 1.008m 1.015m 1.021m 1.028m

time in seconds
Wait until the drain voltage is minimum and reduce turn-on losses: valley switching!
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Agenda
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Power stage: Schematic of flyback converter
N sec
N=
N prim
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Power stage design: Bulk capacitor
• Output power Pout Pout = Vout ⋅ I out
Pout
• Estimation of input power Pin Pin = Estimate the η based
η on the EPA standard
Pin
• Average input current Iin,avg I in ,avg =
Vbulk ,min
• Design the bulk capacitor for the maximum output power and
the minimum input line voltage.
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Power stage design: Bulk capacitor
• 1st current approach
∆Vbulk
 1  ∆Vbulk 
Vbulk,min
1 I in , avg −1 
Cbulk = ⋅ 1 − ⋅ cos 1 − 

2 ⋅ f line ∆Vbulk  π  V peak 
Simple current approach:
I in ,avg ⋅ t 2
Cbulk =
∆Vbulk
Use t2=7.5 to 8.5ms for fline= 50Hz
• 2nd power approach 1

T=
f line
2 ⋅ Pin ⋅ t2 Consideration:
Cbulk =
V peak − Vmin
2 2
Low volume bulk: large ripple, better PF, lower input RMS current
High volume bulk: low ripple, bad PF, high input RMS current
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Power stage design: Drain voltage
Vds(t)
Vds_max
Vleak
Vclamp
Vr
tleak
Vr
Vds_pk
Vbulk
trec
toff ton
Tsw t
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Power stage design: Transformer ratio
Transformer ratio – consideration of the VDSS of used Q1
kC ⋅ (Vout + V f ,diode ) Vclamp

N= kC =
0.85 ⋅ VDS ,max − 20V − Vbulk ,max Vr
The 20V means margin for clamping diode turning-on overshoot.
Reflected voltage Vr at primary from secondary

Vout + V f ,diode N sec
Vr = N=
N N prim
Maximum duty cycle DCmax
In CCM operation: In DCM operation doesn’t depend on N:
Vr Vout 2 ⋅ L prim ⋅ Fsw

DC max = DC max = ⋅
Vr + Vbulk ,min Vbulk ,min Rload ,min
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Power stage design: Current ripple
The average shared

transformer current reflected
to primary winding IL,avg
∆I
Ipeak
I in ,avg
I L ,avg =
Ivalley
DC max
Choose the relative ripple δIr: it affects the operation in the CCM or DCM
• For universal AC input design use the δIr in range 0.5 to 1.0
• For European AC input use the δIr in range 0.8 to 1.6  δI r 
I peak = I L ,avg ⋅ 1 + 
∆I = δI r ⋅ I L , avg  2 
∆I
δI r =  δI r 
I L ,avg ∆I = I peak − I valley I valley = I L ,avg ⋅ 1 − 
 2 
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Power stage design: Primary inductance
Transformer primary winding inductance Lprim
Vbulk , min ⋅ DC max
L prim =
Fsw ⋅ ∆I
Maximum RMS value of the current flowing through primary winding Iprim,RMS
 ∆I 2 
= DC max ⋅  I peak − I peak ⋅ ∆I + 
2
I primRMS
 3 
Maximum RMS value of the current flowing through secondary winding Isec,RMS
I peak ∆I
I sec, peak = ∆I sec =
N N
 ∆I sec 
2
= (1 − DC max ) ⋅  I sec, peak − I sec, peak ⋅ ∆I sec + 

2
I sec RMS
 3 
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Power stage design: Q1 selection
Conduction loss at Q1 should be approx. 1% of the Pout
Pout
R DSon ≤
100 ⋅ I prim , RMS
2
Then the right device is chosen by parameters VDSmax, Ipeak, ton, toff
Current sensing resistor Rsense selection

VILIM
Rsense = Psense = I primRMS ⋅ Rsense
2
1.1 ⋅ I peak
The 1.1 factor means 10% margin for Lprim and other
parameters spread, to be able to deliver maximum power.
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Power stage design: Secondary rectification
D1 selection: Cout selection:
Minimum Cout value
Reverse voltage across D1
I out ⋅ DC max
PIV = Vbulk ,max ⋅ N + Vout C out ≥
Vout ,ripple ⋅ Fsw
The next important parameters for
D1 selection are Isec,peak, Iout and The maximum allowed ESR of Cout
the fast and soft recovery
Vout ,ripple
ESR ≤ Dominant part
I sec, peak
I Cout ,rms = I sec, rms − I out

2 2
It is recommended to use more parallel

Cout for lowering the output voltage ripple.
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Power stage design: Clamping network
TVS – losses in the suppressor: better at no load conditions
1 Vclamp
= Eclamp ⋅ Fsw = ⋅ Lleak ⋅ I peak ⋅ Fsw ⋅
2
Pclamp
2 Vclamp − Vr
RCD clamp – 1st iteration: better EMI response
2 ⋅ Vleak ⋅ Vclamp Vclamp

2
Rclamp = Pclamp =
Lleak ⋅ I peak ⋅ Fsw
2
Rclamp
Vclamp These values need to be optimized for the

C clamp > no load consumption and losses in slow
Vripple ⋅ Rclamp ⋅ Fsw clamping diode D2
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TVS vs RCD clamp comparison
Drain voltage ringing with TVS as clamp Drain voltage ringing with RCD as clamp
Different Rdamp used in clamp
Ch1 – Drain, Ch3 – Clamp node
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Agenda
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Application schematic
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The losses distribution
Losses distribution measured without EMI filters and surge protecting NTC
3.00
2.78
2.50
2.53
2.44
2.00
Power loss [W] 1.50

1.52
1.00
0.50
0.00
h
er
er
r
itc
ie
i
rm
ti f
if
sw
ct
ec
re
sf
y
tr
ar
an
ry
pu
im
da
Tr
In
Pr
n
co
Se
Input line Input power Output power Total loss power Efficiency
110 V / 60 Hz 72.5 W 63.62 W 8.88W 87.75%
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Optimization of efficiency
• There was not found excessive contributor of losses in the
power stage of the flyback converter
• Losses in all components should be decreased
• Optimization approach:
1) decreasing the losses in power stage by selection of
primary switch Q1 and secondary rectifier D1
2) decreasing the losses in power stage by decreasing
losses in transformer
3) try to improve the bridge rectifier (not much space)
4) decreasing the conductive losses in EMI filters
5) Do we need surge protecting NTC in case of “low value”
bulk capacitor ?
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Influence of EMI filters
• Input EMI filter contributes to the conductive losses mainly at full load
and low line condition
• The high inductance 22mH or more is needed to reject the “low”
frequency emissions ( below 1 MHz )
• There is needed to use two chamber CM choke or 2 CM mode chokes
to reject the high frequency emissions above 10MHz
• Output EMI filter (CM choke) reject the high frequency emissions from
the DC cord, only low inductance is needed → low Rdc → low
conduction losses
• The most important are losses in the high inductance input common
choke from the efficiency optimization point of view
Note from experiments:

There was found an influence of HF ripple at input current to the precision of measurement of input power
using wattmeter YOKOGAWA WT210. There were measured lower input power with the connected 100uH
common choke in comparison without any EMC filter. (at the same conditions) It is better always to use some
EMI filter, with small Rdc to reject the error given by the noisy HF currents.
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Transformer optimization result
Q1 breakdown
area Transformer ratio Ns/Np optimization
89.50% The optimum ratio is

given by the Q1
maximum break down
89.00%
voltage with 15%
derating factor
88.50%
Optimum ratio Decreasing the Ns/Np

88.00%
decreases the
Efficiency [%]
secondary winding
87.50% losses and primary
RMS current
87.00%
Decreasing the Ns/Np

86.50% increases the Q1
switching losses and
86.00%
secondary RMS
current
85.50%
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Transformer ratio Ns/Np [-]
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Improving Efficiency
• Sources of loss:
– Switching losses:
1
Ploss ( switching ) = ⋅ C DRAIN ⋅ VDRAIN ( turn−off ) ⋅ FSW
2
2
– Losses caused by leakage inductance:
1
Ploss(leak) = ⋅ Lleak ⋅ I peak ⋅ FSW
2
• Ways to improve efficiency:
– Lower the switching frequency FSW frequency foldback at light loads
– Lower the Drain voltage at turn-off valley switching
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Synchronous rectification
• New SR controller NCP4303

coming in 2010
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Agenda
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Application schematic
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The voltage-mode PWM generation
6.50
Verror
4.50
verr, ramp in volts

plot1
2.50
497m 2
1
PWM -1.50
modulator
7.00
+ 5.00
100 %
D
out in volts
plot2
3.00
- 1.00 0% 3
-1.00
10.0u 30.0u 50.0u 70.0u 90.0u

time in seconds
In voltage-mode, one compares the error voltage to a fix ramp

This is « Pulse Width Modulation » also called « PWM »
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The voltage-mode PWM generation
Vin Vout
This level
sets the duty-cycle
Rupper
Error
Amplifier PWM
- comparator
+
+
-
Vref
Rlower I > Imax ? Rsense
--> reset
The inductor current is sensed for safety only
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The current-mode PWM generation
3.00 3.50
r ror v ol tage 2
1
2.00 2.50
E
idrain in amperes
vfb in volts
plot1
1.00 1.50
0 500m
-1.00 -500m
S 1.31m 1.65m 1.99m

time in seconds
2.33m 2.67m
Q MOSFET
Q
3.50 3.00
3
4
2.50 2.00
R
idrain in amperes
vfb in volts
Plot2
1.50 1.00
500m 0
-500m -1.00 Inductor peak current

2.50m 2.57m 2.65m 2.72m 2.80m
time in seconds
In current-mode, the error voltage fixes the peak current
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The current-mode PWM generation
Vin Vout
This level
sets the peak current
Rupper
clock
Error
Amplifier
-
S
+
Q
Q
Current sense
R
comparator
-
Rlower
Vref +
Rsense
The sense resistor provides a pulse-by-pulse current limit
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Same modulation between VM and CM
Both modulators use trailing edge modulation
feedback
on
Trailing edge
off modulation
Clock
feedback
on
off
Leading edge
off
modulation
Clock
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NCP1237/38/87/88 flyback controller
Value Proposition
The NCP1237/38/87/88 series represents the next generation of fixed frequency PWM controllers. It targets
applications where cost-effectiveness, reliability, design flexibility and low standby power are compulsory.
Unique Features Benefits Application Data
High-voltage current source Fewer components and
with built-in Brown-out and rugged design
mains OVP Extremely low no-load
Freq. reduction in light load standby power
conditions and skip mode Simple option to alter the
Dual Auto
Adjustable Over Power max. peak current set DSS Latch
OCP Recovery
Protection point at high line NCP1237A Yes Yes Yes
NCP1237B Yes Yes Yes
NCP1238A Yes No Yes
Others Features NCP1238B Yes No Yes
Latch-off input for severe fault conditions, allowing NCP1287A HV only Yes Yes
NCP1287B HV only Yes Yes
direct connection of NTC NCP1288A HV only No Yes
Timer-based protection: auto-recovery or latched NCP1288B HV only No Yes
Dual OCP option available
Built-in ramp compensation Various options available depending
Frequency jittering for a softened EMI signature
Vcc operation up to 30 V upon end applications needs
Market & Applications Ordering & Package Information
AC-DC adapters for notebooks, LCD monitor, game
NCP1237/38xDR2G - NCP1287/88xDR2G
console, printers
SOIC-7 2500p per reel Pb O, DW
CE applications (DVD, STB)
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NCP1237/38/87/88 – Built-in Startup FET
A flyback auxiliary winding supplies

biasing voltage in normal condition to
save power
High startup current to

reduce charging time
Low initial startup current to prevent

damage if Vcc pin is shorted to ground.
Saves PCB area

No startup resistor!
& saves power
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NCP1237/38/87/88 – Dynamic Self Supply (optional)
Vcc
How it works... Vccon
11.3V avg
(HV) Vccoff
pin8
2
4 +
ON/OFF
3
-
(Vcc)
pin6
10.5V/12V C ON
Current
source
OFF
10.00M 30.00M 50.00M 70.00M 90.00M
Power ON Current Source turns ON Vcc is rising; no output pulses

Vcc reaches Vcc(on) Current Source turns OFF Vcc is falling; output is pulsing
Vcc falls to Vcc(off) Current Source turns ON Vcc is rising; output is pulsing
Dynamic Self-Supply No need of auxiliary winding!

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54
NCP1237/38/87/88 – Dual startup current level
Startup current is Startup current is

low initially to off when VCC
prevent damage reaches VCC(on)
when VCC pin is
grounded.
Startup current is activated when VCC

drops to VCC(off). Hence, the voltage
never drops below VCC(off) after startup.
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55
NCP1237/38/87/88 – Brown-out and Mains OVP
Detection independent of Can be connected to the

Ripple on HV pin half-wave rectified ac line
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NCP1237/38/87/88 – Brown-out and Mains OVP
VHV
VHV(start)
VHV(stop)
Starts
time
only at
VCC(on) HV HV
timer timer
starts restarts
One Shot
40ms min.
time
DRV
Brown-out
time
Timer-based detection Passes full line cycle drop-out
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Current overshoot: do not underestimate it…
ILp
Turn off is
Detection delayed …
occurs here ∆Ipeak
Ipeak,max
real
Ipeak,max
controller
SLp
tprop
t
Vsense,max Vin ,max
I peak ,max = + t prop
Rsense Lp
Watch-out for clamp voltage variations, at start-up or in short-circuit

The main problem comes from the propagation delay!
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NCP1237/38/87/88 – Over Power Protection
Need to compensate for the The compensation current

effect of the propagation delay creates an offset on the
Current Sense signal
Over Power Protection Maximum output power clamped
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NCP1237/38/87/88 – Dual OCP threshold
Output still in regulation
Fault timer Fault timer
VOUT starts
VOUT starts
Over Over
load Transient load
peak
power
Max Max Max

Skip Output Skip DC
Output
output peak
power load power power load
0.7V at 0.5V at 0.7V at
CS pin CS pin CS pin
Accommodates large output
Suitable for printers
power transients
These protections use the Up/Down counters, like classical analog integration.
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60
NCP1237/38/87/88 – 4 ms Soft Start
voltage / current without soft-start

with soft-start
time
VCC
Max. current setpoint envelope
time
4 ms “digital” soft-start operation
4 ms Soft Start Stressless start-up phase

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NCP1237/38/87/88 – Frequency Foldback
Switching frequency
Increased efficiency
lowered at light load
Switching frequency
No audible noise
clamped at 25 kHz
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NCP1237/38/87/88 – Recover from Standby
Soft-Skip
mode is left as
soon as the
voltage on the
feedback pin
reaches the
TLD threshold
Transient Load Detect Improved Load Transient

Function (TLD) response time
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NCP1237/38/87/88 – Latch-off Protection
VLATCH
Latch!
OK
Latch!
time
An NTC thermistor can be directly connected to the IC
Less external components needed

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64
CCM operation, current instabilities
IL
clock
Ipeak
IL(0)
∆IL(0)
Duty-cycle < 50%
t
Asymptotically stable Perturbation has gone…
IL
clock
Ipeak
Duty clamp
IL(0)
Duty-cycle > 50%
∆IL(0)
t
Asymptotically unstable
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CCM operation, curing current instabilities
IL n
 Sa 
 1 − 
S2
Verr ∆I L (nTsw ) = ∆I L (0)  −  = ∆I L (0) ( −a )
n
b c Ri  d ' + Sa 
 d S 2 
Sa
S1 Must stay
below 1
∆IL(0)
S2 IL(Tsw)
Sa
1−
IL(0)
∆t IL(Tsw) S2
Up to
d = 100%
<1
Sa
0+
t S2
dTsw d’Tsw
Tsw
Inject ramp compensation Sa > 50% S2
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NCP1237/38/87/88 – Slope compensation
• There is a built in slope compensation with no external setting
• The internal slope compensation is activated if the duty cycle is higher
than 40%
• The amount of slope compensation is 5mV/% observed at CS pin
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Block schematic
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Agenda
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Reducing No-load Input Power
• Static losses in the start-up circuit:
– Start-up resistor permanently drawing current from the bulk capacitor
• Ways to lower the start-up circuit losses

– With external start-up resistor Extremely low start-up current
– Integrated start-up current source Extremely low leakage when off
– Connect the start-up circuit to the half-wave rectified ac input
HV rail
1
NCP1351
8
Start-up resistors
2 7
Vcc
3 6
4 5
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Reducing No-load Input Power
Selected from Vpeak

Rstartup bulk connection 350
RstartupHW =
π I1
250
150
50.0
RstartupHW
-50.0
Mains 10.0M 30.0M 50.0M 70.0M 90.0M
input Cbulk time in secs
Vcc
auxiliary
CVcc winding
PRstartup π
PRstartupHW = Brings a 21% reduction in power
4
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No load input power reducing approach
• Decrease the transformer leakage inductance

• Use the controller IC with the frequency foldback and skip mode features
• Do not allow the DSS operation (Vcc cap increase)
• In case of low Vcc and high aux winding leakage increase the aux number of turns
to disable the DSS
• Decrease the value of the Vcc damping resistor (may affect the EMI)
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No load input power reducing approach
• Lower the M1 switching losses

• Optimize the clamping circuitry
• Reduce the losses in the secondary rectifier and its snubber
• Decrease the TL431 biasing
• Decrease the cross current through the feedback resistor divider
• Set a stable operation for all loading currents
• Do not use the output voltage indication LED
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Agenda
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Area product AP
• There is defined the area product AP [m4]
• Product of effective window area Wa [m2] and iron cross
section area Ac [m2]
AP = Wa ⋅ Ac
• Allows fast, effective and optimal magnetic design

• Should be published in core datasheet
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Window utilization factor Ku
Ku is a measure of the amount of copper that appears in
the window area of transformer. This window utilization
factor is affected by:
1) Wire insulation
2) Wire lay (fill factor)
3) Bobbin area
4) Insulation required for multilayer windings or between windings
Typical values lay in range 0.35 to 0.48
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The load coefficient Kload
• Flux density in magnetic should be designed at Ipeak with
some margin (5%) to avoid saturation
• Do you really need 100% Iout for 100% time??
If not, decrease core size!!

I out ,,RMS
K load = RMS
Example: I out , RMS ,max

• Maximum DC output current is 3.5A, but it’s only needed for
transients
• The long term RMS value is only 1.75A (at least 10 min.)
• Loading coefficient is only 0.5 (not 1) → core size is smaller
→ losses in core and in copper are smaller
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77
Flyback transformer core sizing
The core size can be calculated by the AP factor in case of these inputs:
1. Converter parameters: Lprim, Ipeak, Kload, δIr, DCmax

2. Core maximum flux density Bmax considered with the hysteresis and
eddy current losses at switching frequency Fsw
3. Winding parameters (utilization factors for primary and secondary
windings Kuprim, Kusec), (current densities in primary and secondary
windings Jprim, Jsec
L prim ⋅ I peak
2
 DC max 1 − DC max  δ I r + 12
2
AP = ⋅ K load ⋅  + ⋅
Bmax  J prim ⋅ Ku prim J sec ⋅ Ku sec  3 ⋅ (δI + 2)2
  r
Now the appropriate core can be selected from the vendor products list by
the AP factor .
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Windings design
• Number of turns of primary winding
L prim ⋅ I peak
NT prim =
B max ⋅ A c
• Number of turns of secondary winding

NTsec = N ⋅ NT prim
• Number of turns of auxiliary winding

VCC + V f ,Vcc
NTaux = ⋅ NTsec
Vout + V f ,diode
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Air gap length lg
N ⋅ µ 0 ⋅ I peak MPL
lg = − in case of l g << MPL
Bmax µr
MPL – core magnetic path length

µ0 - permeability of vacuum
µr - permeability of core lg
In case an EE, RM or pot core is used, divide Ac

the calculated lg by factor 2, because your
core has 2 air gaps in magnetic path
MPL
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Agenda
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81
How to improve EMI of my design?
Diode snubber
AC line filter
DC output filter
Clamping loop
DRV damping
Power switch loop
• All switching loops with RF currents should have small area

• Divide input AC filter at two chokes to decrease the parasitic capacitance
coupling
• CY – closes the current loop for the RF currents injected via transformer
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Diode snubber design
• Snubber resistance value should be close to the characteristic
impedance of ringing circuitry
Lleak,SEC –the transformer leakage

Lleak , SEC inductance observed from
Rsnubber = secondary side
Cd
Cd – reverse direction diode
capacitance
• RC time constant of the snubber should be small compared to the

switching period but long compared to the voltage rise time
C snubber ≈ 3 ÷ 4 ⋅ C d
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83
PCB Layout tips
DRV loop Clamping loop
Output loop Power switch loop Capacitor pads arrangement for

better filtering RF currents
Diode snubber
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84
Agenda
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Preliminary demonstration board
A typical 65 W notebook adapter (19 V output)
(optimized for EPS 2.0)
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Schematic of preliminary demonstration board
A typical 65 W notebook adapter (19 V output)
(optimized for EPS 2.0)
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87
Demonstration board Efficiency (measured with DC cord)
The DC cord length is 1.05m and copper cross sec. is 0.75mm2
VIN
115 Vac/60Hz 230 Vac/60Hz
% of POUTnom
100 %
(65 W)
87.10 % 87.37 %
75 %
(49 W)
87.52 % 87.63 %
50 %
(32 W)
87.54 % 87.88 %
25 %
(16 W)
87.79 % 85.96 %
Average at 115Vac is 87.32% and at 230 Vac is 87.21 %
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Demonstration board Standby Power
Light load and no load input power with the NCP1237
VIN
115 Vac/60Hz 230 Vac/50Hz
POUT
10 % 86.55 % 83.74 %
(6.5 W)
5% 85.40 % 78.72 %
(3.3 W)
1% 77.49 % 73.77 %
(0.65 W)
No load 51.1 mW 73.5 mW
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Demonstration board Efficiency
90
88
86
84
Efficiency [%]
82
80
78
76 – 115 Vac - NCP1237

74
– 230 Vac - NCP1237
72
70
0 10 20 30 40 50 60 70
Pout [W]
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Demonstration board conducted EMI
80% of full load (2.72A) at 230V/50Hz NCP1237B65kHz
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NCP1237B100kHz frequency jittering
Ref1 – DRV frequency
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NCP1237B100kHz frequency foldback
Ch1 – DRV, Ch2 – FB, Ref1 – DRV frequency
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93
Load transient response from 20% to 100%
Ch1 – Drain, Ch2 – FB, Ch3 – Vout (AC coupling), Ch4 - Iout
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Load transient response from 100% to 20%
Ch1 – Drain, Ch2 – FB, Ch3 – Vout (AC coupling), Ch4 - Iout
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95
Conclusion
• Meeting the most recent requirements from ENERGY STAR®
or IEC is possible with the classical Flyback converter
• The new controller NCP1237/37/87/88 with frequency
foldback and skip-mode at light load makes it possible
• Average efficiencies above 87% are possible
• No-load input power below 300 mW is possible
• No-load input power below 100 mW is achievable, although
the controller alone cannot ensure this. The whole power
supply must be designed to reduce power waste.
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References
Tutorial and Application notes:
http://www.onsemi.com/pub_link/Collateral/TND376-D.PDF
http://www.onsemi.com/pub_link/Collateral/AND8461-D.PDF
http://www.onsemi.com/pub_link/Collateral/DN06074.PDF
Feedback loop design spreadsheet:
http://www.onsemi.com/pub/Collateral/FLYBACK DWS.XLS.ZIP
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Thank You! Any Questions?
Backup
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99
Over power compensation
The overpower compensation affects the primary peak current, by the following
formula:
VCS int t R  R
I PEAK = + Vbulk ⋅  PROP − g OPP ⋅ OPP  + Voff ⋅ g OPP ⋅ OPP
Rsense  LP Rsense  Rsense
Then the overpower compensation resistor can be calculated:
t PROP ⋅ Rsense
ROPP =
LP ⋅ g OPP
The over power compensating resistor affects only the Ipeak value, but in CCM the
output power is given by the following formula, where Ivalley plays a role:
Pout
1
2
(
= ⋅ η ⋅ L prim ⋅ Fsw ⋅ I peak − I valley
2 2
)
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2nd level over current protection
The overpower compensation affects the 2nd level over current

protection by the addition of bulk voltage feed forward.
− (Vbulk − Voff )⋅ g OPP ⋅

VCStran ROPP
I TRAN =
Rsense Rsense
The 2nd level over current protection can be used for

reducing the transformer size to ½ and keeping the peak
power capability.
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Spread sheet design of OPC
OPC design spread sheet was created and the user can choose the right
ROPP and it’s effect to Ipeak, Itran, Pout and Ptran:
Inputs: Output voltage

Primary turns
Vout [V]
N1 [-]
19
100
Secondary turns N2 [-] 25
Ramp Comp at CS RaCo [mV/%] 5
Maximum int set point Vilimit [V] 0.7
Sensing resistor Rsense [Ohm] 0.235
Propagation delay tprop [ns] 100
Primary inductance Lp [uH] 560
Vin to Iopp ratio gopp [uS] 0.5
Over power comp resistor Ropp [Ohm] 680
Switching frequency Fsw [kHz] 65
2nd level overcurrent prot Vcstran [V] 0.5
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Spread sheet design of OPC
Ipeak & Itran vs line input voltage Pmax & Ptran vs line input voltage
3.5 140.0
3.0 120.0
2.5 100.0
Ipeak [A], Itran [A]
Pmax [W], Ptran [W]

2.0 80.0
1.5 60.0
1.0 40.0
0.5 20.0
0.0 0.0
0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400
Vin [V] Vbulk [V]
Ipeak Itran Ptran Pmax
Keeping constant Ipeak in CCM mode tends to Ivalley decreasing with

increasing the Vin. That’s why the maximum output deliverable power
Pout increases with increasing Vin. Choose the right compensation.
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Step by Step Design Tutorial of a

fixed-frequency adapter < 75 W

(was > 0.84 in previous version 1.1)

(< 0.5 W in 1.1)

(< 0.75 W in 1.1)

ETEC = (8760/1000) * (Poff * Toff + Psleep * Tsleep + Pidle * Tidle)

• The light load efficiency and no load consumption is more important

ETEC requirement desktops and notebooks

Desktops and Integrated Computers (kWh) Notebook Computers (kWh)

buck-boost buck-boost flyback

The flyback converter is an isolated version of the buck-boost cell

When the switch closes, current ramps-up in L

Similar buck-boost equations hold when scaled by the turn ratio N

The controller instructs the power switch to turn on

Vout Nton NDTsw ND

N = Ns / Np ton = DTsw toff = (1-D)Tsw

VDS ,off = Vin

dc transfer function in DCM

V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

A simple flyback circuit without parasitic elements

12.0 Ipeak / N Id(t)

DCM (core reset)

12.644 VDS is back

2.00 Ipeak / N Id(t)

The coupling in a transformer is not perfect

For a two-winding transformer, the model is simple:

The switch closes: The switch opens:

vdrain, v(9) in volts

Reflected Vout 7.940m 7.944m 7.949m

The clamp is made by a low impedance voltage source

1.002m 1.008m 1.015m 1.021m 1.028m

Simple current approach:

• 2nd power approach 1

kC ⋅ (Vout + V f ,diode ) Vclamp

Reflected voltage Vr at primary from secondary

Vr Vout 2 ⋅ L prim ⋅ Fsw

The average shared

= (1 − DC max ) ⋅  I sec, peak − I sec, peak ⋅ ∆I sec + 

Current sensing resistor Rsense selection

I Cout ,rms = I sec, rms − I out

It is recommended to use more parallel

RCD clamp – 1st iteration: better EMI response

2 ⋅ Vleak ⋅ Vclamp Vclamp

Vclamp These values need to be optimized for the

Power loss [W] 1.50

Note from experiments:

89.50% The optimum ratio is

Optimum ratio Decreasing the Ns/Np

Decreasing the Ns/Np

• Ways to improve efficiency:

– Lower the switching frequency FSW frequency foldback at light loads

– Lower the Drain voltage at turn-off valley switching

• New SR controller NCP4303

verr, ramp in volts

10.0u 30.0u 50.0u 70.0u 90.0u

In voltage-mode, one compares the error voltage to a fix ramp

The inductor current is sensed for safety only

S 1.31m 1.65m 1.99m

-500m -1.00 Inductor peak current

In current-mode, the error voltage fixes the peak current

The sense resistor provides a pulse-by-pulse current limit

A flyback auxiliary winding supplies

High startup current to

Power ON Current Source turns ON Vcc is rising; no output pulses